Single-channel Digital Decimation Filter Multiple On-chip Coeffic
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CS5378 Low-power Single-channel Decimation Filter
Single-channel Digital Decimation Filter
Multiple On-chip Coefficient Sets Programmable Coefficients Custom Filters Synchronous Operation
Description
CS5378 multi-function digital filter utilizing lowpower signal processing architecture achieve efficient filtering delta-sigma-type modulator. combining CS5378 with CS3301/02 differential amplifier, CS5371 modulator, CS4373 test DAC, synchronous high-resolution measurement system designed quickly easily. Digital filter coefficients CS5378 filters included on-chip simple setup, they programmed custom applications. Selectable digital filter decimation ratios produce output word rates from 4000 SPS, resulting measurement bandwidths ranging from 1600 down when using on-chip coefficient sets. CS5378 includes integrated peripherals simplify system design: low-jitter standard clock manchester inputs, offset gain corrections, test stream generator, time break controller, eight general-purpose pins.
Integrated Clock Generation
1.024 MHz, 2.048 MHz, 4.096 Input Standard Clock Manchester Input
Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 200, 125, 100,
Digital Gain Offset Corrections Test Bit-stream Generator
Sine Wave Impulse Output Mode
Time Break Controller, General-purpose Microcontroller EEPROM Configuration Small-footprint, 28-pin SSOP Package Power Consumption
Flexible Power Supplies
Interface PLL: Digital Logic Core:
ORDERING INFORMATION page
VDDCORE
SS:EECS
VDDPAD
VDDPLL
DRDY
MISO
MOSI
PLL, Clock Generation Serial Interface Reset, Synchronization
MCLK RESET SYNC MSYNC TIMEB
Time Break Controller Decimation Filtering Engine
Test Stream Controller
TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0
Modulator Data Interface
GPIO General Purpose
MDATA
MFLAG
GNDPAD
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved)
GNDCORE
GNDPLL
DS639F1
CS5378
TABLE CONTENTS
General Description.
1.1. 1.2. 1.3. 1.4. Digital Filter Features Integrated Peripheral Features System Level Features Configuration Interface.
Characteristics Specifications.
Specified Operating Conditions Absolute Maximum Ratings Thermal Characteristics Digital Characteristics Power Consumption. Switching Characteristics
System Design with CS5378
3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. Power Supplies Reset Control Clock Generation Synchronization System Configuration. Digital Filter Operation Data Collection. Integrated peripherals
Power Supplies
4.1. Descriptions 4.2. Bypass Capacitors 4.3. Power Consumption.
Reset Control.
5.1. Descriptions 5.2. Reset Self-Tests. 5.3. Boot Configurations
Clock Generation
6.1. 6.2. 6.3. 6.4. 7.1. 7.2. 7.3. 7.4. 7.5. 8.1. 8.2. 8.3. 8.4. 8.5. Descriptions Mode Select Synchronous Clocking Master Clock Jitter Skew. Description MSYNC Generation Digital Filter Synchronization Modulator Synchronization Test Stream Synchronization Descriptions EEPROM Hardware Interface EEPROM Organization EEPROM Configuration Commands Example EEPROM Configuration
Synchronization
Configuration EEPROM
Configuration Microcontroller
DS639F1
CS5378
9.1. 9.2. 9.3. 9.4. 9.5. 10.1. 10.2. 10.3. 10.4. 10.5. Descriptions Microcontroller Hardware Interface Microcontroller Serial Transactions Microcontroller Configuration Commands Example Microcontroller Configuration Descriptions Modulator Clock Generation Modulator Synchronization. Modulator Data Input Modulator Flag Input
Modulator Interface
Digital Filter Initialization
11.1. Filter Coefficient Selection 11.2. Filter Configuration Options
SINC Filter
12.1. 12.2. 12.3. 12.4. 13.1. 13.2. 13.3. 13.4. 13.5. 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. SINC1 Filter SINC2 Filter SINC3 Filter SINC Filter Synchronization FIR1 Filter FIR2 Filter On-Chip Coefficients Programmable Coefficients Filter Synchronization Architecture IIR1 Filter IIR2 Filter IIR3 Filter On-Chip Coefficients Programmable Coefficients Filter Synchronization
Filter
Filter
Gain Offset Correction
15.1. Gain Correction 15.2. Offset Correction 15.3. Offset Calibration
Serial Data Interface
16.1. Descriptions 16.2. Serial Data Format 16.3. Serial Data Transactions
Test Stream Generator.
17.1. 17.2. 17.3. 17.4. 17.5. 17.6. Descriptions Architecture Configuration Data Source Sine Wave Output Impulse Output.
DS639F1
CS5378
17.7. Loopback Testing. 17.8. Synchronization
Time Break Controller
18.1. Description 18.2. Time Break Operation 18.3. Time Break Delay.
General Purpose
19.1. 19.2. 19.3. 19.4. 19.5. Descriptions GPIO Architecture GPIO Registers GPIO Input Mode GPIO Output Mode
Register Summary.
20.1. Registers 20.2. Digital Filter Registers
Description Package Dimensions Ordering Information Environmental, Manufacturing, Handling Information Revision History
LIST FIGURES
Figure CS5378 Block Diagram. Figure Digital Filtering Stages Figure Coefficient Selection Word Figure MOSI Write Timing Slave Mode Figure MISO Read Timing Slave Mode. Figure Serial Data Read Timing. Figure SYNC, MCLK, MSYNC, MDATA Interface Timing. Figure Output Data Timing. Figure Single-Channel System Block Diagram Figure Power Supply Block Diagram Figure Reset Control Block Diagram Figure Clock Generation Block Diagram Figure Synchronization Block Diagram Figure EEPROM Configuration Block Diagram Figure EEPROM Serial Read Transactions Figure Kbyte EEPROM Memory Organization Figure Serial Interface Block Diagram Figure Microcontroller Serial Transactions. Figure Registers Figure Modulator Data Interface Figure Digital Filter Stages. Figure Coefficient Selection Word Figure SINC Filter Block Diagram Figure SINC Filter Stages Figure Filter Block Diagram. Figure Filter Stages DS639F1
CS5378
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure FIR1 Coefficients FIR2 Linear Phase Coefficients FIR2 Minimum Phase Coefficients Filter Block Diagram Filter Stages Gain Offset Correction Serial Data Interface Block Diagram. 32-bit Serial Data Format Port Transaction Test Stream Generator Block Diagram Time Break Block Diagram GPIO Block Diagram. Control Register SPICTRL Command Register SPICMD Data Register SPIDAT1 Data Register SPIDAT2 Hardware Configuration Register CONFIG. GPIO Configuration Register GPCFG Filter Configuration Register FILTCFG Gain Correction Register GAIN. Offset Correction Register OFFSET Time Break Counter Register TIMEBRK Test Stream Configuration Register TBSCFG. Test Stream Gain Register TBSGAIN User Defined System Register SYSTEM1 Hardware Version Register VERSION Self Test Result Register SELFTEST CS5378 Assignments
LIST TABLES
Table Microcontroller EEPROM Configuration Commands Table Configurations Using On-Chip Data. Table Digital Filter Registers Table BOOT Mode Reset Configurations Table Mode Selections Table Maximum EEPROM Configuration. Table EEPROM Boot Configuration Commands Table Example EEPROM File Table Microcontroller Boot Configuration Commands Table Example Microcontroller Configuration Table SINC Filter Configurations Table SINC1 SINC2 Filter Coefficients Table SINC3 Filter Coefficients Table Filter Characteristics Table SINC Group Delay Table Minimum Phase Group Delay Table Filter Characteristics. Table Filter Coefficients Table Configurations Using On-Chip Data. Table Impulse Characteristics
DS639F1
CS5378
VDDCORE
SS:EECS
VDDPAD
VDDPLL
DRDY
MISO
MOSI
PLL, Clock Generation Serial Interface Reset, Synchronization
MCLK RESET SYNC MSYNC TIMEB
Time Break Controller Decimation Filtering Engine
Test Stream Controller
TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0
Modulator Data Interface
GPIO General Purpose
MDATA
MFLAG
GNDPAD
Figure CS5378 Block Diagram
GENERAL DESCRIPTION
CS5378 single channel digital filter with integrated system peripherals. Figure illustrates simplified block diagram CS5378. SPS. Flexible digital filter configuration. (See Figure Cascaded SINC, FIR, filters with selectable output stage. Linear minimum phase low-pass filter coefficients included. Butterworth high-pass filter coefficients included. coefficients programmable create custom filter response.
Digital Filter Single channel decimation filter CS5371 modulator. Synchronous operation simultaneous sampling multi-sensor systems. Internal synchronization digital filter phase external SYNC signal.
Output word rates, including bandwidth rates. Standard output rates: 4000, 2000, 1000, 500, 333, SPS. bandwidth rates: 200, 125, 100,
Digital gain correction normalize sensor gain. Digital offset correction calibration. Offset correction remove measurement
DS639F1
GNDCORE
GNDPLL
CS5378
Modulator Input
Sinc Filter 64000
FIR1
FIR2
IIR1 Order
IIR2
Order
Gain Offset Corrections
Output High Speed Serial Interface Output Word Rate from 4000 Figure Digital Filtering Stages
offset. Calibration engine automatic calculation offset correction factor.
Impulse output mode transfer function characterization.
Time break controller record system timing information. Dedicated status output data stream. Programmable output delay match system group delay.
Integrated Peripheral jitter generate local clocks. 1.024 MHz, 2.048 MHz, 4.096 standard clock manchester encoded input.
Synchronous operation simultaneous sampling multi-sensor systems. MCLK MSYNC output signals synchronize external components. Asynchronous operation direct connection system telemetry. Internal 8-deep data FIFO flexible output timing. Selectable 24-bit data only 32-bit status+data output.
General Purpose (GPIO) pins local hardware control.
System Level Flexible configuration options. Configuration 'on-the-fly' microcontroller system telemetry. Fixed configuration stand-alone boot EEPROM. OWR. standby mode. Separate digital logic core, telemetry I/O,
High speed serial data output.
power consumption.
Digital test stream signal generator suitable CS4373 test DAC. Sine wave output mode testing total harmonic distortion.
Flexible power supply configurations.
DS639F1
CS5378
power supplies. Telemetry interfaces operate from Digital logic core operates from Total footprint plus three bypass capacitors. tion during operation. EEPROM boot sets fixed operational configuration.
Configuration commands written through serial interface. (See Table Standardized microcontroller interface using registers. (See Table Commands write digital filter registers filter coefficients. Digital filter registers hardware configuration options.
Small 28-pin SSOP package.
Configuration Interface
Configuration from microcontroller standalone boot EEPROM. Microcontroller boot permits reconfigura-
DS639F1
CS5378
Microcontroller Boot Configuration Commands
Name WRITE REGISTER READ REGISTER WRITE COEFFICIENTS WRITE COEFFICIENTS 24-bit 000000 000001 000002 000003 000004 DAT1 24-bit [DATA] FIR1 (FIR COEF) COEF DAT2 24-bit DATA FIR2 (FIR COEF) Description Operation Write Digital Filter Register Read Digital Filter Register Write Custom Coefficients Write Custom Coefficients
WRITE COEFFICIENTS FILTER START FILTER STOP
000005 000006 000007 000008 000009
On-Chip Coefficients Operation Operation Start Digital Filter Operation Stop Digital Filter Operation
EEPROM Boot Configuration Commands
Name WRITE REGISTER WRITE COEFFICIENTS 8-bit DATA 24-bit DATA FIR1 FIR2 (FIR COEF) COEF Operation Write Digital Filter Register Write Custom Coefficients Description
WRITE COEFFICIENTS
Write Custom Coefficients
WRITE COEFFICIENTS FILTER START
On-Chip Coefficients Operation Operation Start Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words this type written.
Table Microcontroller EEPROM Configuration Commands
DS639F1
CS5378
Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
FIR2
FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 2000 1000
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 2000 1000
Bits 0000 0001 Bits 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase FIR2 Coefficients Linear Phase Minimum Phase
Figure Coefficient Selection Word
Test Stream Characteristic Equation: (Signal Freq) Data) (Interpolation Output Rate Example: (31.25 (1024) (0x07
Signal Frequency (TBSDATA) 10.00 10.00 25.00 25.00 31.25 31.25 50.00 50.00 125.00 125.00
Output Rate (TBSCLK)
Output Rate Selection (RATE)
Interpolation Selection (INTP) 0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table Configurations Using On-Chip Data
DS639F1
CS5378
Registers
Name SPICTRL SPICMD SPIDAT1 SPIDAT2 Addr. Type Bits Control Command Data Data Description
Digital Filter Registers
Name CONFIG RESERVED GPCFG RESERVED FILTCFG GAIN RESERVED OFFSET RESERVED TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST Addr. 01-0D 0F-1F 22-24 26-28 Type Bits Reserved GPIO[7:0] Direction, Pull-up Enable, Data Reserved Digital Filter Configuration Gain Correction Reserved Offset Correction Reserved Time Break Delay Test Stream Configuration Test Stream Gain User Defined System Register User Defined System Register Hardware Version Self-Test Result Code Description Hardware Configuration
Table Digital Filter Registers
PLL[2:0]
Mode Selection Reset 32.768 clock input (PLL bypass). 1.024 clock input. 2.048 clock input. 4.096 clock input. 32.768 clock input (PLL bypass). 1.024 manchester input. 2.048 manchester input. 4.096 manchester input.
BOOT
Mode Selection Reset EEPROM boot Microcontroller boot
Configuration Note: States PLL[2:0] BOOT pins latched immediately after reset select modes. These pins have weak (~100 pull-up resistor enabled default. external pull-down required condition.
Table BOOT Mode Reset Configurations
DS639F1
CS5378
CHARACTERISTICS SPECIFICATIONS
characteristics specifications guaranteed over Specified Operating Conditions. Typical performance characteristics specifications derived from measurements taken nominal supply voltages 25°C. GND, GND1, GND2 voltages with respect
SPECIFIED OPERATING CONDITIONS
Parameter Logic Core Power Supply Power Supply Power Supply Ambient Operating Temperature Industrial (-IQ) Symbol VDDCORE VDDPLL VDDPAD 2.375 3.135 3.135 5.25 5.25 5.25 Unit
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supplies Symbol Logic Core VDDCORE VDDPLL VDDPAD (Note (Note (Note IOUT VIND TSTG -0.3 -0.3 -0.3 -0.3 VDD+0.3 Units
Input Current, Except Supplies Input Current, Power Supplies Output Current Power Dissipation Digital Input Voltages Ambient Operating Temperature (Power Applied) Storage Temperature Range
Transient currents will cause latch-up.
DS639F1
CS5378
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction Ambient Thermal Impedance (4-Layer PCB) Ambient Operating Temperature (Power Applied) Symbol Unit
DIGITAL CHARACTERISTICS
Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Drive Voltage Low-Level Output Drive Voltage Rise Times, Digital Inputs Fall Times, Digital Inputs Rise Times, Digital Outputs Fall Times, Digital Outputs Input Leakage Current 3-State Leakage Current Digital Input Capacitance Digital Output Capacitance (Note Iout Iout Symbol tRISE tFALL tRISE tFALL COUT Unit
Notes: Maximum leakage pins with pull-up resistors (RESET, SS:EECS, GPIO, MOSI, SCK) ±250
rise fallo
llin
0.90 0.10
0.90 0.10
POWER CONSUMPTION
Parameter Operational Power Consumption 1.024 Digital Filter Clock 2.048 Digital Filter Clock 4.096 Digital Filter Clock 8.192 Digital Filter Clock Standby Power Consumption Digital Filter Clock, Filter Stopped PWRS PWR1 PWR2 PWR4 PWR8 Symbol Unit
DS639F1
CS5378
SWITCHING CHARACTERISTICS
Serial Configuration Interface Timing (External Master)
SS:EECS
MOSI
SCLK
Figure MOSI Write Timing Slave Mode
SS:EECS MISO
SCLK
Figure MISO Read Timing Slave Mode
Parameter MOSI Write Timing SS:EECS Enable Valid Latch Clock Data Set-up Time Prior Rising Data Hold Time After Rising High Time Time Falling Prior SS:EECS Disable MISO Read Timing Falling Data High Time Time SS:EECS Rising MISO Hi-Z
Symbol
Unit
DS639F1
CS5378
SWITCHING CHARACTERISTICS
Serial Data Interface Timing
DRDY
MISO
Figure Serial Data Read Timing
Parameter DRDY Falling Edge Rising Falling Data High Time Time Final Falling DRDY Rising
Symbol
Unit
DS639F1
CS5378
SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, MDATA
SYNC
MCLK
MSYNC tmsd MDATA
tmsh
tmsd Data1 Data2
Note: SYNC input latched MCLK rising edge. MSYNC output triggered MCLK falling edge.
fMCLK 2.048 1.024
tmsd TMCLK tmsh TMCLK
tmsd tmsh
tmsd tmsh
Figure SYNC, MCLK, MSYNC, MDATA Interface Timing
Parameter Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter Synchronization after SYNC rising MSYNC Setup Time MCLK rising MCLK rising Valid MDATA MSYNC falling MCLK rising (Note (Note
Symbol tRISE tFALL SYNC tmss tmdv tmsf
32.768
Unit
Notes: bypass mode. generates 32.768 master clock when enabled. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.
DS639F1
CS5378
SWITCHING CHARACTERISTICS
Test Stream (TBS)
TBSDATA
MCLK
Note: Example timing shown output rate programmable delays.
Figure Output Data Timing
Parameter Data Output Timing Data Rate Data Rising MCLK Rising Setup Time MCLK Rising Data Falling Hold Time (Note
Symbol
Unit kbps
TBSDATA delayed from full periods. timing diagram shows TBSDATA delay.
DS639F1
CS5378
CS5371
System Telemetry
Geophone Hydrophone Sensor
CS3301 CS3302
Modulator CS5378 Digital Filter
µController Configuration EEPROM
CS4373 Communication Interface Test
Figure Single-Channel System Block Diagram
SYSTEM DESIGN WITH CS5378
Figure illustrates simplified block diagram CS5378 single channel measurement system. differential sensor connected through CS3301/02 differential amplifiers CS5371 modulator, where analog digital conversion occurs. modulator's 1-bit output connects CS5378 MDATA input, where oversampled data decimated filtered 24-bit output samples programmed output rate. These output samples buffered into 8-deep data FIFO then passed system telemetry. System self tests performed connecting CS5378 test stream (TBS) generator CS4373 test DAC. Analog tests drive differential signals from CS4373 test into multiplexed inputs CS3301/02 amplifiers directly differential sensor. Digital loopback tests internally connect digital output directly CS5378 modulator input.
Power Supplies
system shown Figure typically operates from ±2.5 analog power supply digital power supply. CS5378 logic core powered from minimize power consumption, required.
Reset Control
System reset required only CS5378 device, standard active signal that generated power supply monitor microcontroller. Other system devices default powerdown state when CS5378 reset.
Clock Generation
included CS5378 generate internal 32.768 master clock from 1.024 MHz, 2.048 MHz, 4.096 standard clock manchester encoded input. Clock inputs other system devices driven clock outputs from CS5378.
DS639F1
CS5378
Synchronization
Digital filter phase analog sample timing modulator connected CS5378 synchronized rising edge SYNC pin. synchronization signal received identically CS5378 devices measurement network, synchronous sampling across network guaranteed.
Data Collection
Data collected from CS5378 through serial data interface. When data available, serial transactions automatically initiated transfer 24-bit data 32-bit status+data from output FIFO system telemetry. output FIFO eight data locations permit latency data collection.
System Configuration
Through serial configuration interface, filter coefficients digital filter register settings either programmed microcontroller automatically loaded from external EEPROM after reset. System configuration only required CS5378 device, other devices configured CS5378 General Purpose pins. registers digital filter, SYSTEM1 SYSTEM2 (0x2C, 0x2D), provided user defined system information. These general purpose registers that will hold 24-bit data values written them.
Integrated peripherals Test Stream (TBS)
digital signal generator built into CS5378 produces 1-bit sine wave impulse function. This digital test stream connected CS4373 test create high quality analog test signals internally looped back CS5378 MDATA input test digital filter data collection circuitry.
Time Break
Timing information recorded during data collection strobing TIMEB pin. dedicated flag sample status bits, high indicate during which measurement timing event occurred.
Digital Filter Operation
After analog digital conversion occurs modulator, oversampled 1-bit data read into CS5378 through MDATA pin. digital filter then processes data through enabled filter stages, decimating 24-bit words programmed output word rate. final 24-bit samples concatenated with 8-bit status words placed into output FIFO.
General Purpose (GPIO)
Eight general purpose pins available CS5378 system control. Each input output, high low, with internal pullup enabled disabled. CS3301/02, CS5371 CS4373 devices Figure configured simple settings controlled through CS5378 GPIO pins.
DS639F1
CS5378
VDDPAD GNDPAD
GNDCORE VDDCORE
GNDPLL VDDPLL
Figure Power Supply Block Diagram
POWER SUPPLIES
CS5378 three sets power supply inputs. supplies power pins device (VDDPAD), another supplies power logic core (VDDCORE) third supplies power (VDDPLL). power supplies determine maximum input output voltages when interfacing peripherals, logic core power supply largely determines power consumption CS5378 power supply powers internal circuitry.
VDDCORE, GNDCORE Pins
Sets operational voltage CS5378 logic core. VDDCORE driven with voltages from supply will minimize total power consumption.
Bypass Capacitors
Each power supply should bypassed with parallel 0.01 caps, single cap, placed close possible CS5378. Bypass capacitors should ceramic (X7R, C0G), tantalum, other good quality dielectric type.
Descriptions VDDPAD, GNDPAD Pins
Sets interface voltage microcontroller, system telemetry, modulator, test DAC. VDDPAD driven with voltages from
Power Consumption
Power consumption CS5378 depends primarily power supply voltage logic core (VDDCORE) programmed digital filter clock rate. Digital filter clock rates selected based required output word rate explained "Digital Filter Initialization" page
VDDPLL, GNDPLL Pins
Sets operational voltage internal CS5378 circuitry. driven with voltages from
DS639F1
CS5378
RESET
Self-Tests
BOOT
SELFTEST Register
EEPROM Boot
µController Boot
Figure Reset Control Block Diagram
RESET CONTROL
CS5378 reset signal active low. When released, series self-tests performed device either actively boots from external EEPROM enters idle state waiting microcontroller configuration. combined into SELFTEST register (0x2F), with 0x0AAAAA indicating passed. Self-tests require complete.
Boot Configurations
logic state BOOT after reset determines CS5378 actively reads configuration information from EEPROM enters idle state waiting microcontroller write configuration commands.
Descriptions RESET
Reset input, active low.
GPIO7:BOOT
Boot mode select, latched immediately following reset. Weak (~100 internal pull-up defaults high, external pull-down required low.
BOOT Reset Mode EEPROM boot Microcontroller boot
EEPROM Boot
When BOOT high after reset, CS5378 actively reads data from external serial EEPROM then begins operation specified configuration. Configuration commands data encoded EEPROM specified `Configuration EEPROM' section this data sheet, starting page
Reset Self-Tests
After RESET released before booting, series digital filter self-tests run. Results
Self-Test Type Program Data Program Data Execution Unit DS639F1 Pass Code 0x00000A 0x0000A0 0x000A00 0x00A000 0x0A0000 Fail Code 0x00000F 0x0000F0 0x000F00 0x00F000 0x0F0000
Microcontroller Boot
When BOOT after reset, CS5378 enters idle state waiting microcontroller write configuration commands initialize filter operation. Configuration commands data written specified `Configuration Microcontroller' section this data sheet, starting page
CS5378
PLL[2:0]
32.768
Clock Divider MCLK Generator
Internal Clocks MCLK Output
DSPCFG Register Figure Clock Generation Block Diagram
CLOCK GENERATION
CS5378 requires 32.768 master clock, which supplied directly from internal phase locked loop. This master clock used generate internal digital filter clock external modulator clock. internal will lock standard clock manchester encoded input signals. input type input frequency selected reset state mode select pins. weak internal pull-up resistor (~100 will hold mode select pins high default. force reset, external pulldown resistor should connected. Once state latched following reset, GPIO[4:6] pins funtion without affecting operation.
Synchronous Clocking
guarantee synchronous measurements throughout sensor network, system clock should distributed arrive nodes phase. distributed system clock either full 32.768 master clock, CS5378 create synchronous 32.768 clock from slower clock. ensure generated clock remains synchronous with network, CS5378 uses phase/frequency detector architecture.
PLL[2:0]
Descriptions
Clock input, standard clock manchester.
GPIO[4:6]:PLL[0:2] Pins
mode select, latched immediately after reset. Weak (~100 internal pull-ups default high, external pull-downs required low.
Mode
32.768 clock input (PLL bypass). 1.024 clock input. 2.048 clock input. 4.096 clock input. 32.768 clock input (PLL bypass). 1.024 manchester input. 2.048 manchester input. 4.096 manchester input.
Mode Select
CS5378 operational mode frequency selected immediately after reset based state PLL[0:2] pins. rising edge reset signal, digital high state PLL[0:2] pins latched used program clock input type frequency.
Table Mode Selections
DS639F1
CS5378
Master Clock Jitter Skew
Care must taken minimize jitter skew distributed system clock both parameters affect measurement performance. Jitter input clock causes jitter generated modulator clock, resulting sample timing errors increased noise. Skew between input clocks from node node creates sample timing offset, resulting systematic measurement errors reconstructed signal.
DS639F1
CS5378
SYNC MSYNC Generator
Digital Filter
Test Stream
MSEN
MSYNC Output
TSYNC
Figure Synchronization Block Diagram
SYNCHRONIZATION
CS5378 dedicated SYNC input that aligns internal digital filter phase generates external signal synchronizing modulator analog sampling. providing simultaneous rising edges SYNC pins multiple CS5378 devices, synchronous sampling across network guaranteed. phase. Filter convolutions restart, next output word available full sample period later. Repetitive synchronization supported when SYNC events occur exactly selected output rate. this case, re-synchronization will occur start convolution cycle when digital filter state machine already reset.
Description SYNC
Synchronization input, rising edge triggered.
Modulator Synchronization
MSYNC Generation
SYNC signal rising edge used generate retimed synchronization signal, MSYNC. MSYNC signal reinitializes internal digital filter phase driven onto MSYNC output phase align modulator analog sampling. MSEN digital filter CONFIG register (0x00) enables MSYNC generation. "Modulator Interface" page more information about MSYNC.
external MSYNC signal phase aligns modulator analog sampling when connected CS5371 MSYNC input. This ensures synchronous analog sampling relative MCLK. Repetitive synchronization modulators supported when SYNC events occur exactly selected output rate. this case, re-synchronization always occurs start analog sampling.
Test Stream Synchronization
When test stream generator enabled, MSYNC signal reset internal data pointer. This restarts test stream from first data point establish known output signal phase. TSYNC digital filter TBSCFG register (0x2A) enables synchronization test stream MSYNC. When TSYNC disabled, test stream phase affected MSYNC.
Digital Filter Synchronization
internal MSYNC signal resets digital filter state machine establish known digital filter
DS639F1
CS5378
HOLD
SS:EECS
CS5378
MISO MOSI
AT25640
Figure EEPROM Configuration Block Diagram
CONFIGURATION EEPROM
After reset, CS5378 reads state GPIO7:BOOT determine source configuration commands. BOOT high, CS5378 initiates serial transactions read configuration information from external EEPROM. read configuration commands data. 8-bit opcodes 16-bit addresses combined read back 8-bit configuration commands 24-bit configuration data. System design should include connection configuration EEPROM in-circuit reprogramming. CS5378 serial pins tri-state when inactive support external connections serial bus.
Descriptions
Pins required EEPROM boot listed here, other serial pins inactive.
Serial clock output, nominally 1.024 MHz.
EEPROM Organization
boot EEPROM holds 8-bit commands 24-bit data required initialize CS5378 into operational state. Configuration information starts memory location 0x10, with addresses 0x00 0x0F free manufacturing header information. first serial transaction reads 1-byte command from memory location 0x10 then, depending command type, reads multiple 3-byte data words complete command. Command data reads continue until `Filter Start' command recognized.
MISO
Serial data input pin. Valid rising edge SCK, transition falling edge.
MOSI
Serial data output pin. Valid rising edge SCK, transition falling edge.
SS:EECS
EEPROM chip select output, active low.
EEPROM Hardware Interface
When booting from EEPROM CS5378 actively performs serial transactions, shown Figure
DS639F1
CS5378
Instruction Read 0x03
Opcode
Address ADDR[15:0]
Definition Read data beginning address given ADDR.
Serial Read from EEPROM
READ MOSI 0x03 BYTE ADDR ADDR ADDR
MISO
DATA1 DATA2 DATA3 BYTE BYTE DATA
SS:EECS
Cycle
MOSI
MISO
SS:EECS
Figure EEPROM Serial Read Transactions
DS639F1
CS5378
Write Register 0x01
0000h 0010h Header 8-bit Command 24-bit Data 8-bit Command 24-bit Data 1FFFh EEPROM Manufacturing Information EEPROM Command Data Values This EEPROM command writes data value specified digital filter register. Digital filter registers control hardware peripherals filtering functions. "Digital Filter Registers" page definitions digital filter registers.
Sample Command:
Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240.
Figure Kbyte EEPROM Memory Organization
Write Coefficients 0x02
maximum number bytes that will written single configuration less than KByte Kbit), including command overhead: This EEPROM command writes custom coefficients FIR1 FIR2 filters. first data words number FIR1 FIR2 coefficients written. remaining data words concatenated FIR1 FIR2 coefficients. maximum coefficients written each filter, though available digital filter computation cycles will limit their practical size. "FIR Filter" page more information about filter coefficients.
Memory Requirement
Bytes
Digital Filter Registers (12) Coefficients (255+255) Coefficients (3+5) `Filter Start' Command Total Bytes
1537 1647
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
Table Maximum EEPROM Configuration
Supported serial configuration EEPROMs mode (0,0) compatible, 16-bit addresses, 8bit data, larger than KByte KBit). ATMEL AT25640, AT25128, similar serial EEPROMs recommended.
Write Coefficients 0x03
This EEPROM command writes custom coefficients stage filter. architecture number coefficients fixed, eight data words containing coefficient values always immediately follow command byte. coefficient write order a11, b10, b11, a21, a22, b20, b21, b22. "IIR Filter" page more information about filter coefficients.
EEPROM Configuration Commands
summary available EEPROM commands shown Table
DS639F1
CS5378
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104.
Sample Command:
Select IIR1 IIR2 low-cut coefficients, with FIR1 FIR2 linear phase highcut coefficients. Data word 0x002200.
Filter Start 0x07
This EEPROM command initializes starts digital filter. Measurement data becomes available full sample period after this command issued. data words required this EEPROM command.
Write Coefficients 0x04
This EEPROM command selects on-chip coefficients FIR1, FIR2, order, order filters digital filter. data word required select which internal coefficient sets use. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
Sample Command:
Name WRITE REGISTER WRITE COEFFICIENTS
8-bit
DATA 24-bit DATA FIR1 FIR2 (FIR COEF) COEF Operation
Description
Write Digital Filter Register Write Custom Coefficients
WRITE COEFFICIENTS
Write Custom Coefficients
WRITE COEFFICIENTS FILTER START
On-Chip Coefficients Operation Operation Start Digital Filter Operation
(DATA) indicates multiple words this type written.
Table EEPROM Boot Configuration Commands
DS639F1
CS5378
Example EEPROM Configuration
Table shows example EEPROM file minimal CS5378 configuration.
Addr
Data
Description header
Addr
Data
Description
Write TBSCFG Register
Write TBSGAIN Register
Write Coefficients
Filter Start
Write CONFIG Register
Write FILTCFG Register
Table Example EEPROM File
DS639F1
CS5378
Digital Filter Command Interpreter
Registers
Serial Logic
SS:EECS MOSI MISO
Figure Serial Interface Block Diagram
CONFIGURATION MICROCONTROLLER
After reset, CS5378 reads state GPIO7:BOOT determine source configuration commands. BOOT low, CS5378 receives configuration commands from microcontroller.
Microcontroller Hardware Interface
When booting from microcontroller CS5378 receives configuration commands configuration data through serial transactions, shown Figure 8-bit opcodes 8-bit addresses combined read write 24-bit configuration commands data. Microcontroller serial transactions require toggling SS:EECS CS5378 chip select writing serial clock input. Serial data input CS5378 MOSI pin, output MISO pin.
Descriptions
Pins required microcontroller boot listed here, other serial pins inactive.
SS:EECS
Slave select input pin, active low. Serial chip select input from microcontroller.
MOSI
Serial data input pin. Valid rising edge SCK, transition falling edge.
Microcontroller Serial Transactions
Microcontroller configuration commands written digital filter through registers. 24bit command 24-bit data words written registers single serial transaction. Some commands require additional data words through additional serial transactions complete. 9.3.1 opcodes microcontroller communicates with CS5378 serial port using standard 8-bit opcodes 8-bit address. standard `Read' `Write' opcodes listed Figure
MISO
Serial data output pin. Valid rising edge SCK, transition falling edge. Open drain output requiring pull-up resistor.
Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz.
DS639F1
CS5378
Instruction Write Read
Opcode 0x02 0x03
Address ADDR[7:0] ADDR[7:0]
Definition Write registers beginning address ADDR. Read registers beginning address ADDR.
Microcontroller Write Registers
SS:EECS
MISO
0x02
ADDR
Data1
Data2
DataN
MOSI
Microcontroller Read from Registers
SS:EECS
MISO
0x03
ADDR
MOSI
Data1
Data2
DataN
Cycle
MOSI
MISO
SS:EECS
Figure Microcontroller Serial Transactions DS639F1
CS5378
9.3.2 registers registers shown Figure 24-bit registers mapped into 8-bit register space high, mid, bytes. "SPI Registers" page definitions registers. 9.3.3 Serial transactions serial transaction registers starts with opcode, followed address, then some number data bytes written read starting that address. Typical serial write transactions require sending groups total bytes SPICMD SPIDAT1 registers: 5-byte write SPICMD 5-byte write SPIDAT1 8-byte write SPICMD, SPIDAT1 8-byte write SPIDAT1, SPIDAT2 11-byte write SPICMD, SPIDAT1, SPIDAT2 Typical serial read transactions require groups bytes, split between writing into MOSI reading from MISO. 3-byte read mid-byte SPICTRL 9.3.5 Polling E2DREQ transaction type that always performed matter delay from previous configuration command reading E2DREQ mid-byte SPICTRL register. 3-byte read transaction. MOSI: MISO: E2DREQ high MISO: E2DREQ E2DREQ reads high while serial transaction being processed. When low, digital filter ready receive serial transaction. MOSI: MISO: 5-byte read SPIDAT1 MOSI: MISO: 9.3.4 Multiple serial transactions Some configuration commands require multiple serial transactions complete. There must small delay between transactions CS5378 process incoming data. methods used ensure CS5378 ready receive next configuration command. Delay fixed period guarantee enough time command completed. Verify status E2DREQ reading SPICTRL register. When low, CS5378 ready next command.
Name SPICTRL SPICMD SPIDAT1 SPIDAT2
Addr.
Type
Bits Control Command Data Data
Description
Figure Registers DS639F1
CS5378
Microcontroller Configuration Commands
summary available microcontroller configuration commands listed Table
Read Register 0x02
This command reads specified digital filter register. register value requested first serial transaction, with register value copied SPIDAT1 read subsequent serial transaction.
Write Register 0x01
This configuration command writes specified digital filter register. Digital filter registers control hardware peripherals filtering functions. "Digital Filter Registers" page definitions digital filter registers.
Sample Command:
Read digital filter registers 0x00 0x20. Delay poll E2DREQ MOSI: MISO: Delay poll E2DREQ MOSI: MISO:
Sample Command:
Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240. Delay poll E2DREQ Delay poll E2DREQ
Name WRITE REGISTER READ REGISTER WRITE COEFFICIENTS WRITE COEFFICIENTS
24-bit 000000 000001 000002 000003 000004
DAT1 24-bit [DATA] FIR1 (FIR COEF) COEF
DAT2 24-bit DATA FIR2 (FIR COEF)
Description Operation Write Digital Filter Register Read Digital Filter Register Write Custom Coefficients Write Custom Coefficients
WRITE COEFFICIENTS FILTER START FILTER STOP
000005 000006 000007 000008 000009
On-Chip Coefficients Operation Operation Start Digital Filter Operation Stop Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words this type written.
Table Microcontroller Boot Configuration Commands
DS639F1
CS5378
Write Coefficients 0x03
This command writes custom coefficients FIR1 FIR2 filters. first data words number FIR1 FIR2 coefficients written. remaining data words concatenated FIR1 FIR2 coefficients. maximum coefficients written each filter, though available digital filter computation cycles will limit their practical size. "FIR Filter" page more information about filter coefficients. Delay poll E2DREQ Delay poll E2DREQ
Write Coefficients 0x05
This configuration command selects on-chip coefficients FIR1, FIR2, order, order filters digital filter. data word required select which internal coefficient sets use. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D. Delay poll E2DREQ Delay poll E2DREQ Delay poll E2DREQ
Sample Command:
Select IIR1 IIR2 low-cut coefficients, with FIR1 FIR2 linear phase highcut coefficients. Data word 0x002200. Delay poll E2DREQ
Filter Start 0x08
This command initializes starts digital filter. Measurement data becomes available full sample period after this command issued. data words required this command.
Write Coefficients 0x04
This command writes custom coefficients stage filter. architecture number coefficients fixed, eight coefficient values immediately follow this command. coefficient write order a11, b10, b11, a21, a22, b20, b21, b22. "IIR Filter" page more information about filter coefficients.
Sample Command:
Delay poll E2DREQ
Filter Stop 0x09
This command disables digital filter. Measurement data output stops immediately after this command issued. data words required this command.
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. Delay poll E2DREQ Delay poll E2DREQ
DS639F1
Sample Command:
Delay poll E2DREQ
CS5378
Example Microcontroller Configuration
Table shows example microcontroller transactions minimal CS5378 configuration.
Transaction
Data Delay poll E2DREQ Delay poll E2DREQ Delay poll E2DREQ Delay poll E2DREQ Delay poll E2DREQ
Description Write coefficients Write CONFIG Register Write FILTCFG Register Write TBSCFG Register Write TBSGAIN Register Filter Start
Table Example Microcontroller Configuration
DS639F1
CS5378
MCLK MSYNC MDATA MFLAG
MCLK MSYNC Generate Input
SYNC
SINC Filter
Filters
Filter
Offset Gain Correction
Output High Speed Serial Interface Output Rate 4000
Figure Modulator Data Interface
MODULATOR INTERFACE
CS5378 performs digital filtering type modulator. Signals from modulators connected through modulator data interface (MDI).
10.2 Modulator Clock Generation
MCLK output low-jitter, low-skew modulator clock generated from 32.768 master clock. MCLK typically operates 2.048 unless analog low-power modes require 1.024 modulator clock. MCLK rate selected MCLK output enabled bits digital filter CONFIG register (0x00). default MCLK disabled driven low.
10.1 Descriptions MCLK
Modulator clock output. Nominally 2.048 1.024 MHz.
MSYNC
Modulator synchronization signal output. Generated from SYNC input.
10.3 Modulator Synchronization
MSYNC output signal follows input SYNC pin. MSYNC phase aligns modulator sampling instant guarantee synchronous analog sampling across measurement network. MSYNC enabled CONFIG register (0x00). default SYNC inputs cause MSYNC output.
MDATA
Modulator data input, nominally kbit/s.
MFLAG
Modulator flag input. Driven high when modulator unstable analog over-range condition.
DS639F1
CS5378
10.4 Modulator Data Input
MDATA input expects 1-bit data rate. input rate selected CONFIG register (0x00). default, MDATA expected kHz. MDATA input one's density designed full scale positive full scale negative 14%, with absolute maximum over-range capability These inputs decimated filtered digital filter create 24bit samples output rate.
10.5 Modulator Flag Input
high MFLAG input signal indicates modulator become unstable analog overrange input signal. Once over-range signal reduced, modulator recovers stability MFLAG signal cleared. MFLAG input mapped status serial data output stream, associated with each sample when written. "Serial Data Interface" page more information MFLAG error serial data status byte.
DS639F1
CS5378
Modulator Input
SINC Filter 64000
FIR1
FIR2
IIR1 Order
IIR2 Order
Offset Gain Correction
Output High Speed Serial Data Interface Output Rate 4000
Figure Digital Filter Stages
DIGITAL FILTER INITIALIZATION
CS5378 digital filter consists three multistage sections: three stage SINC filter, stage filter, stage filter. initialize digital filter, coefficient sets selected using configuration commands, FILTCFG register (0x20) written select output filter stage, output word rate, number enabled channels. digital filter clock rate then selected writing CONFIG register (0x00). word, available coefficient sets each selection. Characteristics on-chip digital filter coefficients discussed `SINC Filter', `FIR Filter', `IIR Filter' sections this data sheet.
11.2 Filter Configuration Options
Digital filter parameters selected bits FILTCFG register (0x20), digital filter clock rate selected bits CONFIG register (0x00). 11.2.1 Output Filter Stage digital filter output data following stage filter chain. output filter stage selected FSEL bits FILTCFG register. Taking data from SINC FIR1 filter stages reduces overall decimation filter chain increases output rate, discussed next section. Taking data from FIR2, IIR1, IIR2, IIR3 results data selected rate.
11.1 Filter Coefficient Selection
Selection SINC filter coefficients required they selected automatically based programmed output word rate. Digital filter coefficients selected using `Write Coefficients' `Write Coefficients', `Write Coefficients' configuration commands. When writing coefficients from ROM, data word selects on-chip coefficient each filter stage. Figure shows format coefficient selection
DS639F1
CS5378
Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
FIR2
FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 2000 1000
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 2000 1000
Bits 0000 0001 Bits 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase FIR2 Coefficients Linear Phase Minimum Phase
Figure Coefficient Selection Word
11.2.2 Output Word Rate CS5378 digital filter supports output word rates (OWRs) between 4000 SPS. output word rate selected bits FILTCFG register. When taking data directly from SINC filter, decimation FIR1 FIR2 stages bypassed actual output word rate multiplied factor eight compared with register selection. When taking data directly from FIR1, decimation FIR2 stage bypassed actual output word rate multiplied factor two. Data taken from FIR2, IIR1, IIR2, IIR3 filtering stages output selected rate. 11.2.3 Digital Filter Clock digital filter clock rate programmable between 8.192 bits CONFIG register.
Computation Cycles
minimum digital filter clock rate configuration depends computation cycles required complete digital filter convolutions selected output word rate. configurations work maximum digital filter clock, lower clock rates consume less power.
Standby Mode
CS5378 placed low-power standby mode sending `Filter Stop' configuration command programming digital filter clock kHz. this mode digital filter idles, consuming minimal power until re-enabled later configuration commands.
DS639F1
CS5378
1-bit Input
order sinc1
order sinc2 stage1
order sinc2 stage2
order sinc2 stage3
order sinc2 stage4
order sinc3 stage1
order sinc3 stage2
order sinc3 stage3
order sinc3 stage4
order sinc3 stage5
order sinc3 stage6
order sinc3 stage7
24-bit Output
Figure SINC Filter Block Diagram
SINC FILTER
SINC filter primary purpose attenuate outof-band noise components from modulators. While doing they decimate 1-bit data into lower frequency 24-bit data suitable filters. SINC filter three cascaded sections, SINC1, SINC2, SINC3, which each made smaller stages shown Figure selected output word rate FILTCFG register automatically determines coefficients decimation ratios selected SINC filters.
12.2 SINC2 Filter
second section SINC2, multi-stage, variable order, variable decimation SINC filter. Depending selected output word rate FILTCFG register, different cascaded SINC2 stages enabled, shown Table
12.3 SINC3 Filter
last section SINC3, flexible multi-stage variable order, variable decimation SINC filter. Depending selected output word rate FILTCFG register, different SINC3 stages enabled, shown Table
12.1 SINC1 Filter
first section SINC1, single stage order fixed decimate SINC filter. This SINC filter decimates incoming 1-bit stream from modulators down rate.
12.4 SINC Filter Synchronization
SINC filter synchronized external system MSYNC signal, which generated from SYNC input. MSYNC signal sets reference time (time filter operations, SINC filter restarted phase align with this reference time.
DS639F1
CS5378
SINC1 Single stage, fixed decimate order decimate coefficients SINC2 Multi-stage, variable decimation Stage Stage Stage Stage order order order order decimate decimate decimate decimate coefficients coefficients coefficients coefficients
SINC3 Multi-stage, variable decimation Stage Stage Stage Stage Stage Stage Stage order order order order order order order decimate decimate decimate decimate decimate decimate decimate coefficients coefficients coefficients coefficients coefficients coefficients coefficients
Figure SINC Filter Stages
SINC filters
FIR2 Output Word Rate 4000 2000 1000 Setting SINC1 Decimation SINC2 Decimation SINC2 Stages SINC3 Decimation SINC3 Stages
0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
2,3,4 1,2,3,4 2,3,4 1,2,3,4 1,2,3,4 2,3,4 1,2,3,4 2,3,4 1,2,3,4 1,2,3,4
3,5,7 3,5,7 3,4,7 3,5,7 2,3,5,7 2,3,5,7 2,3,5,7 1,2,3,5,7
Table SINC Filter Configurations
DS639F1
CS5378
Filter Type SINC1 order decimate coefficients
System Function
Filter Coefficients 1190 1470 1750 2010 2226 2380 2460 2460 2380 2226 2010 1750 1470 1190
Filter Type SINC2 (Stage SINC2 (Stage order decimate coefficients
System Function
Filter Coefficients
SINC2 (Stage order decimate coefficients
SINC2 (Stage order decimate coefficients
Table SINC1 SINC2 Filter Coefficients
DS639F1
CS5378
Filter Type SINC3 (Stage SINC3 (Stage SINC3 (Stage order decimate coefficients
System Function
Filter Coefficients
SINC3 (Stage order decimate coefficients
SINC3 (Stage order decimate coefficients
SINC3 (Stage order decimate coefficients
SINC3 (Stage order decimate coefficients
Table SINC3 Filter Coefficients
DS639F1
CS5378
FIR1 Filter decimate
FIR2 Filter decimate
Figure Filter Block Diagram
FILTER
finite impulse response (FIR) filter block consists cascaded stages, FIR1 FIR2. compensates SINC filter droop creates low-pass corner block aliased components input signal. On-chip linear phase minimum phase coefficients selected using configuration command, coefficients programmed custom filter response.
13.2 FIR2 Filter
FIR2 filter stage decimate architecture. creates low-pass brick wall filter block aliased components input signal. on-chip linear minimum phase coefficient sets 126-tap, with maximum programmable coefficients. coefficients normalized 24-bit two's complement full scale, 0x7FFFFF. characteristic equation FIR2 convolution input values, X(n), filter coefficients, h(k), produce output value, [h(k)*X(n-k)] [h(k+1)*X(n-(k+1))]
13.1 FIR1 Filter
FIR1 filter stage decimate four architecture. compensates SINC filter droop flattens magnitude response pass band. on-chip linear minimum phase coefficient sets 48-tap, with maximum programmable coefficients. coefficients normalized 24-bit two's complement full scale, 0x7FFFFF. characteristic equation FIR1 convolution input values, X(n), filter coefficients, h(k), produce output value, [h(k)*X(n-k)] [h(k+1)*X(n-(k+1))]
13.3 On-Chip Coefficients
sets on-chip coefficients, linear phase minimum phase, available FIR1 FIR2. Performance on-chip coefficient sets very good, with excellent ripple stop band characteristics described Figure Table Which on-chip coefficient selected data word following `Write Coefficients' configuration command. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
DS639F1
CS5378
13.4 Programmable Coefficients
maximum coefficients programmed into FIR1 FIR2 create custom filter response. total number coefficients filter fundamentally limited available computation cycles digital filter, which itself determined digital filter clock rate. Custom filter sets should normalize maximum coefficient value 24-bit two's complement full scale, 0x7FFFFF, scale other coefficients accordingly. maintain maximum internal dynamic range, CS5378 filter performs double precision calculations with automatic gain correction scale final output. Custom coefficients uploaded using `Write Coefficients' configuration command. "EEPROM Configuration Commands" page "Microcontroller Configuration Commands" page information about writing custom coefficients.
13.5 Filter Synchronization
FIR1 FIR2 filters synchronized external system MSYNC signal, which generated from SYNC input. MSYNC signal sets reference time (time filter operations, filters restarted phase align with this reference time.
DS639F1
CS5378
FIR1 Single stage, fixed decimate Coefficient linear phase decimate coefficients Coefficient minimum phase decimate coefficients SINC droop compensation filter FIR2 Single stage, fixed decimate Coefficient linear phase decimate coefficients Coefficient minimum phase decimate coefficients Brick wall low-pass filter, flat
Combined SINC digital filter specifications Passband ripple less than 0.01 below Transition band frequency 42.89% Stopband attenuation greater than above
Figure Filter Stages
SINC filters
FIR2 Output Word Rate 4000 2000 1000 SINC Decimation 1280 1600 2560 3200 6400 12800 64000 FIR1 Decimation FIR2 Decimation Total Decimation 1024 1536 2048 2560 4096 5120 10240 12800 20480 25600 51200 102400 512000 Passband Ripple 0.0042 0.0045 0.0040 0.0041 0.0080 0.0064 0.0043 0.0046 0.0040 0.0040 0.0040 0.0040 0.0036 0.0036 0.0036 0.0029 Stopband Attenuation (dB) 130.38 130.38 130.42 130.42 130.45 130.43 130.44 130.42 130.43 130.43 130.44 132.98 130.43 130.43 130.43 134.31
Table Filter Characteristics
DS639F1
CS5378
Individual filter stage group delay IIR)
Decimation Ratios Stage Stages Stages 2,3,4 Stages 1,2,3,4 SINC3 Stage Stage Stages Stages Stages 3,5,7 Stages 3,4,7 Stages 2,3,5,7 Stages 1,2,3,5,7 FIR1 Coefficient Coefficient FIR2 Coefficient Coefficient 62.5 Figure 23.5 Figure 5,2,2 5,5,2 5,5,2,2 5,5,5,2,2 21,7 17,6,7 17,21,7 17,17,6,7 17,17,17,6,7 25.0 50.5 133.0 260.5 1310.5 2,2,2 2,2,2,2 Number Coefficients 5,6,7 5,5,6,7 Group Delay (Input Rate) 17.5 19.0 40.0
SINC1 SINC2
Cumulative linear phase group delay IIR)
FIR2 Output Word Rate 4000 2000 1000 SINC Output Group Delay (SINC Filter Input Rate) 41.5 85.5 169.5 337.5 553.5 721.5 885.5 1425.5 1701.5 3401.5 4341.5 6801.5 8421.5 16841.5 33681.5 168081.5 FIR1 Output Group Delay (SINC Filter Input Rate) 417.5 837.5 1673.5 3345.5 5065.5 6737.5 8405.5 13457.5 16741.5 33481.5 41941.5 66961.5 83621.5 167241.5 334481.5 1672081.5 FIR2 Output Group Delay (SINC Filter Input Rate) 4417.5 8837.5 17673.5 35345.5 53065.5 70737.5 88405.5 141457.5 176741.5 353481.5 441941.5 706961.5 883621.5 1767241.5 3534481.5 17672081.5 FIR2 Output Group Delay (FIR2 Output Word Rate) 34.5117 34.5215 34.5186 34.5171 34.5479 34.5398 34.5334 34.5355 34.5198 34.5197 34.5267 34.5196 34.5165 34.5164 34.5164 34.5158
Table SINC Group Delay
DS639F1
CS5378
Minimum phase group delay
FIR1 Minimum Phase Group Delay (Normalized frequency)
FIR2 Minimum Phase Group Delay (Normalized frequency)
Table Minimum Phase Group Delay
DS639F1
CS5378
Filter Type FIR1 (Coefficient pass, SINC compensation Linear phase decimate coefficients Filter Coefficients (normalized 24-bit) 1905 3834 5118 -14518 -39787 -67365 -69909 -19450 97434 258881 375562 332367 39864 -496361 -1084130 -1392827 -1053303 189436 2266428 4768946 7042723 8388607 3337 22258 88284 266742 655747 1371455 2502684 4031988 5783129 7396359 8388607 8325707 6988887 4531706 1507479 -1319126 -3207750 -3736028 -2980701 -1421498 237307 1373654 1711919 1322371
8388607 7042723 4768946 2266428 189436 -1053303 -1392827 -1084130 -496361 39864 332367 375562 258881 97434 -19450 -69909 -67365 -39787 -14518 5118 3834 1905 555919 -165441 -581479 -617500 -388985 -99112 114761 186557 141374 58582 -12664 -42821 -35055 -16792 7929 5926 2892 -1164 -538 -238
FIR1 (Coefficient pass, SINC compensation Minimum phase decimate coefficients
Figure FIR1 Coefficients
DS639F1
CS5378
Filter Type FIR2 (Coefficient pass, passband Linear phase decimate coefficients Filter Coefficients (normalized 24-bit)
-371 -870 -986 1786 2291 -2036 -943 2985 3784 -1458 -5808 -1007 7756 5935 -7135 -11691 3531 17500 4388 -20661 -15960 18930 29808 -9795 -42573 -7745 49994 33021 -47092 -62651 29702 90744 4436 -109189 -54172 109009 114154 -81993 -174452 22850 221211 68863 -238025 -187141 208018 318763 -116005 -443272 -49958 533334 298975 -553873 -642475 454990 1113788 -137179 -1854336 -766230 3875315 8388607 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 8388607 3875315 -766230 -1854336 -137179 1113788 454990 -642475 -553873 298975 533334 -49958 -443272 -116005 318763 208018 -187141 -238025 68863 221211 22850 -174452 -81993 114154 109009 -54172 -109189 4436 90744 29702 -62651 -47092 33021 49994 -7745 -42573 -9795 29808 18930 -15960 -20661 4388 17500 3531 -11691 -7135 5935 7756 -1007 -5808 -1458 3784 2985 -943 -2036 2291 1786 -986 -870 -371
Figure FIR2 Linear Phase Coefficients
DS639F1
CS5378
Filter Type FIR2 (Coefficient pass, passband Minimum phase decimate coefficients Filter Coefficients (normalized 24-bit)
4019 43275 235427 848528 2240207 4525758 7077833 8388607 6885673 2483461 -2538963 -4800543 -2761696 1426109 3624338 1820814 -1695825 -2885148 -605252 2135021 1974197 -630111 -2168177 -750147 1516192 1550127 -508445 -1686937 -437822 1308705 1069556 -657282 -1301014 -30654 1173754 579643 -803111 -895851 328399 962522 124678 -820948 -466657 545674 652827 -220448 -680495 -80886 578844 306445 -395302 -431004 181900 454403 15856 -395525 -166123 284099 253485 -152407 -277888 28526 250843 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 67863 -190800 -128546 114197 147750 -46352 -143269 -13290 114721 51933 -75952 -68746 38171 68492 -7856 -57526 -12540 41717 23334 -25516 -26409 11717 24246 -1620 -19248 -4610 13356 7526 -7887 -8016 3559 7023 -598 -5350 -1097 3579 1806 -2058 -1859 1558 -224 -1129 -152 -395 -290 -151
Figure FIR2 Minimum Phase Coefficients
DS639F1
CS5378
Order IIR1 -a11
Order IIR2 -a21
Order IIR3 implemented running both IIR1 IIR2 stages
-a22
Figure Filter Block Diagram
FILTER
infinite impulse response (IIR) filter block consists cascaded stages, IIR1 IIR2. creates high-pass corner block very low-frequency components input signal. On-chip IIR1 IIR2 coefficients selected using configuration command, coefficients programmed custom filter response. characteristic equations order include input value, output value, intermediate values, separated delay element (z-1). (-a11 b10) b11)
14.1 Architecture
architecture filter automatically determined when output filter stage selected FILTCFG register. Selecting order IIR1 filter bypasses order stage, while selecting order IIR2 filter bypasses order stage. Selection order IIR3 filter enables both order stages.
14.3 IIR2 Filter
order filter stage direct form filter with five coefficients: a21, a22, b20, b21, b22. Coefficients order inherently normalized two, should scaled 24-bit two's complement full scale, 0x7FFFFF. Normalization effectively divides order coefficients half relative input, requires modification characteristic equations. characteristic equations order include input value, output value, three intermediate values, each separated delay element (z-1). following
14.2 IIR1 Filter
order filter stage direct form filter with three coefficients: a11, b10, b11. Coefficients order inherently normalized one, should scaled 24-bit two's complement full scale, 0x7FFFFF.
DS639F1
CS5378
characteristic equations model operation order filter with unnormalized coefficients. (-a21 (-a22 b20) b21) b22) Internally, CS5378 uses normalized coefficients perform order filter calculation, which changes algorithm slightly. following characteristic equations model operation order filter when using normalized coefficients. (-a21 (-a22 W5)] [(W3 b20) b21) b22)] Which on-chip coefficient selected data word following `Write Coefficients' configuration command. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
14.6 Programmable Coefficients
maximum coefficients programmed into IIR1 IIR2 create custom filter response. Custom filter sets should normalize coefficients 24-bit two's complement full scale, 0x7FFFFF. maintain maximum internal dynamic range, CS5378 filter performs double precision calculations with automatic gain correction scale final output. Custom coefficients uploaded using `Write Coefficients' configuration command. "EEPROM Configuration Commands" page "Microcontroller Configuration Commands" page information about writing custom coefficients.
14.4 IIR3 Filter
order filter implemented running both order order filter stages. modeled cascading characteristic equations order order stages.
14.7 Filter Synchronization
filter synchronized external system directly, only indirectly through synchronization SINC filters. Because filters have `infinite' memory, discontinuity input data stream from synchronization event require significant time settle out. exact settling time depends size discontinuity filter coefficient characteristics.
14.5 On-Chip Coefficients
Five sets on-chip coefficients available IIR1 IIR2, each providing high-pass Butterworth response different output word rates. Characteristics on-chip coefficient sets described Figure Table
DS639F1
CS5378
IIR1 Single stage, decimation order decimation, coefficients Coefficient Coefficient Coefficient Coefficient Coefficient high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
IIR2 Single stage, decimation order decimation, coefficients Coefficient Coefficient Coefficient Coefficient Coefficient high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
IIR3 stage, decimation order decimation, coefficients (Combined IIR1 IIR2 filter responses) Coefficient Coefficient Coefficient Coefficient Coefficient 0,0: 1,1: 2,2: 3,3: 4,4: high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.20% 0.41% 0.82% 1.22% 1.63% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
Figure Filter Stages
filters
IIR1 Coeff Selection IIR1 Corner Frequency 0.15% 0.30% 0.60% 0.90% 1.20% IIR2 Coeff Selection IIR2 Corner Frequency 0.15% 0.30% 0.60% 0.90% 1.20% IIR3 Coeff Selection IIR3 Corner Frequency 0.2041% 0.4074% 0.8152% 1.2222% 1.6293%
Table Filter Characteristics
DS639F1
CS5378
Filter Type IIR1 (Coefficient order, high pass Corner 0.15% coefficients IIR1 (Coefficient order, high pass Corner 0.30% coefficients IIR1 (Coefficient order, high pass Corner 0.60% coefficients IIR1 (Coefficient order, high pass Corner 0.90% coefficients IIR1 (Coefficient order, high pass Corner 1.20% coefficients Filter Type IIR2 (Coefficient order, high pass Corner 0.15% coefficients System Function Filter Coefficients (normalized 24-bit) -8309916 8349262 -8349262
System Function
-8231957 8310282 -8310282
-8078179 8233393 -8233393
-7927166 8157887 -8157887
-7778820 8083714 -8083714
Filter Coefficients (normalized 24-bit) -8332704 4138771 4166445 -8332890 4166445 -8276806 4083972 4138770 -8277540 4138770 -8165041 3976543 4083972 -8167944 4083972 -8053350 3871939 4029898 -8059796 4029898 -7941764 3770088 3976539 -7953078 3976539
IIR2 (Coefficient order, high pass Corner 0.30% coefficients
IIR2 (Coefficient order, high pass Corner 0.60% coefficients
IIR2 (Coefficient Order, high pass Corner 0.90% coefficients
IIR2 (Coefficient order, high pass Corner 1.20% coefficients
Table Filter Coefficients DS639F1
CS5378
Input
SINC Filter
Filters
Filter
Gain Correction
Offset Correction
Output High Speed Serial Data Port Port) Output Rate 4000
Offset Calibration
Figure Gain Offset Correction
GAIN OFFSET CORRECTION
CS5378 digital filter apply gain offset corrections measurement data. Also, offset calibration algorithm automatically calculate offset correction value. gain correction value written GAIN registers (0x21), while offset correction value written OFFSET register (0x25). Gain offset corrections enabled USEGR USEOR bits FILTCFG register (0x20). When enabled, offset calibration algorithm will automatically calculate offset correction value write into OFFSET register. Offset calibration enabled writing ORCAL bits FILTCFG. gain correction value 24-bit two's complement with unity gain defined full scale, 0x7FFFFF. Gain correction always scales fractional value, never gain digital filter data greater than one. Output Value Data (GAIN 0x7FFFFF) Unity Gain: GAIN 0x7FFFFF Gain: GAIN 0x3FFFFF Zero Gain: GAIN 0x000000 Once GAIN register written, USEGR FILTCFG register enables gain correction.
15.2 Offset Correction
Offset correction CS5378 cancels bias measurement channel subtracting value OFFSET register (0x25) from digital filter output data word. offset correction value 24-bit two's complement with maximum positive value 0x7FFFFF,
15.1 Gain Correction
Gain correction CS5378 normalizes sensor gain multi-sensor networks. requires externally calculated correction value written into GAIN register (0x21).
DS639F1
CS5378
maximum negative value 0x800000. applying offset correction causes final result exceed 24-bit two's complement maximum, output data will saturate that maximum value. Output Data Input Data Offset Correction Positive Output Value 0x7FFFFF Negative Output Value 0x800000 Once OFFSET register written, USEOR FILTCFG register enables offset correction. FILTCFG register, with larger exponent values producing smoother averaging function that requires longer settling time, smaller values producing noisier averaging function that requires shorter settling time. Typical exponential values range from 0x05 0x0F, depending available settling time. characteristic equations offset calibration algorithm include input value, output value, summation value, YSUM, sample index, exponential value, EXP. Y(n) X(n) [YSUM(n-1) EXP] YSUM(n) Y(n) YSUM(n-1) Offset Correction YSUM Once bits written, ORCAL FILTCFG register enable offset calibration. When enabled, updated offset correction value automatically written OFFSET register. When offset calibration algorithm fully settled, ORCAL should cleared maintain final value OFFSET register.
15.3 Offset Calibration
offset calibration algorithm CS5378 automatically calculate offset correction value. When using offset calibration algorithm, background noise data should used input signal calculating offset measurement channel. offset calibration algorithm exponential averaging function that places increased weight more recent digital filter data. exponential weighting factor bits
DS639F1
CS5378
System Telemetry
Data Ready Clock Data
CS5378
DRDY MISO
Figure Serial Data Interface Block Diagram
SERIAL DATA INTERFACE
Once digital filtering complete, each 24-bit output sample combined with 8-bit status byte. These data words written 8-deep FIFO buffer then transmitted communications channel through high speed serial data interface.
MISO
Serial data output.
16.2 Serial Data Format
Serial data transactions transfer either 24-bit data words 32-bit status+data words, depending STAT CONFIG register. When transmitting status information, each 8-bit status byte MFLAG bit, time break bit, FIFO overflow encoded shown Figure
16.1 Descriptions DRDY
Data ready output signal, active low. Open drain output requiring external pull-up resistor.
Serial clock input.
MFLAG MFLAG
MFLAG status byte when signal received MFLAG pin. When
Status
Data
MFLAG
Modulator Modulator Error
Time Break Time Break
FIFO FIFO Overflow
Figure 32-bit Serial Data Format
DS639F1
CS5378
ceived, MFLAG next output word. "Modulator Interface" page more information about MFLAG. sticky, meaning persists indefinitely once set. Clearing requires sending `Filter Stop' `Filter Start' configuration commands reinitialize data FIFO.
Time Break
time break marks timing reference based rising edge into TIMEB pin. After programmed delay, status byte output sample. TIMEBRK digital filter register (0x29) programs sample delay output. "Time Break Controller" page more information about time break.
Conversion Data Word
lower 24-bits serial data word conversion sample specified channel. Conversion data 24-bit two's complement format.
16.3 Serial Data Transactions
CS5378 automatically initiates serial data transactions whenever data becomes available output FIFO driving DRDY low. Once serial data transaction initiated, serial clocks received into cause data output MISO, shown Figure When available data read from serial data FIFO, DRDY released.
FIFO Overflow
FIFO overflow indicates error condition serial data FIFO, digital filter data overwrites FIFO location containing data which been sent.
DRDY
MISO
Figure Port Transaction
DS639F1
CS5378
Digital Filter Data 24-bit TBSGAIN Register 24-bit Digital Modulator 1-bit TBSDATA
Figure Test Stream Generator Block Diagram
TEST STREAM GENERATOR
CS5378 test stream (TBS) generator creates sine wave impulse stream data drive external test DAC. digital output also internally connected MDATA inputs loopback testing digital filter.
17.3 Configuration
Configuration options generator through TBSCFG register (0x2A). Gain scaling generator output TBSGAIN register (0x2B).
17.1 Descriptions TBSDATA
Test stream 1-bit data output.
Interpolation Factor INTP[7:0]
Selects many times interpolator uses data point when generating output stream. Interpolation zero based represents greater than programmed register value.
MCLK
Test stream clock output.
Operational Mode TMODE
Selects between sine wave impulse output mode.
17.2 Architecture
test stream generator consists data interpolator digital modulator. receives periodic 24-bit data from digital filter create 1-bit data output TBSDATA pin. input data from digital filter scaled TBSGAIN register (0x2B). Maximum stable amplitude 0x04FFFF, with 0x04B000 approximately full scale CS4373 test DAC. full scale 1-bit output from generator defined minimum maximum one's density.
DS639F1
Output Rate RATE[2:0]
Selects TBSDATA output rate.
Synchronization TSYNC
Enables synchronization output phase MSYNC signal.
Loopback LOOP
Enables digital loopback from output MDATA inputs.
CS5378
Test Stream Characteristic Equation:
(Signal Freq) Data) (Interpolation Output Rate
Example: (31.25 (1024) (0x07
Signal Frequency (TBSDATA)
Output Rate (TBSCLK)
Output Rate Selection (RATE)
Interpolation Selection (INTP)
10.00 10.00 25.00 25.00 31.25 31.25 50.00 50.00 125.00 125.00
0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table Configurations Using On-chip Data
Enables test stream generator.
17.5 Sine Wave Output
When TMODE TBSCFG register low, generator operates sine wave mode. this mode, sine wave data from digital filter memory used create sine wave test signal that drive test DAC. Sine wave frequency output data rate calculated shown characteristic equation Table sine wave maximum one's density output from generator TBSGAIN register. TBSGAIN programmed maximum 0x04FFFF, with generator unstable higher amplitudes. CS4373 test DAC, gain value 0x04B000 produces approximately full scale sine wave output differential).
Data Delay DDLY[5:0]
Programs full period delays TBSDATA, maximum bits.
Gain TBSGAIN[23:0]
Scales amplitude sine wave output generated impulse. Maximum 0x04FFFF, nominal 0x04B000.
17.4 Data Source
on-chip 24-bit 1024 point digital sine wave stored CS5378 which will produce test signal frequencies listed Table Additional discrete test frequencies output rates programmed varying interpolation factor output rate.
DS639F1
CS5378
Test Stream Impulse Characteristics:
Interpolation Selection (INTP) Output Rate Selection (RATE) Pulse Width from CS4373 Gain Scale Factor (TBSGAIN) Pulse Height from CS4373
0xFF 0xFF 0xFF 0x7F 0x7F 0x7F
0x04B000 0x04B000 0x04B000 0x04B000 0x04B000 0x04B000
Table Impulse Characteristics
17.6 Impulse Output
TMODE TBSCFG high, generator operates impulse mode. this mode, value TBSGAIN sets amplitude generated impulse. Impulse amplitude period shown Table create maximum impulse from generator, TBSGAIN register should 0x04FFFF, INTP bits TBSCFG should also 0xFF. RATE bits should always produce data correct rate intended test DAC. rising edge TIMEB triggers impulse output. When impulse mode enabled TIMEB input received, generator uses negated TBSGAIN register repetitive input value. When rising edge recognized TIMEB pin, single positive TBSGAIN value written generator create impulse.
filter, data collection interface. Digital loopback testing expects data into MDATA input. mismatch generator full scale output MDATA full scale input results amplitude mismatch when testing loopback mode. generator outputs maximum one's density, while MDATA inputs expect maximum one's density from modulator, resulting measured full scale error approximately -3.6
17.8 Synchronization
When TSYNC TBSCFG register, MSYNC signal resets sine wave data pointer phase aligns signal output. Once digital filter settled, CS5378 devices receiving SYNC signal will have identical signal phase. "Synchronization" page more information about SYNC MSYNC signals. TSYNC clear, MSYNC effect data pointer change output phase will occur during synchronization.
17.7 Loopback Testing
Included part CS5378 test stream generator feedback path digital filter MDATA input. This loopback mode provides fully digital signal path test generator, digital
DS639F1
CS5378
TIMEB
TIMEBRK Delay Counter
Flag Serial Data Status Byte
Figure Time Break Block Diagram
TIME BREAK CONTROLLER
time break signal used mark timing events that occur during measurement. external signal sets flag status byte output sample mark when external event occurred. rising edge input TIMEB causes timing reference flag serial data status byte. When set, flag appears only output sample status byte. flag output delayed programming sample delay value into TIMEBRK digital filter register.
18.3 Time Break Delay
TIMEBRK register (0x29) sets sample delay between received rising edge TIMEB writing flag into serial data status byte. programmable sample counter compensate group delay through digital filters. When proper group delay value programmed into TIMEBRK register, flag will status byte measurement sample taken when timing reference signal received.
18.3.1 Step Input Group Delay simple method empirically measure step response group delay CS5378 measurement channel time break signal both timing reference input analog step input.
18.1 Description TIMEB
Time break input pin, rising edge triggered.
18.2 Time Break Operation
externally generated timing reference signal applied TIMEB initiates internal sample counter. After number output samples have passed, programmed TIMEBRK digital filter register (0x29), flag status byte serial data output word. flag automatically cleared subsequent data words, appears only output sample.
When rising edge received TIMEB with delay programmed into TIMEBRK register, flag next serial data status byte. same rising edge step input analog channel, propagating through digital filter appear rising edge measurement data. comparing timing status flag output rising edge measurement data, measurement channel group delay determined.
DS639F1
CS5378
GP_PULL
Pull Logic
GP_DATA
GPIO
GP_DIR
Figure GPIO Block Diagram
GENERAL PURPOSE
General Purpose (GPIO) block provides general purpose pins interface with external hardware. GP_PULL bits enable/disable internal pull-up resistor, GP_DATA bits output data value. After reset, GPIO pins default inputs with pull-up resistors enabled.
19.1 Descriptions GPIO[3:0] Pins
Standard GPIO pins.
19.4 GPIO Input Mode
When reading value from GP_DATA bits, returned data reports current state pins. externally driven high reads logical externally driven reads logical When GPIO used input, pull-up resistor should disabled save power isn't required.
GPIO[6:4]:PLL[2:0] Pins
Standard GPIO pins also used select mode after reset. Internal pull-ups default high, external pull-downs required low.
GPIO7:BOOT
Standard GPIO also used select boot mode after reset. Internal pull-up defaults high, external pull-down required low.
19.5 GPIO Output Mode
When GPIO programmed output with data value driven internal pull-up resistor automatically disabled. When programmed output with data value driven high pull-up resistor inconsequential. GPIO used open-drain output setting data value enabling pull-up, using GP_DIR direction bits control value. This open-drain output configuration uses internal pull-up resistor hold high when GP_DIR input, drives when GP_DIR output.
19.2 GPIO Architecture
Each GPIO configured input output, high low, with weak (~100 internal pull-up resistor enabled disabled. Figure shows structure bi-directional GPIO pin.
19.3 GPIO Registers
GPIO settings programmed GPCFG register. GP_DIR bits input/output mode,
DS639F1
CS5378
19.5.1 GPIO Reads Output Mode When reading GPIO pins GP_DATA register value always reports current state pins, value written output mode does necessarily read back same value. output mode written logical CS5378 attempts drive high. external device forces
low, read value reflects state returns logical Similarly, output written logical forced high externally, read value reflects state returns logical both cases CS5378 contention with external device resulting increased power consumption.
DS639F1
CS5378
REGISTER SUMMARY 20.1 Registers
CS5378 registers interface serial port digital filter.
Name Addr. Type Bits Description
SPICTRLH SPICTRLM SPICTRLL SPICMDH SPICMDM SPICMDL SPIDAT1H SPIDAT1M SPIDAT1L SPIDAT2H SPIDAT2M SPIDAT2L
Control Register, High Byte Control Register, Middle Byte Control Register, Byte Command, High Byte Command, Middle Byte Command, Byte Data High Byte Data Middle Byte Data Byte Data High Byte Data Middle Byte Data Byte
DS639F1
CS5378
20.1.1 SPICTRL 0x00, 0x01, 0x02
Figure Control Register SPICTRL
(MSB) -R/W -R/W1 -R/W -R/W -R/W -R/W -R/W -R/W
Address: 0x00 0x01 0x02
SMODF -R/W EMOP SWEF -R/W -R/W E2DREQ
defined; read Readable Writable Readable Writable
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
(LSB) -R/W
Bits bottom rows reset condition
definitions:
23:16 -reserved SMODF mode fault flag reserved External master operation progress flag write collision error flag reserved -reserved
14:13 EMOP
SWEF
10:9
E2DREQ External master digital filter request flag
DS639F1
CS5378
20.1.2 SPICMD 0x03, 0x04, 0x05
Figure Command Register SPICMD
(MSB) SCMD23 SCMD22 SCMD21 SCMD20 SCMD19 SCMD18 SCMD17 SCMD16
Address: 0x03 0x04 0x05
SCMD15 SCMD14 SCMD13 SCMD12 SCMD11 SCMD10 SCMD9 SCMD8
defined; read Readable Writable Readable Writable
SCMD7
SCMD6
SCMD5
SCMD4
SCMD3
SCMD2
SCMD1
(LSB) SCMD0
Bits bottom rows reset condition
definitions:
23:16 SCMD[23:16] Command High 15:8 Byte SCMD[15:8] Command Mid- 15:8 Byte SCMD[7:0] Command Byte
DS639F1
CS5378
20.1.3 SPIDAT1 0x06, 0x07, 0x08
Figure Data Register SPIDAT1
(MSB) SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16
Address: 0x06 0x07 0x08
SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8
defined; read Readable Writable Readable Writable
SDAT7
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
SDAT1
(LSB) SDAT0
Bits bottom rows reset condition
definitions:
23:16 SDAT[23:16] Data High Byte 15:8 SDAT[15:8] Data Middle Byte 15:8 SDAT[7:0] Data Byte
DS639F1
CS5378
20.1.4 SPIDAT2 0x09, 0x0A, 0x0B
Figure Data Register SPIDAT2
(MSB) SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16
Address: 0x09 0x0A 0x0B
SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8
defined; read Readable Writable Readable Writable
SDAT7
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
SDAT1
(LSB) SDAT0
Bits bottom rows reset condition
definitions:
23:16 SDAT[23:16] Data High Byte 15:8 SDAT[15:8] Data Middle Byte 15:8 SDAT[7:0] Data Byte
DS639F1
CS5378
20.2 Digital Filter Registers
CS5378 digital filter registers control hardware peripherals filtering functions.
Name Addr. Type Bits Description
CONFIG RESERVED GPCFG RESERVED FILTCFG GAIN RESERVED OFFSET RESERVED TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST
01-0D 0F-1F 22-24 26-28
Hardware Configuration Reserved GPIO[7:0] Direction, Pull-Up Enable, Data Reserved Digital Filter Configuration Gain Correction Reserved Offset Correction Reserved Time Break Delay Test Stream Configuration Test Stream Gain User Defined System Register User Defined System Register Hardware Version Self-Test Result Code
DS639F1
CS5378
20.2.1 CONFIG 0x00
Figure Hardware Configuration Register CONFIG
(MSB)23 -R/W -R/W -R/W -R/W -R/W DFS2 DFS1 DFS0
Address: 0x00
-R/W
-R/W
-R/W
-R/W
-R/W
MCKFS2
MCKFS1
MCKFS0
defined; read Readable Writable Readable Writable
STAT
-R/W
MCKEN2
MCKEN
MDIFS
-R/W
BOOT
(LSB)0 MSEN
Bits bottom rows reset condition
definitions:
23:19 -reserved 15:11 -reserved STAT Serial Data Status Byte Disabled (24-bit output) Enabled (32-bit output) MCLK/2 output enable Enabled Disabled MCLK output enable Enabled Disabled MDATA input frequency select reserved Boot source indicator Booted from EEPROM Booted from Micro MSYNC enable MSYNC generated MSYNC remains
18:16 [2:0]
Digital filter frequency select 111: Reserved 110: 8.192 101: 4.096 100: 2.048 011: 1.024 010: 001: 000:
10:8
MCKFS [2:0]
MCLK frequency select 111: reserved 110: reserved 101: 4.096 100: 2.048 011: 1.024 010: 001: reserved 000: reserved
MCKEN2
MCKEN
MDIFS
-BOOT
MSEN
DS639F1
CS5378
20.2.2 GPCFG 0x0E
Figure GPIO Configuration Register GPCFG
(MSB)
GP_DIR7
GP_DIR6
GP_DIR5
GP_DIR4
GP_DIR3
GP_DIR2
GP_DIR1
GP_DIR0
Address: 0x0E
GP_PULL7
GP_PULL6
GP_PULL5
GP_PULL4
GP_PULL3
GP_PULL2
GP_PULL1
GP_PULL0
defined; read Readable Writable Readable Writable
GP_DATA7
GP_DATA6
GP_DATA5
GP_DATA4
GP_DATA3
GP_DATA2
GP_DATA1
(LSB)
GP_DATA0
Bits bottom rows reset condition
definitions:
23:16 GP_DIR [7:0] GPIO direction Output Input 15:8 GP_PULL GPIO pullup resistor [7:0] Enabled Disabled GP_DATA GPIO data value [7:0]
Notes: GPIO[7] also used BOOT mode select after reset GPIO[6:4] also used mode select after reset.
DS639F1
CS5378
20.2.3 FILTCFG 0x20
Figure Filter Configuration Register FILTCFG
(MSB) -R/W -R/W -R/W EXP4 EXP3 EXP2 EXP1 EXP0
Address: 0x20
-R/W
ORCAL
USEOR
USEGR
-R/W
FSEL2
FSEL1
FSEL0
defined; read Readable Writable Readable Writable
DEC3
DEC2
DEC1
DEC0
-R/W
-R/W
-R/W
(LSB) -R/W
Bits bottom rows reset condition
definitions:
23:21 -reserved -ORCAL reserved OFFSET calibration Enable Disable DEC[3:0] Decimation selection (Output word rate) 0111: 0110: 0101: 0100: 0011: 0010: 0001: 0000: 1111: 1110: 1101: 1100: 1011: 1010: 1001: 1000: -4000 2000 1000
20:16 EXP[4:0] OFFSET calibration exponent
USEOR
OFFSET correction Enable Disable
USEGR
GAIN correction Enable Disable
10:8
reserved
reserved
FSEL[2:0] Output filter stage select 111: reserved 110: reserved 101: Order 100: Order 011: Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output
DS639F1
CS5378
20.2.4 GAIN 0x21
Figure Gain Correction Register GAIN
(MSB) GAIN23 GAIN22 GAIN21 GAIN20 GAIN19 GAIN18 GAIN17 GAIN16
Address: 0x21
GAIN15
GAIN14
GAIN13
GAIN12
GAIN11
GAIN10
GAIN9
GAIN8
defined; read Readable Writable Readable Writable
GAIN7
GAIN6
GAIN5
GAIN4
GAIN3
GAIN2
GAIN1
(LSB) GAIN0
Bits bottom rows reset condition
definitions:
23:16 GAIN[23:16] Gain Correction Upper Byte 15:8 GAIN[15:8] Gain Correction Middle Byte 15:8 GAIN[7:0] Gain Correction Lower Byte
DS639F1
CS5378
20.2.5 OFFSET 0x25
Figure Offset Correction Register OFFSET
(MSB) OFST23 OFST22 OFST21 OFST20 OFST19 OFST18 OFST17 OFST16
Address: 0x25
OFST15
OFST14
OFST13
OFST12
OFST11
OFST10
OFST9
OFST8
defined; read Readable Writable Readable Writable
OFST7
OFST6
OFST5
OFST4
OFST3
OFST2
OFST1
(LSB) OFST0
Bits bottom rows reset condition
definitions:
23:16 OFST[23:16] Offset Correction Upper Byte 15:8 OFST[15:8] Offset Correction Middle Byte 15:8 OFST[7:0] Offset Correction Lower Byte
DS639F1
CS5378
20.2.6 TIMEBRK 0x29
Figure Time Break Counter Register TIMEBRK
(MSB) TBRK23 TBRK22 TBRK21 TBRK20 TBRK19 TBRK18 TBRK17 TBRK16
Address: 0x29
TBRK15
TBRK14
TBRK13
TBRK12
TBRK11
TBRK10
TBRK9
TBRK8
defined; read Readable Writable Readable Writable
TBRK7
TBRK6
TBRK5
TBRK4
TBRK3
TBRK2
TBRK1
(LSB) TBRK0
Bits bottom rows reset condition
definitions:
23:16 TBRK[23:16] Time Break Counter 15:8 Upper Byte TBRK[15:8] Time Break Counter 15:8 Middle Byte TBRK[7:0] Time Break Counter Lower Byte
DS639F1
CS5378
20.2.7 TBSCFG 0x2A
Figure Test Stream Configuration Register TBSCFG
(MSB) INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0
Address: 0x2A
TMODE
RATE2
RATE1
RATE0
TSYNC
-R/W
-R/W
-R/W
defined; read Readable Writable Readable Writable
LOOP
DDLY5
DDLY4
DDLY3
DDLY2
DDLY1
(LSB) DDLY0
Bits bottom rows reset condition
definitions:
23:16 INTP[7:0] Interpolation factor 0xFF: 0xFE: 0x01: 0x00: (use once) TMODE Operational mode Impulse mode Sine Mode LOOP Loopback TBSDATA output MDATA inputs Enabled Disabled Test Stream Enabled Disabled
14:12 RATE[2:0]
TBSDATA TBSCLK output rate. 111: 2.048 110: 1.024 101: 100: 011: 010: 001: 000: Synchronization Sync enabled sync
TSYNC
DDLY[5:0]
TBSDATA output delay 0x3F: bits 0x3E: bits 0x01: 0x00: bits delay)
10:8
reserved
DS639F1
CS5378
20.2.8 TBSGAIN 0x2B
Figure Test Stream Gain Register TBSGAIN
(MSB) TGAIN23 TGAIN22 TGAIN21 TGAIN20 TGAIN19 TGAIN18 TGAIN17 TGAIN16
Address: 0x2B
TGAIN15
TGAIN14
TGAIN13
TGAIN12
TGAIN11
TGAIN10
TGAIN9
TGAIN8
defined; read Readable Writable Readable Writable
TGAIN7
TGAIN6
TGAIN5
TGAIN4
TGAIN3
TGAIN2
TGAIN1
(LSB) TGAIN0
Bits bottom rows reset condition
definitions:
23:16 TGAIN[23:16] Test Stream Gain 15:8 Upper Byte TGAIN[15:8] Test Stream Gain Middle Byte 15:8 TGAIN[7:0] Test Stream Gain Lower Byte
DS639F1
CS5378
20.2.9 SYSTEM1, SYSTEM2 0x2C, 0x2D
Figure User Defined System Register SYSTEM1
(MSB) SYS23 SYS22 SYS21 SYS20 SYS19 SYS18 SYS17 SYS16
Address: 0x2C
SYS15
SYS14
SYS13
SYS12
SYS11
SYS10
SYS9
SYS8
defined; read Readable Writable Readable Writable
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
(LSB) SYS0
Bits bottom rows reset condition
definitions:
23:16 SYS[23:16] System Register Upper Byte 15:8 SYS[15:8] System Register Middle Byte 15:8 SYS[7:0] System Register Lower Byte
DS639F1
CS5378
20.2.10 VERSION 0x2E
Figure Hardware Version Register VERSION
(MSB) TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
Address: 0x2E
defined; read Readable Writable Readable Writable
ROM7
ROM6
ROM5
ROM4
ROM3
ROM2
ROM1
(LSB) ROM0
Bits bottom rows reset condition
definitions:
23:16 TYPE [7:0] Chip Type CS5378 15:8 [7:0] Hardware Revision CS5378 [7:0] Version
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CS5378
20.2.11 SELFTEST 0x2F
Figure Self Test Result Register SELFTEST
(MSB) -R/W -R/W -R/W -R/W
Address: 0x2F
DRAM3
DRAM2
DRAM1
DRAM0
PRAM3
PRAM2
PRAM1
PRAM0
defined; read Readable Writable Readable Writable
DROM3
DROM2
DROM1
DROM0
PROM3
PROM2
PROM1
(LSB) PROM0
Bits bottom rows reset condition
definitions:
23:20 -reserved 15:12 DRAM [3:0] Data Test `A': Pass `F': Fail Program Test `A': Pass `F': Fail DROM [3:0] Data Test `A': Pass `F': Fail Program Test `A': Pass `F': Fail
19:16 [3:0]
Execution Unit Test `A': Pass `F': Fail
11:8
PRAM [3:0]
PROM [3:0]
DS639F1
CS5378
DESCRIPTION
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4:PLL0 GPIO5:PLL1 GPIO6:PLL2 TBSDATA VDDPAD GNDPAD MCLK MSYNC MDATA MFLAG
GPIO7:BOOT SS:EECS MOSI MISO DRDY GNDCORE VDDCORE TIMEB SYNC RESET GNDPLL VDDPLL
Figure CS5378 Assignments
Name
GPIO[0:3] GPIO[4:6]:PLL[0:2]
Number
Type
General Purpose Input Output Input Output Input Output
Description
General Purpose I/O. General Purpose with mode select. GPIO pins have weak (~100 internal pullups. mode selection latched immediately after reset. PLL[2:0] Reset Mode 32.768 clock input (PLL bypass). 1.024 clock input. 2.048 clock input. 4.096 clock input. 32.768 clock input (PLL bypass). 1.024 manchester input. 2.048 manchester input. 4.096 manchester input.
GPIO7:BOOT
Input Output
General Purpose with boot mode select. GPIO pins have weak (~100 internal pullups. Boot mode selection latched immediately after reset. BOOT Reset Mode EEPROM boot Microcontroller boot
DS639F1
CS5378
Name
TBSDATA MCLK MSYNC MDATA MFLAG RESET SYNC TIMEB DRDY MISO MOSI SS:EECS VDDPAD, GNDPAD VDDPLL, GNDPLL VDDCORE, GNDCORE
Number
Type
Test Stream Output Modulator Interface Output Output Input Input Telemetry Interface Input Input Input Input Serial Interface Output Input Output Input Output Input Output Input Supply Supply Supply Power Supplies
Description
Test stream data output. Modulator clock output. Modulator sync output. Modulator data input. Modulator flag input. Clock input. Reset, active low. Sync input. Time break input. Data ready, active low. Serial clock. Serial data, master slave out. Serial data, master slave Slave select with EEPROM chip select, active low. power supply. power supply. Logic core power supply.
DS639F1
CS5378
22.PACKAGE DIMENSIONS SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025
INCHES -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354
0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.15 1.75 -10.20 7.80 5.30 0.65 0.90
NOTE 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03
JEDEC MO-150 Controlling Dimension Millimeters
DS639F1
CS5378
23.ORDERING INFORMATION
Model Temperature Package
CS5378-IS CS5378-ISZ Lead Free
28-pin SSOP
24.ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days Days
CS5378-IS CS5378-ISZ Lead Free
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
25.REVISION HISTORY
Revision Date Changes
2004 2005
Initial "Preliminary Product" release. Added lead-free device ordering information. Added data.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
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DS639F1
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