DATA CTRL GA9103 ENDEC HOST customersupplied ENDEC* DATA DECODE STATUS

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DATA CTRL GA9103 ENDEC HOST customersupplied ENDEC* DATA DECODE STATUS

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DATA CTRL GA9103 ENDEC HOST customersupplied ENDEC* DATA DECODE STATUS (7*) GA9102 RECEIVER ENCODE DATA GA9101 TRANSMITTE
OPTICS COAX MEDIA
GA9101/ GA9102
REMOTE
LOOP
DATA
TriQuint's GA9101 Transmitter GA9102 Receiver, conjunction with GA9103 ENDEC, provide comprehensive electrical physical interface compliance with ANSI Fibre Channel Standard. conjunction with customer-supplied ENDEC, GA9101 GA9102 also provide fully-compliant interface with ESCONstandard. GA9101/GA9102 chip also used local-area network applications operating serial data rates 194.4 Megabaud (payload 155.52 Megabits/sec).
Fibre Channel Specification implemented standard channel interface either serial interconnection peripherals computers communication between computers. Fibre Channel links communicate over distances kilometers baud rates from132.8125 Megabaud 1.0625 Gigabaud. GA9101 GA9102 chips designed operate serial baud rates 194.4, 200.0, 265.625 Megabaud. Fibre Channel standard provides variety physical media data rates accommodate different cost/performance needs. framing protocol also provides flexibility, different implementations various features standard optimize system performance. GA9101 GA9102 Transmitter/Receiver chips designed using TriQuint-proprietary micron One-UpGaAs process. They interface either directly electrical medium fiber-optic interface. chips perform parallel-to-serial conversion, clock generation, receive clock/data recovery, serial-to-parallel conversion.
Along with fiber-optic module, this chip will provide complete FC-0 FC-1 solution Fibre Channel data link. Additionally, GA9101 GA9102 used serial SCSI, point-to-point serial communication, other network applications.
(*for ESCON)
MEDIA OPTICS COAX
Fibre Channel Transmitter Receiver
Features
Fully Fibre-Channel- ESCONTM-compatible
With fiber optics ENDEC, makes complete FC-0, FC-1 solution TTL-compatible 10-bit-wide data with 19.44, 20.00, 26.5625 byte clock Serial rate 194.4, 200.0, 265.625 Mbaud with on-chip clock generation On-chip clock data-recovery
Automatic byte alignment 8b/10b code
power dissipation chip (typical)
28-pin surface-mount package
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DATACOM PRODUCTS
GA9101/9102
ESCON interface provides optical-fiber communication link between devices main storage compatible computers implementing Enterprise Systems Architecture/390(ESA/390). customer-supplied ENDEC completes interface implementing data control encoding/decoding functions ESCON standard, typically also provides parity generate/check functions.
10-bit data GA9101 GA9102 chips interfaces with GA9103 CMOS ENDEC chip, which provides data, ordered-set, line-state encoding decoding functions described Fibre Channel Physical Layer standard (FC_PH). addition, performs 32-bit parity generate/check functions.
Functional Description GA9101 Transmitter
block synthesizes reference clock, XBITCLK, which derived from transmit clock input, TXCLK. frequency TXCLK 19.44, 20.00, 26.5625 MHz, which multiplied through internal Phase-Locked Loop obtain XBITCLK 194.4, 200.0, 265.625 MHz, respectively. XBITCLK provides timing transmit path. INPUT REGISTER loads 10-bit-wide input data, BTXD0.9, from ENDEC positive edge TXCLK. sends data PARALLEL-TOSERIAL block.
XMTLD signal strobes 10-bit-wide data into PARALLEL-TO-SERIAL CONVERTER functional block.
Figure GA9101 Transmitter
LOOPEN
SIG, SIGN
TXCLK (19.44, 20.00, 26.5625 MHz) XBITCLK XMTLD PARALLELTO-SERIAL CONVERTER INPUT REGISTER BTXD0.9 PECL-TO-TTL TRANSLATOR SIGDE
This data then serialized using XBITCLK from block. During serialization, most-significant bit, BTXD9, transmitted first, followed BTXD8 BTXD0. serial data sent using differential PECL driver. LOOPEN input signal selects transmit output shown table. unselected differential outputs forced logic state. SIGN differential PECL signals originate from optical receiver and, when active, indicate presence input optical signals. SIGDET activeHIGH signal derived from SIGN, through PECL-to-TTL TRANSLATOR.
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GA9101/9102
required Fibre Channel standard, GA9101/ GA9102 provide Loopback mode system test speed. When LOOPEN outputs GA9101 enabled transmitted inputs local receiver. normal mode (LOOPEN outputs transmitter enabled.
Table Transmit Output Selection
LOOPEN
Output
TLX,
Functional Description GA9102 Receiver
block receives inputs from differential inputs looped transmit outputs connected RLY. output goes CLOCK/DATA RECOVERY block. output selected LOOPEN outlined Table
Table Clock Recovery Input Selection
LOOPEN
CLOCK/DATA RECOVERY (CDR) circuit recovers clock information from input data serial transmission rates 194.4, 200.0, 265.625 Megabaud. block uses REFCLK frequency acquisition recovered clock, called CLOCK, which then used retime data,
Figure GA9102 Receiver
RLX,
LOOPEN
REFCLK (19.44, 20.00 26.5625 MHz)
Output
RLX,
SYNCEN DATA CLOCK/DATA RECOVERY (194.4 265.625 CLOCK MEGABAUD) SERIAL-TOPARALLEL CONVERTER OUTPUT REGISTER BRXD0.9 CLOCK GENERATE RXCLK (19.44, 20.00 26.5625 MHz) SYNC
removing jitter components. REFCLK present, initial receiver bit-synchronization time valid incoming data less than microseconds. receiver guaranteed have valid outputs after valid REFCLK serial data applied. Once synchronized, phase discontinuity occurs incoming data, receiver resynchronizes less than 2500 times, (with probability). recovered data converted 10-bit data word SERIAL-TO-PARALLEL CONVERTER (SPC) logic. CLOCK signal used CLOCK GENERATE blocks provide necessary timing. SERIAL-TO-PARALLEL CONVERTER block does serial-to-parallel conversion. parallel conversion bits, which corresponds
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DATACOM PRODUCTS
GA9101/9102
undecoded byte output 8b/10b coding scheme. output this block sent OUTPUT REGISTER. also generates SYNC signal upon receipt K28.5 byte, (001111 1010 110000 0101), provided SYNCEN HIGH. SYNC signal always SYNCEN inactive. When SYNCEN signal LOW, device retains previous alignment incoming K28.5 byte. SYNCEN signal useful when host decides disable byte alignment incoming K28.5. Using this pin, host decide align only under certain circumstances, such power loss word synchronization (see GA9103 ENDEC data sheet). SYNCEN also non-FibreChannel applications where byte alignment different pattern done interfacing logic.
Figure System Block Diagram Fibre Channel
TXCLK CTXD0.7 CTXP CTXC0,1 RESETN PERR RAWTx RAWRx TERR WSYNC BTXD0.9 GA9101 TRANSMITTER TLX, SIG, SIGN OPTICS/ COAX MEDIA GA9103 ENDEC LOOPEN REMOTE HOST SIGDET RLX, CRXS0.2 CRXD0.7 RXCLK CRXP ERROR RWSTART SYNC BRXD0.9 GA9102 RECEIVER RX,RY OPTICS/ COAX MEDIA FROM REMOTE HOST SYNCEN REFCLK
CLOCK GENERATE block used generate Receive Byte Clock, RXCLK. RXCLK 19.44, 20.00, 26.5625 MHz, corresponding serial baud rate 194.4, 200.0, 265.625 Megabaud, respectively. RXCLK realigned synchronous SYNC signal from SERIAL-TO-PARALLEL CONVERTER. power RXCLK provides arbitrary alignment incoming data until arrival first K28.5 byte while SYNCEN HIGH. OUTPUT REGISTER takes 10-bit-wide output from SERIAL-TO-PARALLEL CONVERTER block generates output data BRXD0.9. BRXD0.9 interfaces ENDEC chip strobed negative edge RXCLK. received sequence within each bits serial data BRXD9 BRXD0.
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GA9101/9102
Specifications
Figure Test Load, RXCLK
Figure PECL Test Load
Table Capacitance1
Symbol
Notes:
These parameters 100% tested, periodically sampled.
Table Absolute Maximum Ratings1
Symbol
Tstorage Tcase VCC1
1100
Figure Test Load, Other Outputs
1100
2200
Description
Test Conditions
Min.
Typ.
Max.
Units
Input capacitance
Output capacitance
VOUT
Description
Test Conditions
-0.5 -0.5
Min.
Typ.
Max.
Units
Storage Temperature Case Temperature Supply Voltage ground Input voltage Input current
Notes: Exceeding absolute maximum ratings damage these devices.
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DATACOM PRODUCTS
GA9101/9102
Table Operating Conditions1
Parameter
Description
Supply Voltage Ambient Temperature
Min.
(-5%)
Typ.
Max.
(+5%)
Units
ICC2
Power supply current
Notes: Proper functionality guaranteed under these conditions. With Max, static.
Table Characteristics-GA9101 Transmitter Signals (BTXDO.9, TXCLK, SIGDET, LOOPEN)
Limits Typ.
Symbol
ISC4 VIH5 VIL5 VNotes:
Description
Output HIGH voltage Output voltage
Output short-circuit current Input current Input HIGH current Input HIGH current Input HIGH level Input level
Input clamp voltage
Typical limits are: inputs could high low. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
Test Conditions Min.
Max.
Unit
-1.6
VIN2 -3.2 VIN2 VOUT
-100
Guaranteed input logical HIGH voltage inputs Guaranteed input logical voltage inputs
-1.2
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GA9101/9102
Table Characteristics-GA9101 Transmitter PECL Signals (TX, TLX, TLY, SIG, SIGN)
Limits Typ.
Symbol
VIHS VILS VDIF VICM VCMO DVOU
Description
Input current Input HIGH current Highest input HIGH voltage Lowest input voltage
Test Conditions
-0.5
Min.
Max.
-0.50
Unit
DATACOM PRODUCTS
Differential input voltage Input common mode voltage Output HIGH voltage Output voltage
Output common mode voltage Output Differential voltage
Notes: Typical limits are: 25°C. inputs could HIGH LOW. RXCLK signal IOL. other outputs have IOL. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
Table Characteristics-GA9102 Receiver Signals (BRXD0.9, RXCLK, SYNC, REFCLK, LOOPEN)
Limits Typ.
Symbol
ISC5 VIH4 VIL4
Notes:
Description
Output HIGH voltage Output voltage Output short-circuit current Input current Input HIGH current Input HIGH current Input HIGH level Input level
Input clamp voltage Power supply current
Typical limits are: 25°C. inputs could HIGH LOW. RXCLK signal IOL. other outputs have IOL. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
PECL load =VCC -1.025 PECL load =VCC -2.0 -1.6 0.75 -0.7 -0.5 -1.62 -1.2
Test Conditions
Min.
Max.
Unit
-1.6 VIN2 VIL= -3.2 VIN2 VIL=
VOUT
-120
0.40 Guaranteed input logical HIGH voltage inputs Guaranteed input logical voltage inputs
-400
-1.2
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GA9101/9102
Table Characteristics-GA9102 Receiver PECL Signals (RX, RLX, RLY)
Limits Typ.
Symbol
VIHS VILS VDIF VICM
Description
Input current Input HIGH current Highest Input HIGH voltage Lowest Input voltage Differential Input voltage Input Common Mode voltage
Test Conditions
=2.4
Min.
Max.
Unit
Notes: Typical limits are: 25°C. inputs could HIGH LOW. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
Table Specifications-GA9101 Transmitter
Parameter
Description
BTXD0.9 Setup Time BTXD0.9 Hold Time TXCLK Pulse Width HIGH TXCLK Pulse Width TXCLK Period
TLX, Rise Time TLX, Fall Time Skew
Output Jitter Deterministic Jitter (DJ) Random Jitter (RJ) Propagation Delay SIG, SIGN SIGDE
Notes: TXCLK period (10/baud rate) +0.01%, where baud rate 194.4, 200.0, 265.625 Mbaud. These numbers measured single-ended, using High Gain Method MHz. jitter numbers 10-12.
Min.
Typ.
Max.
Units
2.50 2.50 15.00
15.00 37.30
52.00
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GA9101/9102
Figure Timing-GA9101 Transmitter
BTXD0.9 TXCLK
Figure Serial Output Timing -GA9101
Figure Serial Output Timing -GA9101
SIG, SIGN
SIGDE
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DATACOM PRODUCTS
GA9101/9102
Table Specifications-GA9102 Receiver
Parameter
T231 T281 T312 T322
Description
REFCLK Pulse width REFCLK Pulse width HIGH REFCLK Period BRXD0.9 Valid RXCLK BRXD0.9 Time from RXCLK RXCLK Pulse width RXCLK Pulse width HIGH RXCLK Period SYNC Valid RXCLK SYNC Time from RXCLK
Min.
15.00 15.00 37.30 T28/5 2.00 (T28/2) -2.50
Typ.
Max.
Units
52.00
RLX, Rise time RLX, Fall time
Skew RLX, RLY, Peak-to-peak input jitter3
Notes: REFCLK RXCLK period (10/baud rate) +0.01%, where baud rate 194.4, 200.0, 265.625 Megabaud. Measured VDIFF jitter numbers 10-12.
Figure Timing-GA9102 Receiver
(T28/2) -2.50 37.30 T28/5 2.00 52.00 1.50 1.50 1.50 0.07*T28
REFCLK BRXD0.9 RXCLK SYNC
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GA9101/9102
Table Synchronization Times
Description
Power application REFCLK Application valid data Resynchronization after phase shift data
Min.
Typ.
Max.
2500
Units
times
Figure Serial Input Timing -GA9102
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DATACOM PRODUCTS
GA9101/9102
Pinouts
Figure GA9101 GA9102 Pinouts pinouts Transmitter Receiver arranged easy interface ENDEC optics.
BTXD1 BTXD0 SIGDET SIGN
ENDEC
BRXD2 BRXD3 BRXD4 BRXD5 BRXD6 BTXD2 BTXD3 BTXD4 BTXD5 BTXD6
BTXD7 BTXD8 BTXD9 TXCLK
BRXD1 BRXD0 RXCLK
BRXD7 BRXD8 BRXD9 SYNC
GA9101
REFCLK
GA9102
LOOPEN
LOOPEN
SYNCEN
OPTICS
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GA9101/9102
Table GA9101 Definitions
Symbol
TLX, SIGN, BTXD0.9 TXCLK LOOPEN SIGDET
3-1, 24-22
OUTPUT OUTPUT INPUT INPUT INPU
Qty.
Logic Level Active
PECL PECL PECL HIGH HIGH
Description
Differential Serial Data Output Diff. Serial Data Output, Loopback Optical Signal Present Transmit Data Input Transmit/PLL Reference Clock (19.44 26.5625 Mhz) Enable Loopback Signal Detected Volt Supply Ground
Table GA9102 Definitions
Symbol
RLX, BRXD0.9 RXCLK SYNC LOOPEN REFCLK SYNCEN
HIGH INPUT OUTPUT INPUT INPUT HIGH HIGH
Qty.
Logic Level Active
PECL PECL HIGH
Description
3-1, 24-22
INPUT INPUT OUTPU
Differential Serial Data Input Diff. Serial Data Input, Loopback Receive Output Data Receive Clock
OUTPU
HIGH
OUTPUT INPUT INPUT INPUT INPU
HIGH HIGH HIGH HIGH
Receive Byte Sync Enable Loopback Oscillator Clock (19.44 26.5625 MHz) Align K28.5 Volt Supply Ground
INPU
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DATACOM PRODUCTS
GA9101/9102
Packaging
Figure 28-Pin MQuad J-leaded Package
.490 ±.005 .045 .445 .172 .104 .040
0.125 VENT PLUG
.015
Ordering Information
GA9101-2MC GA9102-2MC
Additional Information
latest specifications, additional product information, worldwide sales distribution locations, information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
technical questions additional information specific applications: Email: applications@tqs.com
information provided herein believed reliable; TriQuint assumes liability inaccuracies omissions. TriQuint assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. TriQuint does authorize warrant TriQuint product life-support devices and/or systems. Copyright 1997 TriQuint Semiconductor, Inc. rights reserved. Revision 1.1.B April 1999
.490 ±.005 .445 .410 ±.015 .028 .018 .050 .050 .132
Transmitter
Receiver
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DATA CTRL GA9103 ENDEC HOST customersupplied ENDEC* DATA DECODE STATUS

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