Meets exceeds relevant ANSI, Bellcore specifications Fully balanced, d

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Meets exceeds relevant ANSI, Bellcore specifications Fully balanced, d

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Gb/s Demultiplexer with Clock Data Recovery
Meets exceeds relevant ANSI, Bellcore specifications Fully balanced, differential architecture Differential data input accepts signals Gb/s data rate Loss lock signal 4-bit Mb/s Voltage Differential Signal (LVDS) outputs Single supply simplified system integration Industry standard 48-pin LQFP package Section repeaters, muxes, terminators, broadband crossconnects Nortel Networks YA28 Demultiplexer clock recovery circuit bipolar monolithic demultiplexer that accepts nominal Gb/s data stream extracts clock retimes Gb/s datastream. This data then multiplexed 4-bit parallel data Mb/s, which output with data clock MHz. Nortel Networks offers portfolio optical networking highperformance optical transmitter receiver functions. YA28 provides power chip-count savings that translate into better utilization board real estate ultimately cost savings designer fiber-based Datacom Telecom solutions. YA28 fabricated using high yield silicon bipolar process. available 48-lead LQFP package.
System block diagram
Applications
SONET/SDH-based transmission systems, test equipment modules OC-48 fibre optic modules line termination OC-48 SONET applications Aover SONET/SDH
Functional description
YA28 uses phase lock loop techniques recover high frequency dock from binary data presented pins RXD_INP RXD_INN nominally Gb/s. recovered clock retimes data which then demultiplexed into four Mb/s data streams LVDS compatible outputs. SONET/SDH applications device tuned during manufacture provide center frequency close 2.488 GHz. This coarse tuning performed during production additional trimming required alignment. normal operation, only external components required decoupling capacitors loop filter components.
Phase locked loop
used YA28 fully balanced differential design, similar that used YA18 Clock Data Recovery function, comprising phase/frequency detector. been designed minimize jitter effects temperature supply voltage ripple. center frequency digitally programmed during manufacture minimize effect process variations.
System outputs
recovered clock from section divided down output CK622_OUTP CK622_OUTN. retimed data demultiplexed Mb/s output RXD_OUTnP RXD_OUTnN (n=0 data output transitions retimed falling edge recovered clock (i.e. falling edge CK622_OUTP).
System inputs
Inputs RXD_INP RXD_INN fully differential inputs designed receive coupled signals from post amplifier. Normally, this would Nortel Networks AC03/ AC10 Automatic Gain Control (AGC) Amplifier. These inputs include on-chip termination resistors nominally Functional block diagram
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YA28 Gb/s Demultiplexer with Clock Data Recovery
Loss lock
loss lock indicator open-collector output (active low) which functions monitoring cycle slips input relative VCO. output sinks maximum current will active least after most recent frequency correction pulse, which time loop assumed phase lock data assumed valid. loss lock signal extended with external circuitry required. frequency correction current pulse emitted successive samples clock data transitions show slip phase clock signal either forward reverse directions with respect data edges. input signal compliant with tolerance requirements Bellcore GR-253 will trigger output after allotted loop acquisition.
Test inputs outputs
number test inputs provided production testing speeds. These unterminated inputs bypass internal left unconnected under normal operation. divided version output delivered single-ended power PECL output CK155_OUT. CK155_EN used enable this functionality. Note: Under normal operation leave these pins unconnected.
Absolute maximum ratings
These stress ratings only Exposure stresses beyond these maximum ratings cause permanent damage affect reliability device Avoid operating device outside recommended operating conditions defined below.
-0.7
Symbol
VIcml IOlvds VIlvpecl VIlvcmos VOoc Tstg
Parameter
Supply voltage VCC/VCC_OUT/VCC_VCO data input voltage single-ended LVDS output current LVPECL single ended input voltage LVCMOS single ended input voltage Open Collector output voltage Storage Temperature
VCC+0.5
Units
-0.5 -0.5 -0.5
VCC+0.5 VCC+0.5 VCC+0.5
Recommended operating conditions
Symbol
Vripple VIDcml Vicml VIHpecl VILpecl VIHcmos VILcmos Tamb
Parameter
Supply voltage supply voltage noise ripple differential input voltage (peak-to-peak) input voltage, recommended overall range PECL input HIGH voltage PECL input voltage Input voltage high, LVCMOS input Input voltage low, LVCMOS input Junction temperature Ambient temperature
3.135
Typical
3.30
3.465
Units
pk-pk
2.15 -1.165 -1.81
-0.88 -1.475
voltages with respect unless otherwise stated.
specified levels include supply rail variations except ripple noise, which specified Vripple.
YA28 Gb/s Demultiplexer with Clock Data Recovery
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electrical characteristics
Symbol
IIHlvpecl IILlvpecl VOHpecl VOLpecl VMAX
Parameter
LVPECL high current, -0.88 LVPECL current, -1.81 LVPECL output HIGH voltage LVPECL output voltage Input current high, LVCMOS input Input current low, LVCMOS input Open Collector voltage Open Collector High leakage current Open Collector Pull-up Voltage Open Collector Current Current drawn from supply Device power dissipation
Typical
Units
-1.065 -1.81
-0.88 -1.62
Over recommended operating conditions unless otherwise noted.
characteristics
Parameter
loop aquisition time Jitter Tolerance RXD_INP/N inputs, bandwidth from from from from above Jitter generated TXD_OUTP/N outputs, bandwidth Jitter gain from RXD_INP/N CKOP/N asserted pulse width dB/dec dB/dec 0.15 0.0075
Typical
Units
pk-pk pk-pk pk-pk pk-pk pk-pk
Over recommended operating conditions unless otherwise noted, output load
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YA28 Gb/s Demultiplexer with Clock Data Recovery
LVDS output electrical characteristics
Symbol
[Vod]
Parameter
Output voltage high, Output voltage low, Output differential voltage Output offset voltage Output impedance, single ended mismatch between Change [Vod] between Change between Output current Output current
Conditions
load load load load load load Driver shorted ground Driver shorted ground
+125 1125
1475 Voh-125 1275
Unit
[Vod]
Isa, Isab
LVDS output characteristics
Symbol
fall risel Clock
Parameter
fall time, rise time, Clock signal duty cycle
Conditions
Unit
CK622_OUT waveform
diagram data outputs
YA28 Gb/s Demultiplexer with Clock Data Recovery
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Additional design applications information
application diagram "Typical application configuration" shows configuration using YA28 Gb/s OC48/STM-16 system. This shows required external components, including supply decoupling capacitors. Typical application configuration
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YA28 Gb/s Demultiplexer with Clock Data Recovery
Power supply noise
Although device been designed maximize supply noise rejection, recommended that filter network, shown "Supply filter circuit" below, between supply VCC_VCO. Using this configuration, device will function within jitter specification with maximum supply noise mVpp, over frequency range from MHz, supply. effective series resistance network must exceed Supply filter circuit
Setting loop filter
YA28 designed regenerator receiver applications. integrated fully differential design with loop bandwidth external network. configuration this network shown "Loop filter configuration" with typical component values listed typical loop filter component values table. These components surface mount parts 0603 size, with tolerance resistors tolerance capacitors ±10% tolerance capacitors from typical loop filter component values table defines typical values loop filter components given bandwidth. Alternative values determined using standard performance equations.
Loop filter configuration
YA28 Gb/s Demultiplexer with Clock Data Recovery
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Typical loop filter component values
Loop bandwidth (kHz)
1800
(nF)
assignment
Name
VCC_VCO VCO_IN VCO_IP AMP_INN AMP_INP RXD_INP RXD_INN PD_OUTN PD_OUTP FD_OUTN FD_OUTP VCC_CORE GND_CORE GND_OUT VCC_OUT RXD_OUT0N RXD_OUT0P RXD_OUT1N RXD_OUTlP CK622_OUTN CK622_OUTP RXD_OUT2N RXD_OUT2P RXD_OUT3N RXD_OUT3P CK155_EN CK155_OUT TEST_CKN TEST_CKP
Type
Description
Function
voltage controlled oscillator
Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Open Collector
Voltage controlled oscillator positive input Voltage controlled oscillator negative input Input loop filter Input loop filter Positive differential data input Negative differential data input Loop preamplifier negative output Loop preamplifier positive output Frequency detector positive output Frequency detector negative output Lock flag (Active low) connection
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS PECL PECL PECL
core sections chip core sections chip VGND data clock output buffers +3.3 supply rail clock data output buffers Retimed data differential negative output Retimed data differential positive output Retimed data differential negative output Retimed data differential positive output Recovered divided clock differential negative output Recovered divided clock differential positive output Retimed data differential negative output Retimed data differential positive output Retimed data differential negative output Retimed data differential positive output Enable test clock output (leave unconnected) divided clock test output (leave unconnected) External test clock input (leave unconnected) External test clock input (leave unconnected)
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YA28 Gb/s Demultiplexer with Clock Data Recovery
Name
TEST_EN GND_VCO
Type
Description
CMOS
Function
Test enable input test clock (leave unconnected) VGND
Package configuration
device packaged 48-lead plastic low-profile quad flat pack (LQFP). achieve required thermal resistance, package contains heat slug that must soldered directly circuit board. 48-lead LQFP
YA28 Gb/s Demultiplexer with Clock Data Recovery
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Package outline drawing dimensions
Package outline
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YA28 Gb/s Demultiplexer with Clock Data Recovery
Dimension
Lead Pitch Body Size (Dl) Component Tip-to-Tip Component Height Component Standoff (A1) Body Thickness (A2) Lead Width, plated Lead Thickness, plated
(mm)
(mm)
0.50 7.00 9.00
(mm)
1.60 0.05 1.35 0.17 0.09 1.40 0.22 0.15 1.45 0.27 0.20
Ordering information
Please quote Product Code from Table below when ordering this identification that appears part when shipped.
Product ordering information
Product Code
A0774011 (QMV1080-1AF5)
Product Name
YA28 Gb/s Demultiplexer with Clock Data Recovery
additional information Nortel Networks products services offered, please contact your local representative. Nortel Networks High Performance Optical Component Solutions attn: Marketing Department 2745 Iris Street Floor Ottawa, Ontario Canada Tel: 1-800-4 NORTEL Fax: 1-613-763-8416 Email: www.nortelnetworks.com/hpocs
Copyright 2001 Nortel Networks Corporation. rights reserved. Nortel, Nortel Networks, Nortel Networks corporate logo, globemark design trademarks Nortel Networks Corporation. thirdparty trademarks property their respective owners. information contained this document considered accurate date publication. liability assumed Nortel Networks information contained this document, infringement patent rights other proprietary rights third parties which result from such use. license granted implication otherwise under patent right other proprietary right Nortel Networks.
Publication 84067.02/03-01 Issue
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Meets exceeds relevant ANSI, Bellcore specifications Fully balanced, d

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