SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation nois

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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation nois

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QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
operation noise CMOS level outputs 500ps output skew, Q0-Q output, outputs, output, output Outputs 3-state reset while OE/RST disable feature frequency testing Internal loop filter network Functional equivalent Motorola MC88915 Positive negative edge synchronization (PE) Balanced drive outputs ±36mA 160MHz maximum frequency (2xQ output) Available QSOP PLCC packages
QS5919
DESCRIPTION
QS5919 Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock inputs. Eight outputs available: 2xQ, 0-Q4, Q/2. Careful layout design ensure 500ps skew between Q0-Q4, outputs. QS5919 includes internal filter which provides excellent jitter characteristics eliminates need external components. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. LOCK output asserts indicate when phase lock been achieved. QS5919 designed highperformance workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. more information clock driver products, Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL SYNC SYNC E/RST
ETEC
DBACK
PLL_E
FREQ _SEL
2000 Integrated Device Technology, Inc.
JULY 2000
DSC-5823/-
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CONFIGURATION
J28-1 LOCK
OE/RST FEEDBACK REF_SEL SYNC AGND SYNC FREQ_SEL
SO28-9
LOCK PLL_EN
FEED REF_SEL
OE/RST
FREQ _SEL
QSOP VIEW
PLCC VIEW
Unit
ABSOLUTE MAXIMUM RATINGS
Symbol Rating AVDD/VDD Supply Voltage Ground Input Voltage Maximum Power QSOP Dissipation 85°C) PLCC Storage Temperature Range Max. -0.5 -0.5
TSTG
+150
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE 1MHz,
QSOP Parameter Typ. Max. Typ. PLCC Max. Unit
PLL_EN
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
DESCRIPTION
Name SYNC0 SYNC1 REF_SEL FREQ_SEL FEEDBACK LOCK OE/RST PLL_EN AVDD AGND Reference clock input Reference clock input Reference clock select. When selects SYNC When selects SYNC0. frequency select. choosing optimal operating frequency depending input frequency. feedback input which connected user selected output pin. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched frequency, inverted with respect Clock output. Matched phase, frequency double frequency. Clock output. Matched phase, frequency half frequency. lock indication signal. indicates positive lock. indicates that locked outputs synchronized inputs. Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled. enable. Enables disables PLL. Useful testing purposes. When LOW, outputs synchronized with positive edge SYNC. When HIGH, outputs synchronized with negative edge SYNC. Power supply output buffers. Power supply phase lock loop other internal circuitries. Ground supply output buffers. Ground supply phase lock loop other internal circuitries. Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: -40°C +85°C, AVDD/VDD 5.0V
Symbol FMAX_2XQ FMAX_Q FMAX_Q/2 FMIN_2XQ FMIN_Q FMIN_Q/2 Description Frequency, Frequency, Frequency, Frequency, Frequency, Frequency, 27.5 13.75 17.5 66.5 33.25 Units
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
FREQ_SEL HIGH HIGH HIGH HIGH Output Used Feedback SYNC (MHz) (allowable range) Min. FMIN_Q/2 FMIN_Q FMIN_Q FMIN_2XQ FMIN_Q/2 FMIN_Q FMIN_Q FMIN_2XQ FMAX _Q/2 FMAX FMAX FMAX _2XQ FMAX _Q/2 FMAX FMAX FMAX _2XQ SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC Output Frequency Relationships SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC
NOTES: Operation specified SYNC frequency range guarantees that will operate optimal range 20MHz FMAX_2XQ. Operation with Sync inputs outside specified frequency ranges result out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies. lock output (LOCK) indicate reliably frequencies below 30MHz.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, AVDD/VDD 5.0V
Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Input Hysteresis Output Leakage Current Input Leakage Current Input Pull-Down Current (PE) Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level -36mA -100µA Min., 36mA Min., 100µA VOUT GND, Max. AVDD GND, AVDD Max. AVDD Max., AVDD Min. 0.75 Typ. Max. 0.45 Unit
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDDD Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current
Test Conditions Max., OE/RST LOW, SYNC LOW, outputs unloaded Max., 3.4V Max.,
Typ.
Max.
Unit mA/MHz
NOTE: Relative frequency outputs.
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INPUT TIMING REQUIREMENTS
Symbol tPWC Description Maximum input rise fall times, 0.8V Input Clock Frequency, SYNC0, SYNC1 Input clock pulse, HIGH Duty cycle, SYNC0, SYNC1 Min. Max. FMAX _2XQ Unit
NOTES: Output Frequency Frequency Selection tables more detail allowable SYNC input frequencies different speed grades with different FEEDBACK FREQ_SEL combinations. Where pulse witdh implied less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tSKALL tLOCK tPZH tPZL tPHZ tPLZ Parameter Output Skew Between Rising Edges, Q0-Q4 Output Skew Between Falling Edges, Q0-Q4 Output Skew, Outputs
(2,5)
Min. TCY/2 TCY/2 0.15
Max. TCY/2 TCY/2 0.15
Unit
Pulse Width, output, >40MHz Pulse Width, Q0-Q4, outputs, 80MHz Cycle-to-Cycle Jitter SYNC Input Feedback Delay SYNC Phase Lock Output Enable Time, OE/RST HIGH Output Disable Time, OE/RST HIGH Output Rise/Fall Times, 0.2VDD 0.8VDD
NOTES: Test Loads Waveforms test load termination. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). Measured open loop mode PLL_EN Jitter characterized with output 20MHz. Frequency Selection Table information proper FREQ_SEL level specified input frequencies. Skew measured selected synchronization edge. measured device inputs 1.5V, output 80MHz.
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST LOADS WAVEFORMS
7.0V UTPUT
UTPUT
30pF
TEST CIRCUIT
TEST CIRCUIT
1.0ns
1.0ns
0.8V 0.5V 0.2V
3.0V 2.0V 1.5V 0.8V
INPUT TEST WAVEFORM
DISABLE
CMOS OUTPUT WAVEFORM
1.5V NTRO UTPUT ALLY ITCH 1.5V 0.3V ITCH UTPUT ALLY HIGH 0.3V 1.5V 3.5V
ENABLE DISABLE TIMES
TEST CIRCUIT used output enable/disable parameters. TEST CIRCUIT used other timing parameters.
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TIMING DIAGRAM
SYNC
FEEDBACK
NOTES: Timing Diagram applies output connected FEEDBACK GND. VDD, negative edge FEEDBACK aligns with negative edge SYNC input, negative edges multiplied divided outputs align with negative edge SYNC. parameters except measured 0.5VDD; measured 1.5V.
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
OPERATION
Phase Locked Loop (PLL) circuit included QS5919 provides replication incoming SYNC clock signals. manipulation that signal, such frequency multiplying inversion performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feedback path, `propagation delay' even negative! simplified schematic QS5919 circuit shown below.
SIMPLIFIED DIAGRAM QS5919 FEEDBACK
INPU PHASE DETECTOR
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5919 typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. respective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
QS5919 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
XXXX Device Type Package
Quarter Size Outline Package (SO28-9) Plastic Leaded Chip Carrier (J28-1)
5919
Skew CMOS Clock Driver with Integrated Loop Filter
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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation nois

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