GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew clock signa

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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew clock signa

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QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
output, skew clock signal buffer output voltage swing on-chip resistors available noise Input hysteresis better noise margin Guaranteed skew: 0.35ns output skew (same bank) 0.45ns output skew (opposite bank) 0.75ns part-to-part skew Std. speed grades Available QSOP SOIC packages
QS52807T/AT
DESCRIPTION
QS52807T clock driver/buffer circuits used clock buffering schemes where skew parameter. QS52807T generates non-inverting outputs. Designed IDT's proprietary QCMOS process, these devices provide propagation delay buffering with on-chip skew 0.35ns same-transition, same bank signals. QS52807T on-chip series termination resistors lower noise clock signals. QS52807T series resistor version recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed high-performance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QS52807T characterized operation -40°C +85°C.
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-5239/-
QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
QSOP Pins Typ.
+25OC, 1.0MHz,
SOIC Typ. Max. Unit Max.
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names Description Clock Input Clock Outputs
QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 5.0V
Symbol IOFF ROUT Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Input Leakage Current Input/Output Power Leakage Short Circuit Current Input Hysteresis Output Resistance
(2,3)
Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., VIL, -8mA Min., VIL, Max., Max., VOUT Max., VOUT VTLH VTHL Inputs Min., 12mA
Min.
Typ.(1) -0.7
Max. -1.2
Unit
-250
NOTES: Typical values 5.0V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested. Output resistance represents total output inpedance logic device includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples Test Conditions Max., Max., 3.4V Input toggling duty cycle Max., Outputs Enabled Max., Input duty cycle 10MHz Max., Input duty cycle 2.5MHz
NOTES: Guaranteed design tested. 0pF. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs (one) Output Frequency Number outputs (ten)
Typ. 0.09 3.4V 3.4V
Max. 21.5
Unit mA/MHz
QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
QS52807T Symbol tSK(01) tSK(P) tSK(T) tPLH tPHL Parameter Skew between outputs, same transition Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Propagation Delay Output Rise Time Output Fall Time
QS52807/AT Min. Max. 0.75 Unit
Min.
Max. 0.75
NOTES: Skew parameters guaranteed across temperature range, tested. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading, package, speed grade. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delay limits imply skew.
QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Pulse Generator
50pF
Pulse enerator puls 1.0M 2.5ns; 2.5ns
PROPAGATION DELAY
PULSE SKEW tSK(P)
INPU
1.5V
INPU
1.5V
tPLH
tPHL tPLH
1.5V
OUTPUT
2.0V
1.5V
OUTPUT
0.8V
SK(p)
OUTPUT SKEW tSK(O1)
PART-TO-PART SKEW tSK(T)
INPUT
1.5V
INPU
1.5V
PART UTPUT
1.5V
OUPUT
1.5V
tSK(t) SK(t)
1.5V
PART UTPUT
1.5V
OUPUT
tSK(01) PLH2 PHL1
tSK(p) PLH2 tPLH1 PHL2 PHL1
QS52807T/AT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Outline (300 (SO20-2) Quarter-size tline Package (SO20-8)
52807T Guaranteed Skew Clock river/Buffer 52807AT
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com*
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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew clock signa

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