GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER outputs Rail-to-rail out
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QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
outputs Rail-to-rail output voltage swing on-chip resistors available noise Input hysteresis better noise margin Guaranteed skew: 0.3ns output skew (same bank) 0.6ns output skew (different bank) part-to-part skew Std. speed grades Available QSOP SOIC packages
QS52807/A
DESCRIPTION
QS52807 clock driver/buffer circuits used clock buffering schemes where skew parameter. QS52807 offers non-inverting outputs. Designed IDT's proprietary QCMOS process, these devices provide propagation delay buffering with onchip skew 0.3ns same-transition signals. QS52807 on-chip series termination resistors lower noise clock signals. QS52807 series resistor version recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed highperformance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. Railto-rail output swing improves noise margin allows easy interface with CMOS inputs. QS52807 characterized operation -40°C +85°C.
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5233/-
QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
QSOP Pins Typ.
+25OC, 1.0MHz,
SOIC Typ. Max. Unit Max.
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names Description Clock Input Clock Outputs
QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 5.0V 10%, 0.2V, 0.2V
Symbol IOFF ROUT Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Input Leakage Current Input Power Leakage Short Circuit Current Input Hysteresis Output Resistance
(2,3)
Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., VIL, -12mA Min., VIL, -24mA Min., VIL, 12mA Max., Max., VOUT VTLH VTHL Inputs Min., 12mA
Min.
Typ.(1) -0.7
Max. -1.2
Unit
NOTES: Typical values 5.0V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested. Output resistance represents total output impedance logic device includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples Test Conditions Max., Max., 3.4V Input toggling duty cycle Max., outputs Enabled Max., Input duty cycle 10MHz Max., Input duty cycle 2.5MHz
NOTES: Guaranteed design tested. 0pF. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs Output Frequency Number outputs
Typ. 0.005 0.12
Max.
Unit mA/MHz
QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF resistor)
QS52807 Symbol tSK(01) tSK(P) tSK(T) tPLH tPHL Parameter Skew between outputs, same transition Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Propagation Delay Output Rise Time, 0.8V Output Fall Time, 0.2Vcc 0.8Vcc Min. Max. Min. QS52807A Max. 0.35 Unit
NOTES: Skew parameters guaranteed across temperature range, tested. Skew parameters measured 0.5Vcc. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading, package, speed grade. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew.
QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Pulse Generator
50pF
Pulse generator puls 1.0M 2.5ns; 2.5ns
PROPAGATION DELAY
PULSE SKEW tSK(P)
INPUT
1.5V
INPU
1.5V
0.5V
OUTPUT
2.0V
0.5V
OUTPUT
0.8V
tSK(p) PLHL
OUTPUT SKEW tSK(O1)
PART-TO-PART SKEW tSK(T)
INPUT
1.5V
INPU
1.5V
PART UTPUT
0.5V
OUTPUT
0.5V
SK(O tSK(t) tSK(t)
0.5V
0.5V
PART UTPUT
OUTPUT
SK(01) PLH2 PLH1 PHL1
SK(p) PLH2 PLH1 PHL2 PHL1
QS52807/A GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Outline (300 (SO20-2) Quarter-size Outline Package (SO20-8)
52807 52807A
Guaranteed Skew Clock Driver/Buffer
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