Quad 2-Input NAND Gate MC74VHCT00A advanced high speed CMOS 2-inp

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Quad 2-Input NAND Gate MC74VHCT00A advanced high speed CMOS 2-inp

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Quad 2-Input NAND Gate
MC74VHCT00A advanced high speed CMOS 2-input NAND gate fabricated with silicon gate CMOS technology. achieves high speed operation similar equivalent Bipolar Schottky while maintaining CMOS power dissipation. VHCT inputs compatible with levels. This device used level converter interfacing 3.3V 5.0V, because full CMOS level output swings. VHCT00A input structures provide protection when voltages between 5.5V applied, regardless supply voltage. output structures also provide protection when These input output structures help prevent device destruction caused supply voltage input/output voltage mismatch, battery backup, insertion, etc. High Speed: 5.0ns (Typ) Power Dissipation: (Max) 25°C TTL-Compatible Inputs: 0.8V; 2.0V Power Down Protection Provided Inputs Outputs Balanced Propagation Delays Designed 4.5V 5.5V Operating Range Noise: VOLP 0.8V (Max) Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA Performance: 2000V; Machine Model 200V Chip Complexity: FETs Equivalent Gates
MC74VHCT00A
SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03
SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01
SUFFIX 14-LEAD SOIC EIAJ PACKAGE CASE 965-01
ORDERING INFORMATION
LOGIC DIAGRAM
MC74VHCTXXAD MC74VHCTXXADT MC74VHCTXXAM
SOIC TSSOP SOIC EIAJ
FUNCTION TABLE
Inputs Output
Pinout: 14-Lead Packages (Top View)
6/97
Motorola, Inc. 1997
Absolute maximum continuous ratings those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute-maximum-rated conditions implied. Derating SOIC Packages: mW/_C from 125_C TSSOP Package: mW/_C from 125_C
MC74VHCT00A
MAXIMUM RATINGS*
Symbol Vout Tstg Iout Storage Temperature Power Dissipation Still Air, Supply Current, Pins Output Current, Output Diode Current (VOUT GND; VOUT VCC) Input Diode Current Output Voltage Input Voltage Supply Voltage Parameter SOIC Packages TSSOP Package High State Value Unit
ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
MOTOROLA Symbol Symbol IOPD Vout ICCT
Input Rise Fall Time
Operating Temperature
Output Voltage
Input Voltage
Supply Voltage
Output Leakage Current
Quiescent Supply Current
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
VOUT 5.5V
Input: 3.4V Other Input:
Test Conditions
=5.0V ±0.5V
High State
50µA
50µA
3.94
ns/V
Unit
25°C
1.35
0.36
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either Unused outputs must left open.
Data Advanced CMOS Logic DL203 85°C 3.80
1.50 20.0 0.44
Unit
MC74VHCT00A
ELECTRICAL CHARACTERISTICS (Input 3.0ns)
Symbol tPLH, tPHL Parameter 25°C 85°C Test Conditions Unit Propagation Delay, Input Capacitance 0.5V 15pF 50pF Typical 25°C, 5.0V Power Dissipation Capacitance (Note TAG) defined value internal equivalent capacitance which calculated from operating current consumption without load. Average operating current obtained equation: ICC(OPR) (per gate). used determine no-load dynamic power consumption; VCC2 VCC.
NOISE CHARACTERISTICS (Input 3.0ns, 50pF, 5.0V, Measured SOIC Package)
25°C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic Quiet Output Minimum Dynamic Minimum High Level Dynamic Input Voltage Maximum Level Dynamic Input Voltage Unit
TEST POINT 1.5V tPLH 1.5V Includes probe capacitance tPHL DEVICE UNDER TEST OUTPUT
Figure Switching Waveforms
Figure Test Circuit
Data Advanced CMOS Logic DL203
MC74VHCT00A
OUTLINE DIMENSIONS
SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
Data Advanced CMOS Logic DL203
MC74VHCT00A
OUTLINE DIMENSIONS
SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS MEASURED PARTING LINE. MOLD FLASH PROTRUSIONS SHALL EXCEED 0.15 (0.006) SIDE. TERMINAL NUMBERS SHOWN REFERENCE ONLY. LEAD WIDTH DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS LEAD WIDTH DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS ADJACENT LEAD 0.46 0.018). 0.50 MILLIMETERS 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 7.40 8.20 0.50 0.85 1.10 1.50 0.70 0.90 1.42 INCHES 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 0.291 0.323 0.020 0.033 0.043 0.059 0.028 0.035 0.056
DETAIL
VIEW
0.13 (0.005)
0.10 (0.004)
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Mfax trademark Motorola, Inc. reach EUROPE Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 303-675-2140 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
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Data Advanced CMOS Logic DL203
MC74VHCT00A/D

Quad 2-Input NAND Gate MC74VHCT00A advanced high speed CMOS 2-inp

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