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H8/3003 Hardware Manual
revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
ADE-602-055A
Preface
H8/3003 high-performance microcontroller that integrates system supporting functions together with H8/300H core. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. on-chip system supporting functions include RAM, 16-bit integrated timer unit (ITU), programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, ports, direct memory access controller (DMAC), refresh controller, other facilities. four operating modes offer choice data width address space size, enabling H8/3003 adapt quickly flexibly variety conditions. This manual describes H8/3003 hardware. details instruction set, refer H8/300H Programming Manual.
Contents
Section
Overview. Overview Block Diagram. Description 1.3.1 Arrangement. 1.3.2 Functions Functions
Section
Overview 2.1.1 Features. 2.1.2 Differences from H8/300 Operating Modes. Address Space. Register Configuration. 2.4.1 Overview. 2.4.2 General Registers. 2.4.3 Control Registers 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats. 2.5.2 Memory Data Formats Instruction Set. 2.6.1 Instruction Overview 2.6.2 Instructions Addressing Modes. 2.6.3 Tables Instructions Classified Function. 2.6.4 Basic Instruction Formats 2.6.5 Notes Manipulation Instructions Addressing Modes Effective Address Calculation 2.7.1 Addressing Modes 2.7.2 Effective Address Calculation Processing States 2.8.1 Overview. 2.8.2 Program Execution State 2.8.3 Exception-Handling State. 2.8.4 Exception-Handling Sequences 2.8.5 Bus-Released State 2.8.6 Reset State 2.8.7 Power-Down State
Basic Operational Timing. 2.9.1 Overview. 2.9.2 On-Chip Memory Access Timing. 2.9.3 On-Chip Supporting Module Access Timing 2.9.4 Access External Address Space.
Section
Operating Modes Overview 3.1.1 Operating Mode Selection 3.1.2 Register Configuration. Mode Control Register (MDCR) System Control Register (SYSCR). Operating Mode Descriptions. 3.4.1 Mode 3.4.2 Mode 3.4.3 Mode 3.4.4 Mode Functions Each Operating Mode. Memory Each Operating Mode.
Overview 4.1.1 Exception Handling Types Priority. 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table. Reset 4.2.1 Overview. 4.2.2 Reset Sequence 4.2.3 Interrupts after Reset. Interrupts Trap Instruction. Stack Status after Exception Handling Notes Stack Usage
Section
Exception Handling
Section
Interrupt Controller. Overview 5.1.1 Features. 5.1.2 Block Diagram. 5.1.3 Configuration. 5.1.4 Register Configuration.
Register Descriptions. 5.2.1 System Control Register (SYSCR). 5.2.2 Interrupt Priority Registers (IPRA, IPRB) 5.2.3 Status Register (ISR) 5.2.4 Enable Register (IER) 5.2.5 Sense Control Register (ISCR) Interrupt Sources. 5.3.1 External Interrupts 5.3.2 Internal Interrupts 5.3.3 Interrupt Vector Table Interrupt Operation 5.4.1 Interrupt Handling Process 5.4.2 Interrupt Sequence 5.4.3 Interrupt Response Time. Usage Notes 5.5.1 Contention between Interrupt Interrupt-Disabling Instruction 5.5.2 Instructions that Inhibit Interrupts 5.5.3 Interrupts during EEPMOV Instruction Execution.
Section
Controller Overview 6.1.1 Features. 6.1.2 Block Diagram. 6.1.3 Input/Output Pins. 6.1.4 Register Configuration. Register Descriptions. 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR) 6.2.3 Wait Control Register (WCR). 6.2.4 Wait State Control Enable Register (WCER) 6.2.5 Release Control Register (BRCR). Operation 6.3.1 Area Division. 6.3.2 Chip Select Signals 6.3.3 Data Bus. 6.3.4 Control Signal Timing 6.3.5 Wait Modes 6.3.6 Interconnections with Memory (Example). 6.3.7 Arbiter Operation. Usage Notes 6.4.1 Connection Dynamic Pseudo-Static
6.4.2 6.4.3
Register Write Timing BREQ Input Timing.
Section
Refresh Controller Overview 7.1.1 Features. 7.1.2 Block Diagram. 7.1.3 Input/Output Pins. 7.1.4 Register Configuration. Register Descriptions. 7.2.1 Refresh Control Register (RFSHCR) 7.2.2 Refresh Timer Control/Status Register (RTMCSR) 7.2.3 Refresh Timer Counter (RTCNT). 7.2.4 Refresh Time Constant Register (RTCOR) Operation 7.3.1 Area Division. 7.3.2 DRAM Refresh Control. 7.3.3 Pseudo-Static Refresh Control. 7.3.4 Interval Timing Interrupt Source Usage Notes Controller Overview 8.1.1 Features. 8.1.2 Block Diagram. 8.1.3 Functional Overview. 8.1.4 Input/Output Pins. 8.1.5 Register Configuration. Register Descriptions (Short Address Mode) 8.2.1 Memory Address Registers (MAR). 8.2.2 Address Registers (IOAR). 8.2.3 Execute Transfer Count Registers (ETCR). 8.2.4 Data Transfer Control Registers (DTCR) Register Descriptions (Full Address Mode). 8.3.1 Memory Address Registers (MAR). 8.3.2 Address Registers (IOAR). 8.3.3 Execute Transfer Count Registers (ETCR). 8.3.4 Data Transfer Control Registers (DTCR) Operation 8.4.1 Overview.
Section
8.4.2 Mode. 8.4.3 Idle Mode. 8.4.4 Repeat Mode. 8.4.5 Normal Mode. 8.4.6 Block Transfer Mode 8.4.7 DMAC Activation. 8.4.8 DMAC Cycle 8.4.9 Multiple-Channel Operation. 8.4.10 External Requests, Refresh Controller, DMAC. 8.4.11 Interrupts DMAC 8.4.12 Aborting Transfer 8.4.13 Exiting Full Address Mode. 8.4.14 DMAC States Reset State, Standby Modes, Sleep Mode Interrupts Usage Notes 8.6.1 Note Word Data Transfer. 8.6.2 DMAC Self-Access 8.6.3 Longword Access Memory Address Registers. 8.6.4 Note Full Address Mode Setup. 8.6.5 Note Activating DMAC Internal Interrupts 8.6.6 Interrupts Block Transfer Mode 8.6.7 Memory Address Register Values 8.6.8 Cycle when Transfer Aborted
Section
Ports
Overview Port 9.2.1 Overview. 9.2.2 Register Descriptions. 9.2.3 Functions Each Mode. 9.2.4 Input Pull-Up Transistors. Port 9.3.1 Overview. 9.3.2 Register Descriptions. 9.3.3 Functions Each Mode. 9.3.4 Input Pull-Up Transistors. Port 9.4.1 Overview. 9.4.2 Register Descriptions. 9.4.3 Functions
9.10
Port 9.5.1 9.5.2 Port 9.6.1 9.6.2 9.6.3 Port 9.7.1 9.7.2 9.7.3 Port 9.8.1 9.8.2 9.8.3 Port 9.9.1 9.9.2 9.9.3 Port 9.10.1 9.10.2 9.10.3
Overview. Register Description Overview. Register Descriptions. Functions Overview. Register Descriptions. Functions Overview. Register Descriptions. Functions Overview. Register Descriptions. Functions Overview. Register Descriptions. Functions
Section
10.1
16-Bit Integrated Timer Unit (ITU).
10.2
Overview 10.1.1 Features. 10.1.2 Block Diagrams 10.1.3 Input/Output Pins. 10.1.4 Register Configuration. Register Descriptions. 10.2.1 Timer Start Register (TSTR) 10.2.2 Timer Synchro Register (TSNC) 10.2.3 Timer Mode Register (TMDR). 10.2.4 Timer Function Control Register (TFCR) 10.2.5 Timer Output Master Enable Register (TOER) 10.2.6 Timer Output Control Register (TOCR). 10.2.7 Timer Counters (TCNT) 10.2.8 General Registers (GRA, GRB) 10.2.9 Buffer Registers (BRA, BRB) 10.2.10 Timer Control Registers (TCR)
10.3
10.4
10.5
10.6
10.2.11 Timer Control Register (TIOR). 10.2.12 Timer Status Register (TSR). 10.2.13 Timer Interrupt Enable Register (TIER). Interface 10.3.1 16-Bit Accessible Registers 10.3.2 8-Bit Accessible Registers Operation 10.4.1 Overview. 10.4.2 Basic Functions. 10.4.3 Synchronization 10.4.4 Mode 10.4.5 Reset-Synchronized Mode 10.4.6 Complementary Mode. 10.4.7 Phase Counting Mode. 10.4.8 Buffering. 10.4.9 Output Timing. Interrupts 10.5.1 Setting Status Flags 10.5.2 Clearing Status Flags. 10.5.3 Interrupt Sources Controller Activation Usage Notes
Section
11.1
11.2
11.3
Programmable Timing Pattern Controller Overview 11.1.1 Features. 11.1.2 Block Diagram. 11.1.3 Pins 11.1.4 Registers Register Descriptions. 11.2.1 Port Data Direction Register (PADDR) 11.2.2 Port Data Register (PADR) 11.2.3 Port Data Direction Register (PBDDR) 11.2.4 Port Data Register (PBDR) 11.2.5 Next Data Register (NDRA). 11.2.6 Next Data Register (NDRB) 11.2.7 Next Data Enable Register (NDERA) 11.2.8 Next Data Enable Register (NDERB). 11.2.9 Output Control Register (TPCR). 11.2.10 Output Mode Register (TPMR). Operation 11.3.1 Overview.
11.4
11.3.2 Output Timing. 11.3.3 Normal Output. 11.3.4 Non-Overlapping Output. 11.3.5 Output Triggering Input Capture. Usage Notes 11.4.1 Operation Output Pins. 11.4.2 Note Non-Overlapping Output
Section
12.1
Watchdog Timer
12.2
12.3
12.4 12.5
Overview 12.1.1 Features. 12.1.2 Block Diagram. 12.1.3 Configuration. 12.1.4 Register Configuration. Register Descriptions. 12.2.1 Timer Counter (TCNT). 12.2.2 Timer Control/Status Register (TCSR). 12.2.3 Reset Control/Status Register (RSTCSR) 12.2.4 Notes Register Access Operation 12.3.1 Watchdog Timer Operation. 12.3.2 Interval Timer Operation 12.3.3 Timing Setting Overflow Flag (OVF) 12.3.4 Timing Setting Watchdog Timer Reset (WRST) Interrupts Usage Notes
Section
13.1
13.2
Serial Communication Interface Overview 13.1.1 Features. 13.1.2 Block Diagram. 13.1.3 Input/Output Pins. 13.1.4 Register Configuration. Register Descriptions. 13.2.1 Receive Shift Register (RSR) 13.2.2 Receive Data Register (RDR). 13.2.3 Transmit Shift Register (TSR) 13.2.4 Transmit Data Register (TDR). 13.2.5 Serial Mode Register (SMR) 13.2.6 Serial Control Register (SCR) 13.2.7 Serial Status Register (SSR)
13.3
13.4 13.5
13.2.8 Rate Register (BRR) Operation 13.3.1 Overview. 13.3.2 Operation Asynchronous Mode. 13.3.3 Multiprocessor Communication 13.3.4 Synchronous Operation Interrupts. Usage Notes
Section
14.1
14.2
14.3 14.4
14.5 14.6
Converter Overview 14.1.1 Features. 14.1.2 Block Diagram. 14.1.3 Input Pins 14.1.4 Register Configuration. Register Descriptions. 14.2.1 Data Registers (ADDRA ADDRD) 14.2.2 Control/Status Register (ADCSR) 14.2.3 Control Register (ADCR) Interface Operation 14.4.1 Single Mode (SCAN 14.4.2 Scan Mode (SCAN 14.4.3 Input Sampling Conversion Time 14.4.4 External Trigger Input Timing. Interrupts Usage Notes
Section
15.1
15.2 15.3
Overview 15.1.1 Block Diagram. 15.1.2 Register Configuration. System Control Register (SYSCR). Operation
Section
16.1 16.2
Clock Pulse Generator Overview 16.1.1 Block Diagram. Oscillator Circuit 16.2.1 Connecting Crystal Resonator 16.2.2 External Clock Input.
16.3 16.4 16.5
System Clock Divider (Clock-Halving Version) Duty Adjustment Circuit (1:1 Version). Prescalers
Section
17.1 17.2 17.3
Power-Down State
17.4
17.5
Overview Register Configuration. 17.2.1 System Control Register (SYSCR). Sleep Mode 17.3.1 Transition Sleep Mode. 17.3.2 Exit from Sleep Mode. Software Standby Mode 17.4.1 Transition Software Standby Mode 17.4.2 Exit from Software Standby Mode 17.4.3 Selection Waiting Time Exit from Software Standby Mode 17.4.4 Sample Application Software Standby Mode 17.4.5 Note. Hardware Standby Mode 17.5.1 Transition Hardware Standby Mode. 17.5.2 Exit from Hardware Standby Mode. 17.5.3 Timing Hardware Standby Mode.
Section
18.1 18.2
18.3
Electrical Characteristics Absolute Maximum Ratings Electrical Characteristics 18.2.1 Characteristics 18.2.2 Characteristics 18.2.3 Conversion Characteristics Operational Timing. 18.3.1 Timing 18.3.2 Refresh Controller Timing. 18.3.3 Control Signal Timing 18.3.4 Clock Timing 18.3.5 Port Timing. 18.3.6 Timing 18.3.7 Input/Output Timing. 18.3.8 DMAC Timing.
Appendix Instruction
Instruction List. Operation Code Map. Number States Required Execution.
Appendix Register Field
Register Addresses Names. Register Descriptions.
Appendix Port Block Diagrams
Port Block Diagram Port Block Diagram Port Block Diagrams. Port Block Diagram Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams.
Appendix States
Port States Each Mode. States Reset.
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode. Package Dimensions
Major Revisions Additions This Version
Page Item Figure Interrupt Sequence (Mode Two-State Access, Stack External Memory) Interrupt Response Time Programmable Wait Mode ASTCR Write Timing Contention between RTCNT Write Clear Contention between RTCNT Write Increment Contention between RTCOR Write Compare Match DMAC functional overview Operation Normal Mode Timing DMAC Activation DREQ Level Normal Mode Port Functions Description Operation timing amended
P125 P132 P166
Table Figure 6-15 Figure 6-20 Figure 7-20
Table values changed Operation timing amended Operation timing amended Operation timing amended
P167
Figure 7-21
Operation timing amended
P168
Figure 7-22
Address amended
P175 P207 P220
Table Figure Figure 8-17
Table contents amended Signal descriptions amended Operation timing amended
P270 Table 9-16 P272 P279 P343 Table 9-18
Table contents amended
Port Functions
Table contents amended Description added
Figure 10-34 Clearing Procedure Complementary Mode Table 12-1 Sample Flowchart Receiving Serial Data Usage Notes Damping Resistance Value Crystal Resonator Parameters Clock Timing External Clock Input Timing
P408
Note deleted Flowchart amended
P458 Figure 13-7 P459 P480 P506 P507 P509 P509 13.5 Table 16-1 Table 16-2 Table 16-3 Figure 16-6
Formula amended Values added table Values added table Table values changed Figure amended
Page P514
Item 17.3.2 Exit from Sleep Mode Exit Interrupt Electrical Characteristics
Description Description amended
P529 Table 18-4 P536 18-8 P520 Table 18-2 P526 P529 Table 18-4 P531 P532 P536 P541 Table 18-5 Table 18-8 Figure 18-7
Condition values amended
Characteristics
Values changed added table
Timing
Values changed
Refresh Controller Timing Conversion Characteristics DRAM Timing (Read/Write): Three-State Access Mode
Values changed Values changed *added
P543
Figure 18-10 DRAM Timing (Read/Write): Three-State Access 2CAS Mode Figure 18-13 PSRAM Timing (Read/Write): Three-State Access Table Instruction MOV. @(d:16, ERd) Instruction MOV. @(d:24, ERd) Instruction MOV. @(d:16, ERd) Instruction MOV. @(d:24, ERd)
*added
P545
*added
P555
Operation amended
Table
Operation amended
P556
Table
Operation amended
Table
Operation number execution states amended
Table Table P557 P566 P575 Table Table Table
Instruction MOV. #xx:32, Number execution states amended Instruction POP, Instruction PUSH. Instruction Number Cycles Instruction BSRd:16 Port Block Diagram (Pin P7n) Number execution states amended Number execution states amended Menmonics amended places) Internal operation added
P673
Figure
Figure amended
Section Overview
Overview
H8/3003 microcontroller (MCU) that integrates system supporting functions together with H8/300H core having original Hitachi architecture. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. instruction upward-compatible object-code level with H8/300 CPU, enabling easy porting software from H8/300 Series. on-chip system supporting functions include RAM, 16-bit integrated timer unit (ITU), programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, ports, direct memory access controller (DMAC), refresh controller, other facilities. Four operating modes offer choice data width address space size. Table summarizes H8/3003 features. Table Features
Feature Description Upward-compatible with H8/300 object-code level General-register machine Sixteen 16-bit general registers (also useable sixteen 8-bit registers eight 32-bit registers) High-speed operation Maximum clock rate: Add/subtract: Multiply/divide: operating modes Normal mode (64-kbyte address space, available H8/3003) Advanced mode (16-Mbyte address space) Instruction features 8/16/32-bit data transfer, arithmetic, logic instructions Signed unsigned multiply instructions bits bits, bits bits) Signed unsigned divide instructions bits bits, bits bits) accumulator function manipulation instructions with register-indirect specification positions
Table Features (cont)
Feature Memory Interrupt controller controller Description RAM: bytes Nine external interrupt pins: NMI, IRQ0 IRQ7 internal interrupts Three selectable interrupt priority levels Address space partitioned into eight areas, with independent specifications each area Chip select output available each area 8-bit access 16-bit access selectable each area Two-state three-state access selectable each area Selection four wait modes arbitration function DRAM refresh Directly connectable 16-bit-wide DRAM CAS-before-RAS refresh Self-refresh mode selectable Pseudo-static refresh Self-refresh mode selectable Usable interval timer controller (DMAC) Short address mode Maximum eight channels available Selection mode, idle mode, repeat mode activated compare match/input capture interrupts from channels transmit-data-empty receive-data-full interrupts, external requests Full address mode Maximum four channels available Selection normal mode block transfer mode activated compare match/input capture interrupts from channels external requests, auto-request
Refresh controller
Table Features (cont)
Feature 16-bit integrated timer unit (ITU) Description Five 16-bit timer channels, capable processing pulse outputs pulse inputs 16-bit timer counter (channels multiplexed output compare/input capture pins (channels Operation synchronized (channels mode available (channels Phase counting mode available (channel Buffering available (channels Reset-synchronized mode available (channels Complementary mode available (channels DMAC activated compare match/input capture interrupt (channels Maximum 16-bit pulse output, using time base four 4-bit pulse output groups 16-bit group, 8-bit groups) Non-overlap mode available Output data transferred DMAC
Programmable timing pattern controller (TPC) Watchdog timer (WDT), channel Serial communication interface (SCI), channels converter
Reset signal generated overflow Reset signal output externally Usable interval timer Selection asynchronous synchronous mode Full duplex: transmit receive simultaneously On-chip baud-rate generator Resolution: bits Eight channels, with selection single scan mode Variable analog conversion voltage range Sample-and-hold function externally triggered
ports
input/output pins input-only pins
Table Features (cont)
Feature Description
Operating modes Four operating modes Mode Mode Mode Mode Mode Power-down state Other features Product lineup Address Space Mbyte Mbyte Mbyte Mbyte Address Pins Initial Max. Width Width bits bits bits bits bits bits bits bits
Sleep mode Software standby mode Hardware standby mode On-chip clock oscillator Model HD6413003RF HD6413003RVF HD6413003TF HD6413003TVF Package 112-pin (QFP-112) Oscillator Divide-by-2 oscillator oscillator Power Supply Voltage ±10% ±10%
Block Diagram
Figure shows internal block diagram.
Data
Port Port Data (upper) Data (lower) Address
EXTAL XTAL STBY RESO Port /BACK /BREQ /WAIT Port /CS1 /IRQ /CS2 /IRQ /CS3 /IRQ /RFSH/IRQ /IRQ /IRQ /DREQ3 Port /TEND3 /DREQ2 /TEND2 16-bit integrated timer unit (ITU) Watchdog timer (WDT) bytes Refresh controller controller (DMAC) Interrupt controller controller Clock osc. H8/300H
Address Port Port
/SCK /IRQ
Serial communication interface (SCI) channels
Programmable timing pattern controller (TPC)
/SCK /IRQ converter /RxD1 /RxD0 /TxD /TxD
Port /TP15/DREQ 1/ADTRG /TP7 /TIOCB /TP6 /TIOCA /TP5 /TIOCB /TP13 /TOCXB /TP12 /TOCXA /TP11 /TIOCB /TP10 /TIOCA /TP9 /TIOCB 6/TP14 /DREQ /TP8 /TIOCA
Port /TIOCB0 /TCLKD /TIOCA0 /TCLKC /TP4 /TIOCA 1/TP1 /TCLKB/TEND 0/TP0 /TCLKA/TEND AVCC AVSS VREF
Figure Block Diagram
Description
1.3.1 Arrangement Figure shows arrangement H8/3003's QFP-112 package.
/TP3 /TIOCB0/TCLKD /TP2 /TIOCA0/TCLKC /TP1 /TEND /TCLKB /TP0 /TEND /TCLKA
/TP7 /TIOCB2
/TP6 /TIOCA2
/TP5 /TIOCB1
/TP4 /TIOCA1
/RFSH/IRQ
/CS1 /IRQ
/CS2 /IRQ
/CS3 /IRQ
/CS0
/AN7
/AN6
/AN5
/AN4
/AN3
/AN2
/AN1
/AN0
AVSS
TIOCA3/TP TIOCB3/TP TIOCA4/TP10 TIOCB4/TP11 TOCXA4/TP12 TOCXB4/TP13 DREQ /TP14 ADTRG/DREQ /TP15 /TEND2 /DREQ2 /TEND3 /DREQ3 IRQ6 IRQ7 RESO TxD0 TxD1 RxD0 RxD1 4/SCK0 5/SCK1 AVCC XTAL EXTAL STBY /BACK /BREQ /WAIT
view
Figure Arrangement (QFP-112, View)
VREF
1.3.2 Functions Assignments Each Mode: Table lists QFP-112 assignments each mode. Table QFP-112 Assignments Each Mode
Mode PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 Name Mode PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 Mode PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 Mode PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5
Table QFP-112 Assignments Each Mode (cont)
Mode P40/D0*1 P41/D1*1 P42/D2*1 P43/D3*1 P44/D4*1 P45/D5*1 P46/D6*1 P47/D7*1 Name Mode P40/D0*2 P41/D1*2 P42/D2*2 P43/D3*2 P44/D4*2 P45/D5*2 P46/D6*2 P47/D7*2 Mode P40/D0* P41/D1* P42/D2* P43/D3* P44/D4* P45/D5* P46/D6* P47/D7* Mode
Notes: modes functions pins P40/D0 P47/D7 selected after reset, they changed software. modes functions pins P40/D0 D47/D7 selected after reset, they changed software.
Table QFP-112 Assignments Each Mode (cont)
Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Name Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL
Table QFP-112 Assignments Each Mode (cont)
Mode AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS Name Mode AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB Mode AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 Mode AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2
P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB
PA2/TP2/TIOCA0/TCLKC PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2
Functions
Table summarizes functions. Table Functions
Type Power Symbol QFP-112 Input Name Function Power: connection power supply Connect pins +5-V system power supply. Ground: connection ground Connect pins system power supply. connection crystal resonator. examples crystal resonator external clock input, section Clock Oscillator. connection crystal resonator input external clock signal. examples crystal resonator external clock input, section Clock Pulse Generator.
Input Input
Clock
XTAL
EXTAL
Input
Operating mode control
Output System clock: Supplies system clock external devices Input Mode mode setting operating mode, follows Operating Mode Mode Mode Mode Mode
Table Functions (cont)
Type Symbol QFP-112 Input Name Function Reset input: When driven low, this resets H8/3003
System control RESO STBY BREQ BACK
Output Reset output: Outputs reset signal external devices Input Input Standby: When driven low, this forces transition hardware standby mode request: Used external master request right from H8/3003
Output request acknowledge: Indicates that been granted external master Input Nonmaskable interrupt: Requests nonmaskable interrupt Interrupt request Maskable interrupt request pins
Interrupts
IRQ7 IRQ0
Input
Address
Output Address bus: Outputs address signals
Data control
Input/ output
Data bus: Bidirectional data
Output Chip select: Select signals areas Output Address strobe: Goes indicate valid address output address Output Read: Goes indicate reading from external address space Output High write: Goes indicate writing external address space; indicates valid data upper data (D15 D8). Output write: Goes indicate writing external address space; indicates valid data lower data D0). Input Wait: Requests insertion wait states cycles during access external address space
WAIT
Table Functions (cont)
Type Refresh controller Symbol RFSH QFP-112 Name Function
Output Refresh: Indicates refresh cycle Output address strobe RAS: address strobe signal DRAM connected area Output Column address strobe CAS: Column address strobe signal DRAM connected area used with DRAM. Write enable: Write enable signal DRAM connected area used with 2CAS DRAM.
Output Upper write: Write enable signal DRAM connected area used with DRAM. Upper column address strobe: Column address strobe signal DRAM connected area used with 2CAS DRAM.
Output Lower write: Write enable signal DRAM connected area used with DRAM. Lower column address strobe: Column address strobe signal DRAM connected area used with 2CAS DRAM.
controller (DMAC)
DREQ3 DREQ0 TEND3 TEND0 TCLKD TCLKA TIOCA4 TIOCA0 TIOCB4 TIOCB0 TOCXA4 TOCXB4
106,
Input
request DMAC activation requests
Output Transfer These signals indicate that DMAC ended data transfer Clock input External clock inputs Input capture/output compare GRA4 GRA0 output compare input capture, output Input capture/output compare GRB4 GRB0 output compare input capture, output
16-bit integrated time unit (ITU)
Input 111, 109, 112, 110, Input/ output Input/ output
Output Output compare XA4: output Output Output compare XB4: output
Table Functions (cont)
Type Symbol QFP-112 Name Function
Programmable TP15 timing pattern controller (TPC) Serial communication interface (SCI) TxD1, TxD0 RxD1, RxD0 SCK0, SCK1 converter ADTRG AVCC
Output output Pulse output Output Transmit data (channels data output Input Input/ output Input Input Input Receive data (channels data input Serial clock (channels clock input/output Analog Analog input pins trigger: External trigger input starting conversion Power supply converter. Connect system power supply when using converter. Ground converter. Connect system ground when using converter. Reference voltage input converter. Connect system power supply when using converter. Port Eight input/output pins. direction each selected port data direction register (P4DDR). Port Four input/output pins. direction each selected port data direction register (P5DDR). Port Three input/output pins. direction each selected port data direction register (P6DDR). Port Eight input pins Port Five input/output pins. direction each selected port data direction register (P8DDR).
AVSS
Input
VREF
Input
ports
Input/ output Input/ output Input/ output Input
Input/ output
Table Functions (cont)
Type ports Symbol QFP-112 Input/ output Name Function Port input/output pins. direction each selected port data direction register (P9DDR). Port Eight input/output pins. direction each selected port data direction register (PADDR). Port Eight input/output pins. direction each selected port data direction register (PBDDR). Port Eight input/output pins. direction each selected port data direction register (PCDDR).
Input/ output Input/ output Input/ output
Section
Overview
H8/300H high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 CPU. H8/300H sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. 2.1.1 Features H8/300H following features. Upward compatibility with H8/300 execute H8/300 series object programs without alteration General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-two basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) @(d:24, ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8, @(d:16, PC)] Memory indirect [@@aa:8]
16-Mbyte linear address space
High-speed operation frequently-used instructions execute four states Maximum clock frequency: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 8-bit register-register divide: 16-bit register-register multiply: 1.375 16-bit register-register divide: 1.375
operating modes Normal mode (not available H8/3003) Advanced mode
Low-power mode Transition power-down state SLEEP instruction
2.1.2 Differences from H8/300 comparison H8/300 CPU, H8/300H following enhancements. More general registers Eight 16-bit registers have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Normal mode supports same 64-kbyte address space H8/300 CPU. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Data transfer, arithmetic, logic instructions operate 32-bit data. Signed multiply/divide instructions other instructions have been added.
Operating Modes
H8/300H operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports Mbytes. figure 2-1. H8/3003 uses only advanced mode.
Normal mode
Maximum kbytes, program data areas combined
operating modes Maximum Mbytes, program data areas combined
Advanced mode
Note: Normal mode available H8/3003.
Figure Operating Modes
Address Space
maximum address space H8/300H Mbytes. H8/3003 operating modes (MCU modes), providing 1-Mbyte address space, other supporting full Mbytes. Figure shows H8/3003's address ranges. further details section 3.6, Memory Each Operating Mode. 1-Mbyte operating mode uses 20-bit addressing. upper bits effective addresses ignored.
H'00000
H'000000
H'FFFFF
H'FFFFFF 1-Mbyte mode 16-Mbyte mode
Figure Memory
Register Configuration
2.4.1 Overview H8/300H internal registers shown figure 2-3. There types registers: general registers control registers.
General Registers (ERn) Control Registers (CR) Legend Stack pointer Program counter CCR: Condition code register Interrupt mask User interrupt mask Half-carry flag User Negative flag Zero flag Overflow flag Carry flag (SP)
Figure Registers
2.4.2 General Registers H8/300H eight 32-bit general registers. These general registers functionally alike used without distinction between data registers address registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers registers
registers
registers
Figure Usage General Registers
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area (ER7) Stack area
Figure Stack 2.4.3 Control Registers control registers 24-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word) multiple bytes, least significant ignored. When instruction fetched, least significant regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when accepted regardless setting. start exception-handling sequence. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details section Interrupt Controller.
5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Indicates most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted
carry flag also used accumulator manipulation instructions. Some instructions leave flag bits unchanged. Operations performed LDC, STC, ANDC, ORC, XORC instructions. flags used conditional branch (Bcc) instructions. action each instruction flag bits, appendix A.1, Instruction List. bits, section Interrupt Controller. 2.4.4 Initial Register Values reset exception handling, initialized value loaded from vector table, other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer must therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
H8/300H process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats Figures show data formats general registers.
Data Type
General Register
Data Format Don't care
1-bit data
1-bit data
Don't care
4-bit data
Upper digit Lower digit
Don't care
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Figure General Register Data Formats
Data Type
General Register
Data Format
Word data
Word data
Longword data Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats 2.5.2 Memory Data Formats Figure shows data formats memory. H8/300H access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type
Address
Data Format
1-bit data Byte data Word data Address Address Address Address Address Longword data Address Address Address
Figure Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
Instruction
2.6.1 Instruction Overview H8/300H types instructions, which classified table 2-1. Table Instruction Classification
Function Data transfer Arithmetic operations Logic operations Shift operations manipulation Branch System control Block data transfer Total types Notes: POP.W identical MOV.W @SP+, PUSH.W identical MOV.W @-SP. POP.L identical MOV.L @SP+, PUSH.L identical MOV.L @-SP. They available H8/3003. generic branching instruction. Instruction MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*2 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*3, JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Types
2.6.2 Instructions Addressing Modes Table indicates instructions available H8/300H CPU. Table Instructions Addressing Modes
Addressing Modes (d:16, (d:24, @ERn+/ @ERn ERn) ERn) @-ERn aa:8 aa:16 (d:8, aa:24 (d:16, aa:8
Function Data transfer
Instruction POP, PUSH MOVFPE, MOVTPE
Implied
Arithmetic ADD, operations
ADDX, SUBX ADDS, SUBS INC, DAA, DIVXU, MULXS, MULXU, DIVXS EXTU, EXTS Logic AND, operations Shift instructions manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer Legend Byte Word Longword
2.6.3 Tables Instructions Classified Function Tables 2-10 summarize instructions each functional category. operation notation used these tables defined next. Operation Notation
(EAd) (EAs) #IMM disp :3/:8/:16/:24 General register (destination)* General register (source)* General register* General register (32-bit register address register) Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move (logical complement) 16-, 24-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit data address registers (ER0 ER7).
Table Data Transfer Instructions
Instruction Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. MOVFPE (EAs) Cannot used H8/3003. MOVTPE (EAs) Cannot used H8/3003. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, Similarly, POP.L identical MOV.L @SP+, ERn. PUSH @-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. Similarly, PUSH.L identical MOV.L ERn, @-SP. Note: Size refers operand size. Byte Word Longword
Table Arithmetic Operation Instructions
Instruction Size* ADD, B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow data general registers, immediate data data general register. B/W/L Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. MULXS Performs signed multiplication data general registers: either bits bits bits bits bits bits. Note: Size refers operand size. Byte Word Longword
ADDX, SUBX
INC,
ADDS, SUBS DAA,
MULXU
Table Arithmetic Operation Instructions (cont)
Instruction Size* DIVXU Function Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder. DIVXS Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder, bits bits 16-bit quotient 16-bit remainder. B/W/L #IMM Compares data general register with data another general register with immediate data, sets according result. B/W/L Takes two's complement (arithmetic complement) data general register. EXTS (sign extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, extending sign bit. EXTU (zero extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, padding with zeros. Note: Size refers operand size. Byte Word Longword
Table Logic Operation Instructions
Instruction Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data. B/W/L #IMM Performs logical operation general register another general register immediate data. B/W/L #IMM Performs logical exclusive operation general register another general register immediate data. B/W/L Takes one's complement general register contents. Note: Size refers operand size. Byte Word Longword
Table Shift Instructions
Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR B/W/L Function (shift) Performs arithmetic shift general register contents. B/W/L (shift) Performs logical shift general register contents. B/W/L (rotate) Rotates general register contents. B/W/L (rotate) Rotates general register contents through carry bit.
Note: Size refers operand size. Byte Word Longword
Table Manipulation Instructions
Instruction Size* BSET Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower bits general register. BCLR (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower bits general register. BNOT (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower bits general register. BTST (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower bits general register. BAND (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. BIAND (<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. Note: Size refers operand size. Byte
Table Manipulation Instructions (cont)
Instruction Size* Function (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. BIOR (<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. BXOR (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. BIXOR (<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. BILD (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. BIST (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data. Note: Size refers operand size. Byte
Table Branching Instructions
Instruction Size Function Branches specified address specified condition true. branching conditions listed below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
Table System Control Instructions
Instruction Size* TRAPA SLEEP Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) Moves source operand contents condition code register. condition code register size byte, transfer from memory, data read word access. (EAd) Transfers contents destination location. condition code register size byte, transfer memory, data written word access. ANDC #IMM Logically ANDs condition code register with immediate data. #IMM Logically condition code register with immediate data. XORC #IMM Logically exclusive-ORs condition code register with immediate data. Only increments program counter. Note: Size refers operand size. Byte Word
Table 2-10 Block Transfer Instruction
Instruction Size EEPMOV.B Function then repeat @ER5+ @ER6+, until else next; then repeat @ER5+ @ER6+, until else next; Transfers data block according parameters general registers ER5, ER6. Size block (bytes) ER5: Starting source address ER6: Starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
2.6.4 Basic Instruction Formats H8/300H instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. 24-bit address displacement treated 32-bit data which first bits (H'00). Condition Field: Specifies branching condition instructions. Figure shows examples instruction formats.
Operation field only Operation field register fields ADD.B etc. NOP, RTS, etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) MOV.B @(d:16, Rn),
Figure Instruction Formats
2.6.5 Notes Manipulation Instructions BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify byte, then write byte back. Care required when these instructions used access registers with write-only bits, access ports. BCLR instruction used clear flags on-chip registers. interrupt-handling routine, example, known that flag necessary read flag ahead time.
Addressing Modes Effective Address Calculation
2.7.1 Addressing Modes H8/300H supports eight addressing modes listed table 2-11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. manipulation instructions register direct, register indirect, absolute (@aa:8) addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2-11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16, ERn)/@d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, @@aa:8
Register Direct-Rn: register field instruction code specifies 16-, 32-bit register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn), lower bits which contain address operand. Register Indirect with Displacement-@(d:16, ERn) @(d:24, ERn): 16-bit 24-bit displacement contained instruction code added contents address register (ERn) specified register field instruction, lower bits specify address memory operand. 16-bit displacement sign-extended when added. Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) lower bits which contain address memory operand. After operand accessed, added address register contents bits) stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, lower bits result become address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, resulting register value should even. Absolute Address-@aa:8, @aa:16, @aa:24: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24). 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 24-bit absolute address access entire address space. Table 2-12 indicates accessible address ranges.
Table 2-12 Absolute Address Access Ranges
Absolute Address bits (@aa:8) bits (@aa:16) 1-Mbyte Modes H'FFF00 H'FFFFF (1048320 1048575) H'00000 H'07FFF, H'F8000 H'FFFFF 32767, 1015808 1048575) H'00000 H'FFFFF 1048575) 16-Mbyte Modes H'FFFF00 H'FFFFFF (16776960 16777215) H'000000 H'007FFF, H'FF8000 H'FFFFFF 32767, 16744448 16777215) H'000000 H'FFFFFF 16777215)
bits (@aa:24)
Immediate-#xx:8, #xx:16, #xx:32: instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. instruction codes ADDS, SUBS, INC, instructions contain immediate data implicitly. instruction codes some manipulation instructions contain 3-bit immediate data specifying number. TRAPA instruction code contains 2-bit immediate data specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction code signextended bits added 24-bit contents generate 24-bit branch address. value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. memory operand accessed longword access. first byte memory operand ignored, generating 24-bit branch address. figure 2-10. upper bits 8-bit absolute address assumed (H'0000), address range (H'000000 H'0000FF). Note that first part this range also exception vector area. further details section Interrupt Controller.
Specified @aa:8
Reserved
Branch address
Figure 2-10 Memory-Indirect Branch Address Specification When word-size longword-size memory operand specified, when branch address specified, specified memory address odd, least significant regarded accessed data instruction code therefore begins preceding address. section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation Table 2-13 explains effective address calculated each addressing mode. 1-Mbyte operating modes upper bits calculated address ignored order generate 20-bit effective address.
Table 2-13 Effective Address Calculation
Effective Address Calculation Operand general register contents General register contents General register contents Effective Address
Addressing Mode Instruction Format
Register direct (Rn)
Register indirect (@ERn)
Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
Sign extension
disp
disp
Register indirect with post-increment pre-decrement General register contents
Register indirect with post-increment @ERn+
General register contents byte operand, word operand, longword operand
Register indirect with pre-decrement @-ERn
Table 2-13 Effective Address Calculation (cont)
Effective Address Calculation H'FFFF Effective Address
Addressing Mode Instruction Format
Sign extension
Absolute address @aa:8
@aa:16
@aa:24
Sign extension
Immediate #xx:8, #xx:16, #xx:32
Operand immediate data
Program-counter relative @(d:8, @(d:16,
contents disp
disp
Table 2-13 Effective Address Calculation (cont)
Effective Address Calculation Effective Address
Addressing Mode Instruction Format
H'0000 Memory contents
Memory indirect @@aa:8
Legend disp: IMM: abs:
Register field Operation field Displacement Immediate data Absolute address
Processing States
2.8.1 Overview H8/300H five processing states: program execution state, exception-handling state, power-down state, reset state, bus-released state. power-down state includes sleep mode, software standby mode, hardware standby mode. Figure 2-11 classifies processing states. Figure 2-13 indicates state transitions.
Processing states
Program execution state executes program instructions sequence Exception-handling state transient state which executes hardware sequence (saving CCR, fetching vector, etc.) response reset, interrupt, other exception
Bus-released state external been released response request signal from master other than Reset state on-chip supporting modules initialized halted
Power-down state halted conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2-11 Processing States
2.8.2 Program Execution State this state executes program instructions normal sequence. 2.8.3 Exception-Handling State exception-handling state transient state that occurs when alters normal program flow reset, interrupt, trap instruction. fetches starting address from exception vector table branches that address. interrupt trap exception handling references stack pointer (ER7) saves program counter condition code register. Types Exception Handling Their Priority: Exception handling performed resets, interrupts, trap instructions. Table 2-14 indicates types exception handling their priority. Trap instruction exceptions accepted times program execution state. Table 2-14 Exception Handling Types Priority
Priority Type Exception Detection Timing High Reset Interrupt Synchronized with clock instruction execution exception handling* When TRAPA instruction executed Start Exception Handling Exception handling starts immediately when changes from high When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed
Trap instruction
Note: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling.
Figure 2-12 classifies exception sources. further details about exception sources, vector numbers, vector addresses, section Exception Handling, section Interrupt Controller.
Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction
Figure 2-12 Classification Exception Sources
release request Program execution state release request Exception Bus-released state exception handling Exception-handling state
SLEEP instruction with SSBY Sleep mode
Interrupt NMI, interrupt
SLEEP instruction with SSBY
Software standby mode
STBY Reset state*1
Hardware standby mode Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2-13 State Transitions
2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling highest priority. reset state entered when signal goes low. Reset exception handling starts after that, when changes from high. When reset exception handling starts fetches start address from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception-handling sequence immediately after ends. Interrupt Exception Handling Trap Instruction Exception Handling: When these exception-handling sequences begin, references stack pointer (ER7) pushes program counter condition code register stack. Next, system control register (SYSCR) sets condition code register cleared sets both condition code register Then fetches start address from exception vector table execution branches that address. Figure 2-14 shows stack after exception-handling sequence.
SP-4 SP-3 SP-2 SP-1 (ER7) Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling starts Legend CCR: Condition code register Stack pointer
Pushed stack
After exception handling ends
Notes: address first instruction executed after return from exception-handling routine. Registers must saved restored word access longword access, starting even address.
Figure 2-14 Stack Structure after Exception Handling
2.8.5 Bus-Released State this state released master other than CPU, response request. masters other than controller, refresh controller, external master. While released, halts except internal operations. Interrupt requests accepted. details section 6.3.7, Arbiter Operation 2.8.6 Reset State When input goes current processing stops enters reset state. condition code register reset. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details section Watchdog Timer. 2.8.7 Power-Down State power-down state stops operating conserve power. There three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: transition sleep mode made SLEEP instruction executed while SSBY cleared system control register (SYSCR). operations stop immediately after execution SLEEP instruction, contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SYSCR. clock halt on-chip supporting modules stop operating. on-chip supporting modules reset, long specified voltage supplied contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY input goes low. software standby mode, clock halt on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained. further information section Power-Down State.
Basic Operational Timing
2.9.1 Overview H8/300H operates according system clock interval from rise system clock next rise referred "state." memory cycle cycle consists three states. uses different methods access on-chip memory, on-chip supporting modules, external address space. Access external address space controlled controller. 2.9.2 On-Chip Memory Access Timing On-chip memory accessed states. data bits wide, permitting both byte word access. Figure 2-15 shows on-chip memory access cycle. Figure 2-16 indicates states.
cycle state Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data Address state
Figure 2-15 On-Chip Memory Access Cycle
Address Address
High High impedance
Figure 2-16 States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing on-chip supporting modules accessed three states. data bits wide, depending register being accessed. Figure 2-17 shows on-chip supporting module access timing. Figure 2-18 indicates states.
cycle state Address state state
Address Internal read signal Internal data
Read access
Read data
Internal write signal Write access Internal data Write data
Figure 2-17 Access Cycle On-Chip Supporting Modules
Address
Address
High High impedance
Figure 2-18 States during Access On-Chip Supporting Modules 2.9.4 Access External Address Space external address space divided into eight areas (areas Bus-controller settings determine whether each area accessed 8-bit 16-bit bus, whether accessed three states. details section Controller.
Section Operating Modes
Overview
3.1.1 Operating Mode Selection H8/3003 four operating modes (modes that selected mode pins (MD2 MD0) indicated table 3-1. input these pins determines size address space initial mode. Table Operating Mode Selection
Mode Pins Operating Mode Mode Mode Mode Mode Address Space Mbyte Mbyte Mbytes Mbytes Description Initial Mode*1 bits bits bits bits On-Chip Enabled*2 Enabled*2 Enabled*2 Enabled*2
Notes: modes, 8-bit 16-bit data selected per-area basis settings made area width control register (ABWCR). details section Controller. enable (RAME) system control register (SYSCR) cleared these addresses become external addresses.
address space size there choices: Mbyte Mbytes. external data either bits wide depending settings area width control register (ABWCR). 8-bit access selected areas, external data bits wide. details section Controller. Modes externally expanded modes that enable access external memory peripheral devices. Modes support maximum address space Mbyte. Modes support maximum address space Mbytes. H8/3003 only used modes inputs mode pins must select these four modes. inputs mode pins must changed during operation.
3.1.2 Register Configuration H8/3003 mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR). Table summarizes these registers. Table Registers
Address* H'FFF1 H'FFF2 Name Mode control register System control register Abbreviation MDCR SYSCR Initial Value Undetermined H'0B
Note: lower bits address indicated.
Mode Control Register (MDCR)
MDCR 8-bit read-only register that indicates current operating mode H8/3003.
Initial value Read/Write Reserved bits MDS2 MDS1 MDS0
Reserved bits
Mode select Bits indicating current operating mode
Note: Determined pins
Bits 6-Reserved: Read-only bits, always read Bits 3-Reserved: Read-only bits, always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate logic levels pins (the current operating mode). MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits. mode (MD2 MD0) levels latched when MDCR read.
System Control Register (SYSCR)
SYSCR 8-bit register that controls operation H8/3003.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME enable Enables disables on-chip Reserved edge select Selects valid edge input User enable Selects whether user interrupt mask Standby timer select These bits select waiting time recovery from software standby mode Software standby Enables transition software standby mode
7-Software Standby (SSBY): Enables transition software standby mode. (For further information about software standby mode section Power-Down State.) When software standby mode exited external interrupt, this remains clear this bit, write
SSBY Description SLEEP instruction causes transition sleep mode SLEEP instruction causes transition software standby mode (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select length time on-chip supporting modules wait internal clock oscillator settle when software standby mode exited external interrupt. these bits that waiting time will least system clock rate. further information about waiting time selection, section 17.4.3, Selection Oscillator Waiting Time after Exit from Software Standby Mode.
STS2 STS1 STS0 Description Waiting time 8192 states Waiting time 16384 states Waiting time 32768 states Waiting time 65536 states Waiting time 131072 states Waiting time states (Initial value)
3-User Enable (UE): Selects whether condition code register user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge interrupt requested rising edge (Initial value)
1-Reserved: Read-only bit, always read 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized rising edge signal. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
Operating Mode Descriptions
3.4.1 Mode Address pins enabled, permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.2 Mode Address pins enabled, permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. 3.4.3 Mode Address pins enabled, permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.4 Mode Address pins enabled, permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits.
Functions Each Operating Mode
functions ports vary depending operating mode. Table indicates their functions each operating mode. Table Functions Each Mode
Port Port Port Mode P40* Mode Mode P40* Mode
Note: Initial state. mode switched settings ABWCR. These pins function 8-bit mode, 16-bit mode.
Memory Each Operating Mode
Figure shows memory modes address space divided into eight areas. initial mode differs between modes also between modes address locations on-chip on-chip registers differ between 1-Mbyte modes (modes 16-Mbyte modes (modes address range specifiable 8and 16-bit absolute addressing modes (@aa:8 @aa:16) also differs.
Modes (1-Mbyte modes) H'00000 Vector table H'000000
Modes (16-Mbyte modes) Vector table
H'07FFF Area Area Area Area Area Area Area Area
16-bit absolute addresses
H'007FFFF Area H'1FFFFF H'200000 Area H'3FFFFF H'400000 Area H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 Area H'BFFFFF H'C00000 External address space
16-bit absolute addresses
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000
Area
Area H'F8000 H'FFD0F H'FFD10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C F'FFFFF
On-chip RAM* 16-bit absolute addresses 8-bit absolute addresses
Area H'DFFFFF H'E00000 Area
External address space On-chip registers
H'FF8000 H'FFFD0F H'FFFD10 H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C On-chip registers H'FFFFFF
On-chip RAM* 16-bit absolute addresses 8-bit absolute addresses
External address space
Note: External addresses accessed clearing RAME system control register (SYSCR).
Figure Memory Each Operating Mode
Section Exception Handling
Overview
4.1.1 Exception Handling Types Priority table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4-1. more exceptions occur simultaneously, they accepted processed priority order. Trap instruction exceptions accepted times program execution state. Table Exception Types Priority
Priority Exception Type High Reset Interrupt Start Exception Handling Starts immediately after low-to-high transition Interrupt requests handled when execution current instruction handling current exception completed
Trap instruction (TRAPA) Started execution trap instruction (TRAPA)
4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions interrupts handled follows. program counter (PC) condition code register (CCR) pushed onto stack. interrupt mask vector address corresponding exception source generated, program execution starts from that address.
reset exception, steps above carried out.
4.1.3 Exception Vector Table exception sources classified shown figure 4-1. Different vectors assigned different exception sources. Table lists exception sources their vector addresses.
Reset External interrupts: NMI, IRQ7 Exception sources Interrupts Internal interrupts: interrupts from on-chip supporting modules
Trap instruction
Figure Exception Sources Table Exception Vector Table
Exception Source Reset Reserved system Vector Number Vector Address*1 H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'00F0 H'00F3
External interrupt (NMI) Trap instruction sources)
External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 External interrupt IRQ6 External interrupt IRQ7 Internal interrupts*2
Notes: Lower bits address. internal interrupt vectors, section 5.3.3, Interrupt Vector Table.
Reset
4.2.1 Overview reset highest-priority exception. When goes low, processing halts H8/3003 enters reset state. reset initializes internal state registers on-chip supporting modules. Reset exception handling begins when changes from high. H8/3003 also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Sequence H8/3003 enters reset state when goes low. ensure that H8/3003 reset, hold least power-up. reset H8/3003 during operation, hold least system clock cycles. appendix D.2, States Reset, states pins reset state. When goes high after being held necessary time, H8/3003 starts reset exception handling follows. internal state registers on-chip supporting modules initialized, CCR. contents reset vector address (H'0000 H'0003) read, program execution starts from address indicated vector address.
Figure shows reset sequence modes Figure shows reset sequence modes
Vector fetch
Internal processing
Prefetch first program instruction
Address
Figure Reset Sequence (Modes
High
(10)
(1), (3), (5), (2), (4), (6), (10)
Address reset vector: H'00000, H'00001, H'00002, H'00003 Start address (contents reset vector) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Vector fetch
Internal processing
Prefetch first program instruction
Address
High
(1), (2),
Address reset vector: H'00000, H'00002 Start address (contents reset vector) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Figure Reset Sequence (Modes 4.2.3 Interrupts after Reset interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. first instruction program always executed immediately after reset state ends. This instruction should initialize stack pointer (example: MOV.L #xx:32, SP).
Interrupts
Interrupt exception handling requested nine external sources (NMI, IRQ0 IRQ7) internal sources on-chip supporting modules. Figure classifies interrupt sources indicates number interrupts each type. on-chip supporting modules that request interrupts watchdog timer (WDT), refresh controller, 16-bit integrated timer-pulse unit (ITU), controller (DMAC), serial communication interface (SCI), converter. Each interrupt source separate vector address. highest-priority interrupt always accepted. Interrupts controlled interrupt controller. interrupt controller assign interrupts other than priority levels, arbitrate between simultaneous interrupts. Interrupt priorities assigned interrupt priority registers (IPRA IPRB) interrupt controller. details interrupts section Interrupt Controller.
External interrupts Interrupts
Refresh controller (15) DMAC converter
Internal interrupts
Notes: Numbers parentheses number interrupt sources. When watchdog timer used interval timer, generates interrupt request every counter overflow. When refresh controller used interval timer, generates interrupt request compare match.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. system control register (SYSCR), exception handling sequence sets CCR. bits both TRAPA instruction fetches start address from vector table entry corresponding vector number from which specified instruction code.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
Note: modes only bits valid; upper bits ignored.
Figure Stack after Completion Exception Handling
Notes Stack Usage
When accessing word data longword data, H8/3003 regards lowest address stack should always accessed word access longword access, value stack pointer (SP, ER7) should always kept even. following instructions save registers: PUSH.W MOV.W @-SP) PUSH.L MOV.L ERn, @-SP) following instructions restore registers: POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB
H'FFFEFC H'FFFEFD
H'FFFEFF
TRAPA instruction executed
MOV. RIL, @-ER7
H'FFFEFF Legend CCR: Condition code register Program counter R1L: General register Stack pointer
Data saved above
contents lost
Note: diagram illustrates modes
Figure Operation when Value
Section Interrupt Controller
Overview
5.1.1 Features interrupt controller following features: Interrupt priority registers (IPRs) setting interrupt priorities Interrupts other than assigned priority levels module-by-module basis interrupt priority registers (IPRA IPRB). Three-level masking bits condition code register (CCR) Independent vector addresses interrupts independently vectored; interrupt service routine does have identify interrupt source. Nine external interrupt pins highest priority always accepted; either rising falling edge selected. each IRQ0 IRQ7, sensing falling edge level sensing selected independently.
5.1.2 Block Diagram Figure shows block diagram interrupt controller.
ISCR input input ADIE input section Priority decision logic IPRA, IPRB
Interrupt request Vector number
Interrupt controller SYSCR Legend IER: IPRA: IPRB: ISCR: ISR: SYSCR: Interrupt mask enable register Interrupt priority register Interrupt priority register sense control register status register System control register User enable User bit/interrupt mask
Figure Interrupt Controller Block Diagram
5.1.3 Configuration Table lists interrupt pins. Table Interrupt Pins
Name Nonmaskable interrupt Abbreviation Input Input Function Nonmaskable interrupt, rising edge falling edge selectable Maskable interrupts, falling edge level sensing selectable
External interrupt request IRQ7 IRQ0
5.1.4 Register Configuration Table lists registers interrupt controller. Table Interrupt Controller Registers
Address*1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFF9 Name System control register sense control register enable register status register Interrupt priority register Interrupt priority register Abbreviation SYSCR ISCR IPRA IPRB R/(W)*2 Initial Value H'0B H'00 H'00 H'00 H'00 H'00
Notes: Lower bits address. Only written, clear flags.
Register Descriptions
5.2.1 System Control Register (SYSCR) SYSCR 8-bit readable/writable register that controls software standby mode, selects action CCR, selects edge, enables disables on-chip RAM. Only bits described here. bits section 17.2, Register Configuration. section 15.2, System Control Register (SYSCR). SYSCR initialized H'0B reset hardware standby mode. initialized software standby mode.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME
enable Reserved Standby timer select Software standby edge select Selects input edge User enable Selects whether user interrupt mask
3-User Enable (UE): Selects whether user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects input edge.
NMIEG Description Interrupt requested falling edge input Interrupt requested rising edge input (Initial value)
5.2.2 Interrupt Priority Registers (IPRA, IPRB) IPRA IPRB 8-bit readable/writable registers that control interrupt priority.
Interrupt Priority Register (IPRA): IPRA 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level refresh controller interrupt requests Priority level Selects priority level IRQ4 interrupt requests Priority level Selects priority level interrupt requests Priority level Selects priority level IRQ1 interrupt requests Priority level Selects priority level interrupt requests
IPRA initialized H'00 reset hardware standby mode.
7-Priority Level (IPRA7): Selects priority level IRQ0 interrupt requests.
IPRA7 Description IRQ0 interrupt requests have priority level (low priority) IRQ0 interrupt requests have priority level (high priority) (Initial value)
6-Priority Level (IPRA6): Selects priority level IRQ1 interrupt requests.
IPRA6 Description IRQ1 interrupt requests have priority level (low priority) IRQ1 interrupt requests have priority level (high priority) (Initial value)
5-Priority Level (IPRA5): Selects priority level IRQ2 IRQ3 interrupt requests.
IPRA5 Description IRQ2 IRQ3 interrupt requests have priority level (low priority) IRQ2 IRQ3 interrupt requests have priority level (high priority) (Initial value)
4-Priority Level (IPRA4): Selects priority level IRQ4 IRQ7 interrupt requests.
IPRA4 Description IRQ4 IRQ7 interrupt requests have priority level (low priority) IRQ4 IRQ7 interrupt requests have priority level (high priority) (Initial value)
3-Priority Level (IPRA3): Selects priority level refresh controller interrupt requests.
IPRA3 Description refresh controller interrupt requests have priority level (low priority) (Initial value)
refresh controller interrupt requests have priority level (high priority)
2-Priority Level (IPRA2): Selects priority level channel interrupt requests.
IPRA2 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
1-Priority Level (IPRA1): Selects priority level channel interrupt requests.
IPRA1 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
0-Priority Level (IPRA0): Selects priority level channel interrupt requests.
IPRA0 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
Interrupt Priority Register (IPRB): IPRB 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRB7 IPRB6 IPRB5 IPRB4 IPRB3 IPRB2 IPRB1
Reserved Priority level Selects priority level converter interrupt request Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level DMAC group interrupt requests (channels Priority level Selects priority level DMAC group interrupt requests (channels Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests
IPRB initialized H'00 reset hardware standby mode.
7-Priority Level (IPRB7): Selects priority level channel interrupt requests.
IPRB7 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
6-Priority Level (IPRB6): Selects priority level channel interrupt requests.
IPRB6 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
5-Priority Level (IPRB5): Selects priority level DMAC group interrupt requests (channels
IPRB5 Description DMAC group interrupt requests (channels have priority level (low priority) (Initial value)
DMAC group interrupt requests (channels have priority level (high priority)
4-Priority Level (IPRB4): Selects priority level DMAC group interrupt requests (channels
IPRB4 Description DMAC group interrupt requests (channels have priority level (low priority) (Initial value)
DMAC group interrupt requests (channels have priority level (high priority)
3-Priority Level (IPRB3): Selects priority level channel interrupt requests.
IPRB3 Description SCI0 interrupt requests have priority level (low priority) SCI0 interrupt requests have priority level (high priority) (Initial value)
2-Priority Level (IPRB2): Selects priority level channel interrupt requests.
IPRB2 Description SCI1 interrupt requests have priority level (low priority) SCI1 interrupt requests have priority level (high priority) (Initial value)
1-Priority Level (IPRB1): Selects priority level converter interrupt requests.
IPRB1 Description converter interrupt requests have priority level (low priority) converter interrupt requests have priority level (high priority) (Initial value)
0-Reserved: Although reserved, this written read.
5.2.3 Status Register (ISR) 8-bit readable/writable register that indicates status IRQ0 IRQ7 interrupt requests.
Initial value Read/Write IRQ7F R/(W)* IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*
IRQ0 flags These bits indicate interrupt request status Note: Only written, clear flags.
initialized H'00 reset hardware standby mode. Bits 0-IRQ7 IRQ0 Flags (IRQ7F IRQ0F): These bits indicate status IRQ7 IRQ0 interrupt requests.
Bits IRQ7F IRQ0F Description [Clearing conditions] (Initial value) written IRQnF after reading IRQnF flag when IRQnF IRQnSC IRQn input high, interrupt exception handling carried out. IRQnSC IRQn interrupt exception handling carried out. [Setting conditions] IRQnSC IRQn input low. IRQnSC IRQn input changes from high low.
Note:
5.2.4 Enable Register (IER) 8-bit readable/writable register that enables disables IRQ0 IRQ7 interrupt requests.
Initial value Read/Write IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
IRQ0 enable These bits enable disable interrupts
initialized H'00 reset hardware standby mode. Bits 0-IRQ7 IRQ0 Enable (IRQ7E IRQ0E): These bits enable disable IRQ7 IRQ0 interrupts.
Bits IRQ7E IRQ0E Description IRQ7 IRQ0 interrupts disabled IRQ7 IRQ0 interrupts enabled (Initial value)
5.2.5 Sense Control Register (ISCR) ISCR 8-bit readable/writable register that selects level sensing falling-edge sensing inputs pins IRQ7 IRQ0.
Initial value Read/Write
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
IRQ0 sense control These bits select level sensing falling-edge sensing interrupts
ISCR initialized H'00 reset hardware standby mode. Bits 0-IRQ7 IRQ0 Sense Control (IRQ7SC IRQ0SC): These bits selects whether interrupts IRQ7 IRQ0 requested level sensing pins IRQ7 IRQ0, falling-edge sensing.
Bits IRQ7SC IRQ0SC Description Interrupts requested when IRQ7 IRQ0 inputs Interrupts requested falling-edge input IRQ7 IRQ0 (Initial value)
Interrupt Sources
interrupt sources include external interrupts (NMI, IRQ0 IRQ7) internal interrupts. 5.3.1 External Interrupts There nine external interrupts: NMI, IRQ0 IRQ7. these, NMI, IRQ0, IRQ1, IRQ2 used exit software standby mode. NMI: highest-priority interrupt always accepted, regardless states bits CCR. NMIEG SYSCR selects whether interrupt requested rising falling edge input pin. interrupt exception handling vector number IRQ0 IRQ7 Interrupts: These interrupts requested input signals pins IRQ0 IRQ7. IRQ0 IRQ7 interrupts have following features. ISCR settings select whether interrupt requested level input pins IRQ0 IRQ7, falling edge. settings enable disable IRQ0 IRQ7 interrupts. Interrupt priority levels assigned four bits IPRA (IPRA7 IPRA4). status IRQ0 IRQ7 interrupt requests indicated ISR. flags cleared software.
Figure shows block diagram interrupts IRQ0 IRQ7.
IRQnSC IRQnF Edge/level sense circuit IRQn input Clear signal Note:
IRQnE
IRQn interrupt request
Figure Block Diagram Interrupts IRQ0 IRQ7
Figure shows timing setting interrupt flags (IRQnF).
IRQn input IRQnF
Figure Timing Setting IRQnF Interrupts IRQ0 IRQ7 have vector numbers These interrupts detected regardless whether corresponding input output. When using external interrupt input, clear chip select output, refresh output, input output. 5.3.2 Internal Interrupts Thirty-four internal interrupts requested from on-chip supporting modules. Each on-chip supporting module status flags indicating interrupt status, enable bits enabling disabling interrupts. Interrupt priority levels assigned IPRA IPRB. interrupt requests activate DMAC, which case interrupt request sent interrupt controller, bits disregarded.
5.3.3 Interrupt Vector Table Table lists interrupt sources, their vector addresses, their default priority order. default priority order, smaller vector numbers have higher priority. priority interrupts other than changed IPRA IPRB. priority order after reset default order shown table 5-3.
Table Interrupt Sources, Vector Addresses, Priority
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 WOVI (interval timer) (compare match) Reserved Watchdog timer Refresh controller Origin External pins Vector Number IMIA0 (compare match/input capture IMIB0 (compare match/input capture OVI0 (overflow Reserved IMIA1 (compare match/input capture IMIB1 (compare match/input capture OVI1 (overflow Reserved IMIA2 (compare match/input capture IMIB2 (compare match/input capture OVI2 (overflow Reserved channel channel channel Vector Address* H'001C H'001F H'0030 H'0033 H'0034 H0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'0064 H'0067 H'0068 H'006B H'006C H'006F H'0070 H'0073 H'0074 H'0077 H'0078 H'007B H'007C H'007F H'0080 H'0083 H'0084 H'0087 H'0088 H'008B H'008C H'008F IPRA0 IPRA1 IPRA2 IPRA3 IPRA4 IPRA7 IPRA6 IPRA5 Priority High
Note: Lower bits address.
Table Interrupt Sources, Vector Addresses, Priority (cont)
Interrupt Source IMIA3 (compare match/input capture IMIB3 (compare match/input capture OVI3 (overflow Reserved IMIA4 (compare match/input capture IMIB4 (compare match/input capture OVI4 (overflow Reserved DEND0A DEND0B DEND1A DEND1B DEND2A DEND2B DEND3A DEND3B ERI0 (receive error RXI0 (receive data full TXI0 (transmit data empty TEI0 (transmit ERI1 (receive error RXI1 (receive data full TXI1 (transmit data empty TEI1 (transmit (A/D end) channel channel DMAC group DMAC group channel Origin channel Vector Number Vector Address* H'0090 H'0093 H'0094 H'0097 H'0098 H'009B H'009C H'009F H'00A0 H'00A3 H'00A4 H'00A7 H'00A8 H'00AB H'00AC H'00AF H'00B0 H'00B3 H'00B4 H'00B7 H'00B8 H'00BB H'00BC H'00BF H'00C0 H'00C3 IPRB4 H'00C4 H'00C7 H'00C8 H'00CB H'00CC H'00CF H'00D0 H'00D3 IPRB3 H'00D4 H'00D7 H'00D8 H'00DB H'00DC H'00DF H'00E0 H'00E3 H'00E4 H'00E7 H'00E8 H'00EB H'00EC H'00EF H'00F0 H'00F3 IPRB1 IPRB2 IPRB5 IPRB6 Priority
IPRB7 High
Note: Lower bits address.
Interrupt Operation
5.4.1 Interrupt Handling Process H8/3003 handles interrupts differently depending setting bit. When interrupts controlled bit. When interrupts controlled bits. Table indicates interrupts handled setting combinations bits. interrupts always accepted except reset hardware standby states. interrupts interrupts from on-chip supporting modules have their enable bits. Interrupt requests ignored when enable bits cleared Table Settings Interrupt Handling
SYSCR Description interrupts accepted. Interrupts with priority level have higher priority. interrupts accepted except NMI. interrupts accepted. Interrupts with priority level have higher priority. interrupts with priority level accepted. interrupts accepted except NMI.
Interrupts IRQ0 IRQ7 interrupts from on-chip supporting modules masked CPU's CCR. Interrupts masked when unmasked when cleared Interrupts with priority level have higher priority. Figure flowchart showing interrupts accepted when
Program execution state
Interrupt requested? Priority level Pending
Save Read vector address Branch interrupt service routine
Figure Process Interrupt Acceptance when
interrupt condition occurs corresponding interrupt enable interrupt request sent interrupt controller. When interrupt controller receives more interrupt requests, selects highestpriority request, following interrupt priority settings, holds other requests pending. more interrupts with same setting requested simultaneously, interrupt controller follows priority order shown table 5-3. interrupt controller checks bit. cleared selected interrupt request accepted. only accepted; other interrupt requests held pending. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. interrupt exception handling, saved stack area. value that saved indicates address first instruction that will executed after return from interrupt service routine. Next CCR, masking interrupts except NMI. vector address accepted interrupt generated, interrupt service routine starts executing from address indicated contents vector address.
bits CPU's bits enable three-level masking IRQ0 IRQ7 interrupts interrupts from on-chip supporting modules. Interrupt requests with priority level masked when unmasked when cleared Interrupt requests with priority level masked when bits both unmasked when either cleared example, interrupt enable bits interrupt requests IPRA H'20, IPRB H'00 (giving IRQ2 IRQ3 interrupt requests priority over other interrupts), interrupts masked follows: interrupts unmasked (priority order: IRQ2 IRQ3 >IRQ0 only NMI, IRQ2, IRQ3 unmasked. interrupts masked except NMI.
Figure shows transitions among above states.
interrupts unmasked Only NMI, unmasked
Exception handling,
Exception handling,
interrupts masked except
Figure Interrupt Masking State Transitions (Example) Figure flowchart showing interrupts accepted when interrupt condition occurs corresponding interrupt enable interrupt request sent interrupt controller. When interrupt controller receives more interrupt requests, selects highestpriority request, following interrupt priority settings, holds other requests pending. more interrupts with same setting requested simultaneously, interrupt controller follows priority order shown table 5-3. interrupt controller checks bit. cleared selected interrupt request accepted regardless setting, regardless bit. cleared only interrupts with priority level accepted; interrupt requests with priority level held pending. both only accepted; other interrupt requests held pending. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. interrupt exception handling, saved stack area. value that saved indicates address first instruction that will executed after return from interrupt service routine. bits CCR, masking interrupts except NMI. vector address accepted interrupt generated, interrupt service routine starts executing from address indicated contents vector address.
Program execution state
Interrupt requested? Priority level Pending
Save Read vector address Branch interrupt service routine
Figure Process Interrupt Acceptance when
Interrupt accepted
5.4.2 Interrupt Sequence
Interrupt level decision wait instruction Instruction Internal prefetch processing Stack Vector fetch
Prefetch interrupt Internal service routine processing instruction
Interrupt request signal (11) (13)
High (10) (12) (14)
Figure shows interrupt sequence mode when program code stack external memory area accessed states 16-bit bus.
Figure Interrupt Sequence (Mode Two-State Access, Stack External Memory)
Instruction prefetch address (not executed; return address, same contents) (2), Instruction code (not executed) Instruction prefetch address (not executed)
(6), saved stack (9), (11) Vector address (10), (12) Starting address interrupt service routine (contents vector address) (13) Starting address interrupt service routine; (13) (10), (12) (14) First instruction interrupt service routine
Note: Mode with program code stack external memory area accessed states 16-bit bus.
5.4.3 Interrupt Response Time Table indicates interrupt response time from occurrence interrupt request until first instruction interrupt service routine executed. Table Interrupt Response Time
External Memory On-Chip Memory 8-Bit States States 31*4 12*4 12*4 12*4 16-Bit States States 25*4
Item Total Interrupt priority decision Maximum number states until current instruction Saving stack Vector fetch Instruction prefetch*2 Internal processing*3
Notes: state internal interrupts. Prefetch after interrupt accepted prefetch first instruction interrupt service routine. Internal processing after interrupt accepted internal processing after prefetch. number states increases wait states inserted external memory access.
Usage Notes
5.5.1 Contention between Interrupt Interrupt-Disabling Instruction When instruction clears interrupt enable disable interrupt, interrupt disabled until after execution instruction completed. interrupt occurs while BCLR, MOV, other instruction being executed clear interrupt enable instant when execution instruction ends interrupt still enabled, interrupt exception handling carried out. higher-priority interrupt also requested, however, interrupt exception handling higher-priority interrupt carried out, lower-priority interrupt ignored. This also applies clearing interrupt flag. Figure shows example which IMIEA cleared ITU.
TIER write cycle Internal address Internal write signal IMIEA
IMIA exception handling
TIER address
IMIA IMFA interrupt signal
Figure Contention between Interrupt Interrupt-Disabling Instruction This type contention will occur interrupt masked when interrupt enable flag cleared
5.5.2 Instructions that Inhibit Interrupts LDC, ANDC, ORC, XORC instructions inhibit interrupts. When interrupt occurs, after determining interrupt priority, interrupt controller requests interrupt. currently executing these interrupt-inhibiting instructions, however, when instruction completed always continues executing next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution EEPMOV.B EEPMOV.W instructions differ their reaction interrupt requests. When EEPMOV.B instruction executing transfer, interrupts accepted until transfer completed, even NMI. When EEPMOV.W instruction executing transfer, interrupt requests other than accepted until transfer completed. requested, exception handling starts transfer cycle boundary. value saved stack address next instruction. Programs should coded follows allow interrupts during EEPMOV.W execution: EEPMOV.W MOV.W R4,R4
Section Controller
Overview
H8/3003 on-chip controller that divides address space into eight areas assign different specifications each. This enables different types memory connected easily. arbitration function controller controls operation controller (DMAC) refresh controller. controller also release external device. 6.1.1 Features Features controller listed below. Independent settings address areas 128-kbyte areas 1-Mbyte modes; 2-Mbyte areas 16-Mbyte modes. Chip select signals (CS0 CS7) output areas Areas designated 8-bit 16-bit access. Areas designated two-state three-state access.
Four wait modes Programmable wait mode, auto-wait mode, wait modes selected. Zero three wait states inserted automatically.
arbitration function built-in arbiter grants right CPU, DMAC, refresh controller, external master.
6.1.2 Block Diagram Figure shows block diagram controller.
ABWCR Internal address ASTCR Area decoder WCER control circuit Internal signals mode control signal size control signal Access state control signal Wait request signal
WAIT
Wait-state controller Internal signals
request signal DMAC request signal Refresh controller request signal acknowledge signal DMAC acknowledge signal Refresh controller acknowledge signal
BRCR arbiter
BACK Legend ABWCR: ASTCR: WCER: WCR: BRCR: width control register Access state control register Wait state controller enable register Wait control register release control register BREQ
Figure Block Diagram Controller
Internal data
6.1.3 Input/Output Pins Table summarizes controller's input/output pins. Table Controller Pins
Name Chip select Address strobe Read High write Abbreviation Output Output Output Output Function Strobe signals selecting areas Strobe signal indicating valid address output address Strobe signal indicating reading from external address space Strobe signal indicating writing external address space, with valid data upper data (D15 Strobe signal indicating writing external address space, with valid data lower data Wait request signal access external threestate-access areas Request signal releasing external device Acknowledge signal indicating released external device
write
Output
Wait request acknowledge
WAIT BREQ BACK
Input Input Output
6.1.4 Register Configuration Table summarizes controller's registers. Table Controller Registers
Abbreviation ABWCR ASTCR WCER BRCR Initial Value Modes Modes H'FF H'FF H'F3 H'FF H'FE H'00 H'FF H'F3 H'FF H'FE
Address* H'FFEC H'FFED H'FFEE H'FFEF H'FFF3
Name width control register Access state control register Wait control register Wait state controller enable register release control register
Note: Lower bits address.
Register Descriptions
6.2.1 Width Control Register (ABWCR) ABWCR 8-bit readable/writable register that selects 8-bit 16-bit access each area.
Mode ABW7 Initial value Mode Read/Write ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Bits selecting width each area
When ABWCR contains H'FF (selecting 8-bit access areas), H8/3003 operates 8-bit mode: upper data (D15 valid, port input/output port. When least cleared ABWCR, H8/3003 operates 16-bit mode with 16-bit data (D15 D0). modes ABWCR initialized H'FF reset hardware standby mode. modes ABWCR initialized H'00 reset hardware standby mode. ABWCR initialized software standby mode. Bits 0-Area Width Control (ABW7 ABW0): These bits select 8-bit access 16-bit access corresponding address areas.
Bits ABW7 ABW0 Description Areas 16-bit access areas Areas 8-bit access areas
ABWCR specifies width external memory areas. width on-chip memory registers fixed does depend ABWCR settings.
6.2.2 Access State Control Register (ASTCR) ASTCR 8-bit readable/writable register that selects whether each area accessed states three states.
Initial value Read/Write AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Bits selecting number states access each area
ASTCR initialized H'FF reset hardware standby mode. initialized software standby mode. Bits 0-Area Access State Control (AST7 AST0): These bits select whether corresponding area accessed three states.
Bits AST7 AST0 Description Areas accessed states Areas accessed three states (Initial value)
ASTCR specifies number states which external areas accessed. On-chip memory registers accessed fixed number states that does depend ASTCR settings.
6.2.3 Wait Control Register (WCR) 8-bit readable/writable register that selects wait mode wait-state controller (WSC) specifies number wait states.
Initial value Read/Write WMS1 WMS2
Reserved bits
Wait count These bits select number wait states inserted Wait mode select These bits select wait mode
initialized H'F3 reset hardware standby mode. initialized software standby mode. Bits 4-Reserved: Read-only bits, always read Bits 2-Wait Mode Select (WMS1/0): These bits select wait mode.
WMS1 WMS0 Description Programmable wait mode wait states inserted wait-state controller wait mode auto-wait mode (Initial value)
Bits 0-Wait Count (WC1/0): These bits select number wait states inserted access external three-state-access areas.
Description wait states inserted wait-state controller state inserted states inserted states inserted (Initial value)
6.2.4 Wait State Control Enable Register (WCER) WCER 8-bit readable/writable register that enables disables wait-state control external three-state-access areas wait-state controller.
Initial value Read/Write WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0
Wait state controller enable These bits enable disable wait-state control
WCER initialized H'FF reset hardware standby mode. initialized software standby mode. Bits 0-Wait-State Control Enable (WCE7 WCE0): These bits enable disable wait-state control external three-state-access areas.
Bits WCE7 WCE0 Description Wait-state control disabled (pin wait mode Wait-state control enabled (Initial value)
6.2.5 Release Control Register (BRCR) BRCR 8-bit readable/writable register that enables disables release external device.
Initial value Read/Write Reserved bits BRLE
release enable Enables disables release external device
BRCR initialized H'FE reset hardware standby mode. initialized software standby mode. Bits 1-Reserved: Read-only bits, always read 0-Bus Release Enable (BRLE): Enables disables release external device.
BRLE Description cannot released external device; BREQ BACK used input/output pins released external device (Initial value)
Operation
6.3.1 Area Division external address space divided into areas Each area size kbytes 1-Mbyte modes, Mbytes 16-Mbyte modes. Figure shows general view memory map.
H'00000 Area (128 kbytes) H'1FFFF H'20000 Area (128 kbytes) H'3FFFF H'40000 Area (128 kbytes) H'5FFFF H'60000 Area (128 kbytes) H'7FFFF H'80000 Area (128 kbytes) H'9FFFF H'A0000 Area (128 kbytes) H'BFFFF H'C0000 Area (128 kbytes) H'DFFFF H'E0000 Area (128 kbytes) On-chip
H'000000 Area Mbytes) H'1FFFFF H'200000 Area Mbytes) H'3FFFFF H'400000 Area Mbytes) H'5FFFFF H'600000 Area Mbytes) H'7FFFFF H'800000 Area Mbytes) H'9FFFFF H'A00000 Area Mbytes) H'BFFFFF H'C00000 Area Mbytes) H'DFFFFF H'E00000 Area Mbytes) On-chip External address space*3 H'FFFFFF On-chip registers*1 16-Mbyte modes (modes
External address space*3 H'FFFFF On-chip registers 1-Mbyte modes (modes
Notes: on-chip on-chip registers have fixed width accessed fixed number states. When RAME cleared SYSCR, this area conforms specifications area 12-byte external address space conforms specifications area
Figure Access Area Modes
Chip select signals (CS0 CS7) output each area. specifications each area selected ABWCR, ASTCR, WCER, shown table 6-3. Table Specifications
ABWCR ASTCR WCER ABWn ASTn WCEn WMS1 WMS0 Note: Width Specifications Access States Wait Mode Disabled wait mode Programmable wait mode Disabled wait mode auto-wait mode Disabled wait mode Programmable wait mode Disabled wait mode auto-wait mode
6.3.2 Chip Select Signals each areas H8/3003 output chip select signal (CS0 CS7) that goes indicate when area selected. Figure shows output timing signal. Output signal enabled disabled data direction register (DDR) corresponding port. reset leaves output state pins input state. output chip select signals CS7, corresponding bits must details section Ports. When on-chip on-chip registers accessed, goes HWR, signals remain high. signals decoded from address signals. They used chip select signals SRAM other devices.
Address
External address area
Figure Output Timing
6.3.3 Data H8/3003 allows either 8-bit access 16-bit access designated each areas 8-bit-access area uses upper data (D15 D8). 16-bit-access area uses both upper data (D15 lower data
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