Multirange, +5V, 12-Bit with 2-Wire Serial Interface 12-Bit Resol

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Multirange, +5V, 12-Bit with 2-Wire Serial Interface 12-Bit Resol

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19-4773; 7/98
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
12-Bit Resolution, Linearity Single-Supply Operation I2C-Compatible, 2-Wire Serial Interface Four Software-Selectable Input Ranges MAX127: +10V, +5V, ±10V, MAX128: +VREF, +VREF/2, ±VREF, ±VREF/2 Analog Input Channels 8ksps Sampling Rate ±16.5V Overvoltage-Tolerant Input Multiplexer Internal 4.096V External Reference Power-Down Modes 24-Pin Narrow 28-Pin SSOP Packages
MAX127/MAX128
MAX127/MAX128 multirange, 12-bit data acquisition systems (DAS) that require only single supply operation, accept signals their analog inputs that span above power-supply rail below ground. These systems provide eight analog input channels that independently software programmable variety ranges: ±10V, ±5V, +10V, MAX127; ±VREF, ±VREF/2, +VREF, +VREF/2 MAX128. This range switching increases effective dynamic range bits provides flexibility interface 4-20mA, ±12V, ±15V-powered sensors directly single system. addition, these converters fault protected ±16.5V; fault condition channel will affect conversion result selected channel. Other features include 5MHz bandwidth track/hold, 8ksps throughput rate, option internal 4.096V external reference. MAX127/MAX128 feature 2-wire, I2C-compatible serial interface that allows communication among multiple devices using lines. hardware shutdown input (SHDN) softwareprogrammable power-down modes (standby full power-down) provided low-current shutdown between conversions. standby mode, referencebuffer remains active, eliminating start-up delays. MAX127/MAX128 available 24-pin space-saving 28-pin SSOP packages.
Typical Operating Circuit
0.1µF
Applications
Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments
ANALOG INPUTS
SHDN
MAX127 MAX128
REFADJ
AGND
Ordering Information
PART MAX127ACNG MAX127ACNG TEMP. RANGE +70°C +70°C PIN-PACKAGE Narrow Plastic Narrow Plastic (LSB) ±1/2
4.7µF
0.01µF
DGND
Ordering Information continued data sheet. Configurations appear data sheet.
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 408-737-7600 ext. 3468.
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
ABSOLUTE MAXIMUM RATINGS
AGND.-0.3V AGND DGND.-0.3V +0.3V CH0-CH7 AGND ±16.5V AGND.-0.3V (VDD 0.3V) REFADJ AGND.-0.3V (VDD 0.3V) DGND.-0.3V (VDD 0.3V) SHDN, SCL, DGND .-0.3V Current into .50mA Continuous Power Dissipation +70°C) 24-Pin Narrow (derate 13.33mW/°C above +70°C).1067mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) .762mW Operating Temperature Ranges MAX127_ _/MAX128_ _.0°C +70°C MAX127_ _/MAX128_ .-40°C +85°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF REF; external clock, fCLK 400kHz; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note Bipolar Gain Tempco (Note Unipolar Bipolar MAX127A/MAX128A MAX127B/MAX128B MAX127A/MAX128A MAX127B/MAX128B MAX127A/MAX128A MAX127B/MAX128B MAX127A/MAX128A MAX127B/MAX128B ±0.1 ±0.3 ppm/°C MAX127A/MAX128A MAX127B/MAX128B ±1/2 Bits SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (800Hz sine-wave input, ±10Vp-p (MAX127) ±4.096Vp-p (MAX128), fSAMPLE 8ksps) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter SINAD SFDR 4kHz, (Note ±16.5V harmonic
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 400kHz; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ANALOG INPUT Track/Hold Acquisition Time ±10V ±VREF range Small-Signal Bandwidth -3dB rolloff ±VREF/2 range VREF range VREF/2 range MAX127 Unipolar, Table MAX128 Input Voltage Range MAX127 Bipolar, Table MAX128 MAX127 MAX128 Input Current Bipolar MAX128 Input Resistance Input Capacitance INTERNAL REFERENCE REFOUT Voltage REFOUT Tempco Output Short-Circuit Current Load Regulation (Note Capacitive Bypass REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain Figure 0.5mA output current 2.465 2.500 ±1.5 1.638 2.535 VREF VREF +25°C MAX127_C/MAX128_C MAX127_E/MAX128_E 4.076 4.096 4.116 ppm/°C Unipolar Bipolar (Note MAX127 ±10V range range ±VREF range ±VREF/2 range range range -VREF -VREF/2 -1200 -600 -1200 -600 1.25 VREF VREF/2 VREF VREF/2 SYMBOL CONDITIONS UNITS
MAX127/MAX128
Unipolar
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 400kHz; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER Input Voltage Range Input Current VREF 4.18V Normal, STANDBY power-down mode FULL power-down mode SYMBOL CONDITIONS 4.18 UNITS
REFERENCE INPUT (buffer disabled, reference input applied REF)
Input Resistance REFADJ Threshold Buffer Disable POWER REQUIREMENTS Supply Voltage
Normal STANDBY power-down mode FULL power-down mode
4.75 Normal mode, bipolar ranges Normal mode, unipolar ranges STANDBY power-down mode (Note FULL power-down mode External reference 4.096V Internal reference ±0.1 ±0.5
5.25 ±0.5
Supply Current
Power-Supply Rejection Ratio (Note TIMING External Clock Frequency Range Conversion Time Throughput Rate Bandgap Reference Start-Up Time Reference Buffer Settling Time
PSRR
fCLK tCONV
10.0 Power-up (Note 0.1mV, bypass capacitor fully discharged CREF 4.7µF CREF 33µF (Note ±0.1
ksps
DIGITAL INPUTS (SHDN, Input High Threshold Voltage Input Threshold Voltage Input Leakage Current Input Capacitance Input Hysteresis VHYS
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 400kHz; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER DIGITAL INPUTS (SDA, SCL) Input High Threshold Voltage Input Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS (SDA) Output Voltage Three-State Output Capacitance COUT ISINK ISINK (Note VHYS (Note 0.05 ±0.1 SYMBOL CONDITIONS UNITS
MAX127/MAX128
TIMING CHARACTERISTICS
(VDD +4.75V +5.25V; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETERS 2-WIRE FAST MODE 2-WIRE FAST MODE Clock Frequency Free Time Between STOP START Condition Hold Time (Repeated) START Condition Period Clock High Period Clock Set-Up Time Repeated START Condition Data Hold Time Data Setup Time Rise Time Both Signals (Receiving) Fall Time Both Signals (Receiving) Fall Time Both Signals (Transmitting) Set-Up Time STOP Condition Capacitive Load Each Line Pulse Width Spike Suppressed fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tSU,STO Total capacitance line Total capacitance line Total capacitance line SYMBOL CONDITIONS UNITS
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
TIMING CHARACTERISTICS (continued)
(VDD +4.75V +5.25V; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETERS 2-WIRE STANDARD MODE Clock Frequency Free Time Between STOP START Condition Hold Time (Repeated) START Condition Period Clock High Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time Rise Time Both Signals (Receiving) Fall Time Both Signals (Receiving) Fall Time Both Signals (Transmitting) Setup Time STOP Condition Capacitive Load Each Line Pulse Width Spike Suppressed Note Note Note Note Note Note Note Note fSCL tBUF tHD,STA tLOW tHIGH tSU, tHD, tSU, tSU, total capacitance line sink 1000 SYMBOL CONDITIONS UNITS
Accuracy specifications tested 5.0V. Performance power-supply tolerance limits guaranteed PowerSupply Rejection test. External reference: VREF 4.096V, offset error nulled, ideal last-code transition 3/2LSB. Ground "on" channel, sine wave applied "off" channels. Guaranteed design. tested. static external load during conversion specified accuracy. Tested using internal reference. PSRR measured full scale. Tested ±10V (MAX127) ±4.096V (MAX128) input ranges. subject production testing. Provided design guidance only.
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
Typical Operating Characteristics
(VDD +5V, external reference mode, VREF 4.096V; 4.7µF REF; external clock, fCLK 400kHz; +25°C; unless otherwise noted.)
STANDBY SUPPLY CURRENT TEMPERATURE
MAX127/8-02 MAX127/8-03
MAX127/MAX128
SUPPLY CURRENT SUPPLY VOLTAGE
max127/8-01
SUPPLY CURRENT TEMPERATURE
STANDBY SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA) SUPPLY CURRENT (mA)
INTERNAL REFERENCE
EXTERNAL REFERENCE
SUPPLY VOLTAGE
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
FULL POWER-DOWN SUPPLY CURRENT TEMPERATURE
MAX127/8-04
NORMALIZED REFERENCE VOLTAGE TEMPERATURE
MAX127/8-05
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING TEMPERATURE
BIPOLAR MODE
MAX127/8-06
FULL POWER-DOWN SUPPLY CURRENT (µA)
1.001 NORMALIZED REFERENCE VOLTAGE 1.000
0.35 0.30 0.25 0.20 0.15 0.10 0.05
EXTERNAL REFERENCE
0.999
INTERNAL REFERENCE
0.998
0.997
UNIPOLAR MODE
TEMPERATURE (°C)
0.996 TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING TEMPERATURE
MAX127/8-07
INTEGRAL NONLINEARITY DIGITAL CODE
MAX127/8-08
PLOT
800Hz fSAMPLE 8kHz
MAX127/8-09
UNIPOLAR MODE
0.15 INTEGRAL NONLINEARITY (LSB) 0.10 0.05 -0.05 -0.10 -0.15
AMPLITUDE (dB) -100 -110
BIPOLAR MODE
1638
2457
3276
4095
1600
2400
3200
4000
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (Hz)
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
Description
SSOP NAME N.C. DGND FUNCTION Supply. Bypass with 0.1µF capacitor AGND. Connect. internal connection. Digital Ground Serial Clock Input Address Select Inputs Open-Drain Serial Data I/O. Input data clocked rising edge SCL, output data clocked falling edge SCL. External pull-up resistor required. Shutdown Input. When low, device full power-down (FULLPD) mode. Connect high normal operation. Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with 0.01µF capacitor AGND. Connect when using external reference REF. Reference Buffer Output/ADC Reference Input. internal reference mode, reference buffer provides 4.096V nominal output, externally adjustable REFADJ. external reference mode, disable internal reference pulling REFADJ applying external reference REF.
13-20
15-21,
SHDN AGND CH0-CH7 REFADJ
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
SHDN
SERIAL INTERFACE LOGIC
CLOCK
ANALOG INPUT SIGNAL CONDITIONING
AGND DGND
CLOCK 12-BIT
2.5V REFERENCE REFADJ
1.638
MAX127 MAX128
Figure Block Diagram
Detailed Description
BIPOLAR
Converter Operation
MAX127/MAX128 multirange, fault-tolerant ADCs successive approximation internal track/hold (T/H) circuitry convert analog signal 12-bit digital output. Figure shows block diagram these devices.
5.12k
UNIPOLAR CHOLD HOLD TRACK TRACK
VOLTAGE REFERENCE
Analog-Input Track/Hold
circuitry enters tracking/acquisition mode falling edge sixth clock 8-bit input control word enters hold/conversion mode when master issues STOP condition. timing information, Start Conversion section.
HOLD
Input Range Protection
MAX127/MAX128 have software-selectable input ranges. Each analog input channel independently programmed four ranges setting appropriate control bits (RNG, BIP) control byte (Table MAX127 selectable input ranges extending ±10V (±VREF 2.441), while MAX128 selectable input ranges extending ±VREF. Note that when external reference applied REFADJ, voltage given VREF 1.638 VREFADJ (2.4 4.18). Figure shows equivalent input circuit. resistor network each analog input provides ±16.5V fault protection channels. This circuit limits current going into less than 1.2mA, whether channel This provides added layer protection when momentary overvoltages occur selected input channel, when negative signal applied input even though
BIPOLAR/UNIPOLAR SWITCH INPUT SWITCH SWITCH
12.5k (MAX127) 5.12k (MAX128) 8.67k (MAX127) (MAX128)
Figure Equivalent Input Circuit
device configured unipolar mode. Overvoltage protection active even device power-down mode
Digital Interface
MAX127/MAX128 feature 2-wire serial interface consisting pins. data serial clock input, controlled master device. A2-A0 used program MAX127/MAX128 different slave addresses. (The MAX127/MAX128 only work slaves.) lines (SDA SCL) must high when use. External pull-up resistors (1kor greater) required maintain compatibility. Table shows input control-byte format.
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
Table Control-Byte Format
(MSB) START (MSB) (LSB) SEL2 NAME START SEL2, SEL1, SEL0 PD1, SEL1 SEL0 (LSB)
DESCRIPTION logic received after acknowledge write (R/W defines beginning control byte. These three bits select desired "ON" channel (Table Selects full-scale input voltage range (Table Selects unipolar bipolar conversion mode (Table These bits select power-down modes (Table
Table Channel Selection
SEL2 SEL1 SEL0 CHANNEL
Table Power-Down Clock Selection
MODE Normal Operation (always Standby Power-Down Mode (STBYPD) Full Power-Down Mode (FULLPD)
Table Range Polarity Selection
INPUT RANGE MAX127 MAX128 VREF/2 VREF ±VREF/2 ±VREF -VREF/2 -VREF VREF/2 VREF VREF/2 VREF -VREF 1.2207 -VREF 2.4414 VREF 1.2207 VREF 2.4414 VREF 1.2207 VREF 2.4414 NEGATIVE FULL SCALE ZERO SCALE FULL SCALE
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
Slave Address
MAX127/MAX128 have 7-bit-long slave address. first four bits (MSBs) slave address have been factory programmed always 0101. logic state address input pins (A2-A0) determine three LSBs device address (Figure maximum eight MAX127/MAX128 devices therefore connected same time. A2-A0 connected DGND, they actively driven CMOS logic levels. eighth address byte determines whether master writing reading from MAX127/ MAX128 (R/W selects write condition. selects read condition).
Conversion Control
master signals beginning transmission with START condition (S), which high-to-low transition while high. When master finished communicating with slave, master issues STOP condition (P), which low-to-high transition while high (Figure then free another transmission. Figure shows timing diagram signals 2-wire interface. address-byte, control-byte, data-byte transmitted between START STOP conditions. state allowed change only while low, except START STOP conditions. Data transmitted 8-bit words. Nine clock cycles required transfer data MAX127/MAX128. (Figures 10).
MAX127/MAX128
SLAVE ADDRESS START CONDITION SLAVE ADDRESS BITS CORRESPOND LOGIC STATE ADDRESS INPUT PINS STOP CONDITION
Figure Address Byte
Figure START STOP Conditions
tSU, tLOW tHD, START CONDITION tHIGH REPEATED START CONDITION STOP CONDITION START CONDITION tHD, tSU, tHD, tSU, tBUF
Figure 2-Wire Serial-Interface Timing Diagram
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
Start Conversion (Write Cycle) conversion cycle begins with master issuing START condition followed seven address bits (Figure write (R/W Once eighth been received address matches, MAX127/MAX128 (the slave) issues acknowledge pulling clock cycle master then writes input control byte slave (Figure After this byte data, slave issues another acknowledge, pulling clock cycle. master ends write cycle issuing STOP condition (Figure When write (R/W acquisition starts soon (BIP) input control-byte been latched ends when STOP condition been issued. Conversion starts immediately after acquisition. MAX127/MAX128's internal conversion clock frequency 1.56MHz, resulting typical conversion time 7.7µs. Figure shows complete write cycle. Read Conversion (Read Cycle) Once conversion starts, master does need wait conversion before attempting read data from slave. Data access begins with master issuing START condition followed 7-bit address (Figure read (R/W Once eighth been received address matches, slave issues acknowledge pulling clock cycle followed first byte serial data (D11-D4, first). After first byte been issued slave, releases master issue acknowledge After receiving acknowledge, slave issues second byte (D3-D0 four zeros) followed acknowledge from master indicate that last data byte been received. Finally, master issues STOP condition (P), ending read cycle (Figure
MAX127/MAX128
SLAVE ADDRESS CONTROL-BYTE START CONDITION WRITE ACKNOWLEDGE
MASTER SLAVE SLAVE MASTER BITS
STOP CONDITION ACKNOWLEDGE
Figure Write Cycle
MASTER SLAVE SLAVE MASTER SLAVE ADDRESS DATA-BYTE DATA-BYTE ACKNOWLEDGE READ BITS
START CONDITION
STOP CONDITION ACKNOWLEDGE
Figure Read Cycle
START SEL2 START: ACK:
SEL1 SEL0
FIRST LOGIC RECEIVED AFTER ACKNOWLEDGE WRITE. ACKNOWLEDGE BIT. MAX127/MAX128 PULL DURING CLOCK PULSE.
Figure Command Byte
SLAVE ADDRESS BYTE STATE START CONDITION
CONTROL BYTE CONVERSION STOP CONDITION
ACQUISITION
Figure Complete 2-Wire Serial Write Transmission
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
SLAVE ADDRESS BYTE START CONDITION
DATA BYTE
DATA BYTE FILLED WITH ZEROS STOP CONDITION
Figure Complete 2-Wire Serial Read Transmission
MAX127/MAX128 ignore acknowledge NOTacknowledge conditions issued master during read cycle. device waits master read output data waits until STOP condition issued. Figure shows complete read cycle. unipolar input mode, output straight binary. bipolar input mode, output two's complement. output binary codes Transfer Function section.
External Reference input directly, disable internal buffer connecting REFADJ (Figure 11b). Using REFADJ input eliminates need buffer reference externally. When reference applied REFADJ, bypass REFADJ with 0.01µF capacitor AGND (Figure 11c).
REFADJ, input impedance minimum currents. During conversions, external reference must able drive 400µA load, must have output impedance less. reference higher input impedance noisy, bypass with 4.7µF capacitor AGND close chip possible. With external reference voltage less than 4.096V less than 2.5V REFADJ, increase noise value (full-scale voltage/4096) results performance degradation loss effective bits.
Applications Information
Power-On Reset
MAX127/MAX128 power normal operating mode, waiting START condition followed appropriate slave address. contents input output data registers cleared power-up.
Internal External Reference
MAX127/MAX128 operate with either internal external reference (Figures 11a-11c). external reference connected either REFADJ. REFADJ internal buffer gain trimmed 1.6384 provide 4.096V from 2.5V reference.
Power-Down Mode
save power, converter into low-current shutdown mode between conversions. programmable power-down modes available, addition hardware shutdown. Select STBYPD FULLPD programming input control byte (Table When software power-down asserted, becomes effective only after conversion. powerdown modes, interface remains active conversion results read. Input overvoltage protection active power-down modes.
Internal Reference internally trimmed 2.50V reference amplified through REFADJ buffer provide 4.096V REF. Bypass with 4.7µF capacitor AGND bypass REFADJ with 0.01µF capacitor AGND (Figure 11a). internal reference voltage adjustable ±1.5% (±65 LSBs) with reference-adjust circuit Figure
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
CREF 4.7µF 100k REFADJ 0.01µF 0.01µF
MAX127 MAX128
1.638
510k REFADJ
MAX127 MAX128
2.5V
Figure 11a. Internal Reference
Figure Reference-Adjust Circuit
4.096V CREF 4.7µF
MAX127 MAX128
1.638 REFADJ
power-up from software initiated power-down, START condition followed correct slave address must received (with MAX127/MAX128 power-up after receiving next bit. hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown asserted, becomes effective immediately conversion progress aborted.
Choosing Power-Down Modes
bandgap reference reference buffer remain active STBYPD mode, maintaining voltage 4.7µF capacitor REF. This "DC" state that does degrade after standby power-down duration. FULLPD mode, only bandgap reference active. Connect 33µF capacitor between AGND maintain reference voltage between conversions reduce transients when buffer enabled disabled. Throughput rates down 1ksps achieved without allotting extra acquisition time reference recovery prior conversion. This allows conversion begin immediately after power-down ends. discharge capacitor during FULLPD exceeds desired limits accuracy (less than fraction LSB), STBYPD power-down cycle prior starting conversions. Take into account that reference buffer recharges bypass capacitor 80mV/ms slew rate, 50µs settling time.
2.5V
Figure 11b. External Reference, Reference
MAX127 MAX128
1.638 REFADJ
CREF 4.7µF
2.5V 0.01µF
2.5V
Auto-Shutdown Selecting STBYPD every conversion automatically shuts MAX127/MAX128 down after each conversion without requiring start-up time next conversion.
Figure 11c. External Reference, Reference REFADJ
Multirange, +5V, 12-Bit with 2-Wire Serial Interface
Transfer Function
Output data coding MAX127/MAX128 binary unipolar mode with 1LSB (FS/4096) two's complement binary bipolar mode with 1LSB 4096]. Code transitions occur halfway between successive-integer values. Figures show input/output (I/O) transfer functions unipolar bipolar operations, respectively. full-scale (FS) values, refer Table
OUTPUT CODE FULL-SCALE TRANSITION 4096
Layout, Grounding, Bypassing
Careful printed circuit board layout essential best system performance. best performance, ground plane. reduce crosstalk noise injection, keep analog digital signals separate. Connect analog grounds DGND star configuration AGND. noise-free operation, ensure ground return from AGND supply ground impedance short possible. Connect logic grounds directly supply ground. Bypass with 0.1µF 4.7µF capacitors AGND minimize highand low-frequency fluctuations. supply excessively noisy, connect resistor between supply VDD, shown Figure
MAX127/MAX128
SUPPLY
4.7µF
INPUT VOLTAGE (LSB)
0.1µF AGND DGND DGND
MAX127 MAX128
DIGITAL CIRCUITRY
Figure 13a. Unipolar Transfer Function
OUTPUT CODE 011. 011.
OPTIONAL CONNECT AGND DGND WITH GROUND PLANE SHORT TRACE.
4096
Figure Power-Supply Grounding Connection
000. 000. 111.
100. 100. 100. INPUT VOLTAGE (LSB)
Figure 13b. Bipolar Transfer Function
Multirange, +5V, 12-Bit with 2-Wire Serial Interface MAX127/MAX128
Ordering Information (continued)
PART MAX127ACAI MAX127BCAI TEMP. RANGE +70°C +70°C PIN-PACKAGE SSOP SSOP Narrow Plastic Narrow Plastic SSOP SSOP Narrow Plastic Narrow Plastic SSOP SSOP Narrow Plastic Narrow Plastic SSOP SSOP (LSB) ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2
Chip Information
TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED AGND
MAX127AENG -40°C +85°C MAX127BENG -40°C +85°C MAX127AEAI MAX127BEAI MAX128ACNG MAX128BCNG MAX128ACAI MAX128BCAI -40°C +85°C -40°C +85°C +70°C +70°C +70°C +70°C
MAX128AENG -40°C +85°C MAX128BENG -40°C +85°C MAX128AEAI MAX128BEAI -40°C +85°C -40°C +85°C
Configurations
VIEW
DGND N.C. N.C. N.C. N.C. SHDN AGND N.C. REFADJ N.C. N.C. N.C. DGND N.C. SHDN AGND N.C. N.C. REFADJ
MAX127 MAX128
N.C.
MAX127 MAX128
SSOP
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Multirange, +5V, 12-Bit with 2-Wire Serial Interface 12-Bit Resol

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