Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MA

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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MA

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19-1399; 10/98
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
MAX1108/MAX1109 low-power, 8-bit, dual-channel, analog-to-digital converters (ADCs) feature internal track/hold (T/H) voltage reference, clock, serial interface. MAX1108 specified from +2.7V +3.6V consumes only 105µA. MAX1109 specified from +4.5V +5.5V consumes only 130µA. analog inputs software configurable, allowing unipolar/bipolar single-ended/differential operation; battery monitoring capability also included. full-scale analog input range determined internal reference +2.048V (MAX1108) +4.096V (MAX1109), externally applied reference ranging from VDD. MAX1108/MAX1109 also feature software power-down mode that reduces power consumption 0.5µA when device use. 4-wire serial interface directly connects SPITM, QSPITM, MICROWIREdevices without external logic. Conversions 50ksps performed using either internal clock external serial-interface clock. MAX1108 MAX1109 available 10-pin µMAX package with footprint that just 8-pin plastic DIP.
Features
Single Supply: +2.7V +3.6V (MAX1108) +4.5V +5.5V (MAX1109) Power: 105µA 50ksps 0.5µA Power-Down Mode Software-Configurable Unipolar Bipolar Inputs Input Voltage Range: Internal Track/Hold Internal Reference: +2.048V (MAX1108) +4.096V (MAX1109) Reference Input Range: SPI/QSPI/MICROWIRE-Compatible Serial Interface Monitoring Mode Small 10-Pin µMAX Package
MAX1108/MAX1109
Ordering Information
PART MAX1108CUB MAX1108EUB MAX1109CUB MAX1109EUB TEMP. RANGE +70°C -40°C +85°C +70°C -40°C +85°C PIN-PACKAGE µMAX µMAX µMAX µMAX
Applications
Portable Data Logging Hand-Held Measurement Devices Medical Instruments System Diagnostics Solar-Powered Remote Systems 4-20mA-Powered Remote Systems Receive-Signal Strength Indicators
Functional Diagram
SCLK INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER
Configuration
DOUT
VIEW
SCLK DOUT
MAX1108 MAX1109
CONTROL LOGIC ANALOG INPUT INTERNAL REFERENCE
INTERNAL OSCILLATOR
MAX1108 MAX1109
CHARGE REDISTRIBUTION
µMAX
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ABSOLUTE MAXIMUM RATINGS
.-0.3V CH0, CH1, COM, REF, DOUT .-0.3V (VDD 0.3V) DIN, SCLK, .-0.3V Continuous Power Dissipation +70°C) 10-pin µMAX (derate 5.6mW/°C above +70°C) .444mW Operating Temperature Ranges MAX110_CUB .0°C +70°C MAX110_EUB .-40°C +85°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS-MAX1108
(VDD +2.7V +3.6V; unipolar input mode; GND, fSCLK 500kHz, external clock mode (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +2.048V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching Sampling Accuracy DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 50ksps, 500kHz external clock) Signal-to-Noise Plus Distortion Total Harmonic Distortion harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Unipolar input, VCOM Input Voltage Range (Note VCH_ Bipolar input, VCOM VCH1 VREF referenced On/off-leakage current, VCOM ±0.01 VREF ±VREF SINAD SFDR BW-3dB -3dB rolloff +25°C TMIN TMAX ±0.5 ±0.1 ±0.8 2.7V 3.6V 5.5V (Note missing codes over temperature 2.7V 3.6V 5.5V (Note ±0.2 ±0.5 ±0.15 ±0.2 ±0.5 bits ppm/°C SYMBOL CONDITIONS UNITS
Multiplexer Leakage Current Input Capacitance
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS-MAX1108 (continued)
(VDD +2.7V +3.6V; unipolar input mode; GND, fSCLK 500kHz, external clock mode (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +2.048V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER TRACK/HOLD Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage Short-Circuit Current Tempco Load Regulation Capacitive Bypass EXTERNAL REFERENCE Input Voltage Range Input Current POWER REQUIREMENTS Supply Voltage 2.7V 3.6V, 10pF Supply Current (Notes 5.5V, 10pF Internal reference External reference Internal reference External reference ±0.4 +2.048V REF, full scale, 500kHz external clock 0.05 0.5mA (Note VREF IREFSC (Note 1.968 2.048 2.128 ppm/°C data transfer only tCONV tACQ Internal clock External clock, 500kHz, sclks/conv External clock, 2MHz SYMBOL CONDITIONS UNITS
MAX1108/MAX1109
Power down, 2.7V 3.6V Power-Supply Rejection (Note Full-scale input, 2.7V 3.6V 3.6V 3.6V DIGITAL INPUTS (DIN, SCLK, Threshold Voltage High Threshold Voltage Input Hysteresis Input Current High Input Current Input Capacitance VHYST
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ELECTRICAL CHARACTERISTICS-MAX1108 (continued)
(VDD +2.7V +3.6V; unipolar input mode; GND, fSCLK 500kHz, external clock mode (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +2.048V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER DIGITAL OUTPUT (DOUT) Output High Voltage Output Voltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time SCLK Setup Time SCLK Hold Time SCLK Fall Output Data Valid Fall Output Enable Rise Output Disable SCLK Rise Setup SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Wake-Up Time Wake-Up Time COUT tACQ tCSS tCSH tWAKE External reference Internal reference (Note Figure CLOAD 100pF Figure CLOAD 100pF Figure CLOAD 100pF ISOURCE 0.5mA ISINK ISINK 16mA ±0.01 SYMBOL CONDITIONS UNITS
TIMING CHARACTERISTICS (Figures
ELECTRICAL CHARACTERISTICS-MAX1109
(VDD +4.5V +5.5V; unipolar input mode; GND, fSCLK 500kHz, external clock (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +4.096V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching Sampling Accuracy +25°C TMIN TMAX ±0.5 ±0.1 ±0.8 4.5V 5.5V missing codes over temperature 4.5V 5.5V ±0.2 ±0.15 ±0.5 bits ppm/°C SYMBOL CONDITIONS UNITS
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS-MAX1109 (continued)
(VDD +4.5V +5.5V; unipolar input mode; GND, fSCLK 500kHz, external clock (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +4.096V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER Signal-to-Noise Plus Distortion Total Harmonic Distortion harmonic) Spurious Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Unipolar input, VCOM Input Voltage Range (Note VCH_ Bipolar input, VCOM VCH1 VREF referenced On/off-leakage current, Internal clock External clock, 500kHz, sclks/conv External clock, 2MHz data transfer only VREF IREFSC 0.5mA (Note +4.096V REF, full scale, 500kHz external clock 0.05 3.936 4.096 4.256 ±0.01 VREF ±VREF SYMBOL SINAD SFDR BW-3dB -3dB rolloff CONDITIONS UNITS DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
MAX1108/MAX1109
Multiplexer Leakage Current Input Capacitance TRACK/HOLD Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage Short-Circuit Current Tempco Load Regulation Capacitive Bypass EXTERNAL REFERENCE Input Voltage Range Input Current tCONV tACQ
ppm/°C
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ELECTRICAL CHARACTERISTICS-MAX1109 (continued)
(VDD +4.5V +5.5V; unipolar input mode; GND, fSCLK 500kHz, external clock (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +4.096V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER POWER REQUIREMENTS Supply Voltage 4.5V 5.5V, 10pF, full-scale input Internal reference External reference ±0.4 SYMBOL CONDITIONS UNITS
Supply Current (Notes
Power down, 4.5V 5.5V Power-Supply Rejection (Note External reference +4.096V, full-scale input, 4.5V 5.5V
DIGITAL INPUTS (DIN, SCLK, Threshold Voltage High Threshold Voltage Input Hysteresis Input Current High Input Current Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Voltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time SCLK Setup Time SCLK Hold Time SCLK Fall Output Data Valid Fall Output Enable Rise Output Disable COUT tACQ Figure CLOAD 100pF Figure CLOAD 100pF Figure CLOAD 100pF ISOURCE 0.5mA ISINK ISINK 16mA ±0.01 VHYST
TIMING CHARACTERISTICS (Figures
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS-MAX1109 (continued)
(VDD +4.5V +5.5V; unipolar input mode; GND, fSCLK 500kHz, external clock (50% duty cycle); clocks/conversion cycle (50ksps); capacitor REF, external +4.096V reference REF; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER SCLK Rise Setup SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Wake-Up Time SYMBOL tCSS tCSH tWAKE External reference Internal reference (Note CONDITIONS UNITS
MAX1108/MAX1109
Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Typical Operating Characteristics. Note VREF +2.048V (MAX1108), VREF +4.096V (MAX1109), offset nulled. Note Common-mode range (CH0, CH1, COM) VDD. Note Conversion time defined number clock cycles times clock period; clock duty cycle (Figures Note supplies typically 2.5mA under normal operating conditions. Note External load should change during conversion specified accuracy. Note Power consumption with CMOS levels. Note Measured VFS(2.7V) VFS(3.6V) MAX1108, measured VFS(4.5V) VFS(5.5V) MAX1109. Note REF, internal reference settling 0.5LSB.
Typical Operating Characteristics
(VDD +3.0V (MAX1108), +5.0V (MAX1109); external conversion mode; fSCLK 500kHz; 50ksps; external reference; REF; +25°C; unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE
MAX1108/09-02
SUPPLY CURRENT SUPPLY VOLTAGE
MAX1108/09-01
SUPPLY CURRENT TEMPERATURE
SUPPLY CURRENT (µA) DOUT 10101010 CLOAD 10pF INTERNAL REFERENCE 0.50 0.45 SHUTDOWN CURRENT (µA) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05
SUPPLY CURRENT (µA)
CLOAD 47pF
CLOAD 10pF
DOUT 10101010 MAX1108 (2.7V 5.5V) MAX1109 (4.5V 5.5V) INTERNAL REFERENCE
SUPPLY VOLTAGE
TEMPERATURE (°C)
SUPPLY VOLTAGE
MAX1108/09-03
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Typical Operating Characteristics (continued)
(VDD +3.0V (MAX1108), +5.0V (MAX1109); external conversion mode; fSCLK 500kHz; 50ksps; external reference; REF; +25°C; unless otherwise noted.)
OFFSET ERROR TEMPERATURE
MAX1108/09-04 MAX1108/09-05
OFFSET ERROR SUPPLY VOLTAGE
OFFSET ERROR (LSB) -0.1 -0.2 -0.3 -0.4 -0.5 SUPPLY VOLTAGE OFFSET ERROR (LSB) -0.1 -0.2 -0.3 -0.4 -0.5
OFFSET ERROR REFERENCE VOLTAGE
0.15 OFFSET ERROR (LSB) 0.10 0.05 -0.05 -0.10 -0.15 -0.20
MAX1108/09-06
0.20
REFERENCE VOLTAGE
TEMPERATURE (°C)
GAIN ERROR SUPPLY VOLTAGE
MAX1108/09-07
GAIN ERROR TEMPERATURE
GAIN ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0
MAX1108/09-08
GAIN ERROR REFERENCE VOLTAGE
GAIN ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0
MAX1108/09-09
GAIN ERROR (LSB) -0.1 -0.2 -0.3 -0.4 -0.5
REFERENCE VOLTAGE
SUPPLY VOLTAGE
TEMPERATURE (°C)
INTEGRAL NONLINEARITY SUPPLY VOLTAGE
MAX1108/09-10
DIFFERENTIAL NONLINEARITY CODE
MAX1108/09-11
DIFFERENTIAL NONLINEARITY SUPPLY VOLTAGE
(LSB) -0.1 -0.2 -0.3 -0.4 -0.5
MAX1108/09-12
(LSB) -0.1 -0.2 -0.3 -0.4
(LSB)
-0.1 -0.2 -0.3 SUPPLY VOLTAGE
-0.5 DIGITAL CODE
SUPPLY VOLTAGE
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(VDD +3.0V (MAX1108), +5.0V (MAX1109); external conversion mode; fSCLK 500kHz; 50ksps; external reference; REF; +25°C; unless otherwise noted.)
INTEGRAL NONLINEARITY CODE
MAX1108/09-13
MAX1108/MAX1109
PLOT
MAX1108/09-14
CONVERSION TIME SUPPLY VOLTAGE
INTERNAL CONVERSION MODE 20.5 CONVERSION TIME(µs) 20.0 19.5 19.0 18.5 18.0
MAX1108/09-15
(LSB) -0.1 -0.2 -0.3 -0.4 -0.5
AMPLITUDE (dB) -100
fCH_ 9997Hz, 2Vp-p fSAMPLE 53.25kHz
21.0
DIGITAL CODE
FREQUENCY (kHz)
SUPPLY VOLTAGE
CONVERSION TIME TEMPERATURE
MAX1108/09-16
NORMALIZED REFERENCE VOLTAGE TEMPERATURE
MAX1108/09-17
CHANNEL-TO-CHANNEL CROSSTALK FREQUENCY
CROSSTALK (dB) VCH_OFF VREFp-p
MAX1108/09-18
CONVERSION TIME (µs) INTERNAL CONVERSION MODE
1.0010 1.0005 REFERENCE VOLTAGE 1.0000 0.9995 0.9990 0.9985 0.9980
-100 TEMPERATURE (°C) FREQUENCY (kHz)
TEMPERATURE (°C)
Description
NAME CH0, DOUT SCLK Positive Supply Voltage Sampling Analog Inputs Ground Reference voltage analog-to-digital conversion (internal external reference). Reference input external reference. Bypass internal reference with capacitor GND. Common reference analog inputs. Sets zero-code voltage single-ended mode. Must stable ±0.5LSB during conversion. Active-Low Chip Select. Data clocked into unless low. When high, DOUT high impedance. Serial Data Input. Data clocked rising edge SCLK. Serial Data Output. Data clocked falling edge SCLK. High impedance when high. Serial Clock Input. Clocks data serial interface. external clock mode, SCLK also sets conversion speed. FUNCTION
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
DOUT DOUT
DOUT
DOUT
DGND High-Z
CLOAD
CLOAD DGND High-Z
DGND High-Z
CLOAD
CLOAD DGND High-Z
Figure Load Circuits Enable Time
Figure Load Circuits Disable Time
_Detailed Description
MAX1108/MAX1109 analog-to-digital converters (ADCs) successive-approximation conversion technique input track/hold (T/H) circuitry convert analog signal 8-bit digital output. flexible serial interface provides easy interface microprocessors (µPs). external hold capacitors required. MAX1108/MAX1109 operating modes software-configurable: internal external reference, internal external conversion clock, single-ended unipolar pseudo-differential unipolar/bipolar conversion, power down (Table
ANALOG INPUTS 0.1µF
MAX1108 MAX1109
SCLK DOUT (SK) MOSI (SO) MISO (SI)
Analog Inputs
Track/Hold input architecture ADCs illustrated equivalent-input circuit Figure composed T/H, input multiplexer, input comparator, switched capacitor DAC, reference, autozero rail. analog-inputs configuration determined control-byte through serial interface shown Table (see Modes Operation section Table eight modes operation include single-ended, pseudo-differential, unipolar/bipolar, monitoring mode. During acquisition conversion, only switches Figure closed time. enters tracking mode falling clock edge after (SEL0) control byte been shifted enters hold mode falling edge after (I/EREF) control byte been shifted example, chosen (SEL2 SEL1 SEL0 conversion, defined sampled input (SI), defined reference input (RI). During acquisition mode, switch switch closed, charging
Figure Typical Operating Circuit
CAPACITIVE CHOLD 18pF AUTOZERO RAIL HOLD 6.5k TRACK COMPARATOR
Figure Equivalent Input Circuit
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
holding capacitor CHOLD through RIN. acquisition switch opens CHOLD connected COM, retaining charge CHOLD sample signal CH0, difference between converted signal. Once conversion complete, returns immediately tracking mode. This procedure holds different combinations summarized Table time available acquire input signal (tACQ) determined clock frequency, maximum clock frequency 2MHz. acquisition time also minimum time needed signal acquired. calculated tACQ 6(RS RIN)18pF where 6.5k, source impedance input signal, never less than 1µs. Note that source impedances below 2.7k significantly affect performance maximum clock speed. input-source impedance higher than clock speed must reduced accordingly. input configuration selection also determines unipolar bipolar conversion mode. commonmode input range CH0, CH1, +VDD. unipolar mode, full scale achieved when VREF; bipolar mode, full scale achieved when VREF unipolar mode, must higher than bipolar mode, span above below provided that within common-mode range.
MAX1108/MAX1109
Conversion Process comparator negative input connected autozero rail. Since device requires only single supply, ZERO node input comparator equals VDD/2. capacitive restores node ZERO have difference comparator inputs within limits 8-bit resolution. This action equivalent transferring charge 18pF(VIN+ VIN-) from CHOLD binary-weighted capacitive which, turn, forms digital representation analog-input signal. Input Voltage Range Internal protection diodes that clamp analog input AGND allow channel input pins (CH0, CH1, COM) swing from (AGND 0.3V) (VDD 0.3V) without damage. However, accurate conversions, inputs must exceed (VDD 50mV) less than (GND 50mV). analog input voltage "off" channel exceeds 50mV beyond supplies, current should limited maintain conversion accuracy "on" channel. MAX1108/MAX1109 input range from VDD; unipolar bipolar conversion available. unipolar mode, output code invalid (code zero) when negative input voltage negative differential input voltage) applied. reference input-voltage range from (VDD 50mV.) Input Bandwidth ADC's input tracking circuitry 1.5MHz smallsignal bandwidth, possible digitize highspeed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, anti-alias filtering recommended.
Pseudo-Differential Input MAX1108/MAX1109 input configuration pseudodifferential extent that only signal sampled input (SI) stored holding capacitor (CHOLD). reference input (RI) must remain stable within ±0.5LSB (±0.1LSB best results) relation during conversion. Sampled input reference input configuration determined bit6-bit4 (SEL2-SEL0) control byte (Table varying signal applied selected reference input, amplitude frequency need limited. following equations determine relationship between maximum signal amplitude frequency maintain ±0.5LSB accuracy: Assuming sinusoidal signal reference input
VRIsin(2ft) maximum voltage variation determined dvRI CONV VREF CONV
60Hz signal with amplitude 1.2V will generate ±0.5LSB error. This with 35µs conversion time (maximum tCONV internal conversion mode) reference voltage +4.096V. When reference voltage used connect 0.1µF capacitor minimize noise input.
Serial Interface
MAX1108/MAX1109 have 4-wire serial interface. DIN, SCLK inputs used control device, while three-state DOUT used access result conversion.
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
serial interface provides easy connection microcontrollers with SPI, QSPI MICROWIRE serial interfaces clock rates 2MHz. QSPI, CPOL CPHA control registers microcontroller. Figure shows MAX1108/MAX1109 common serial-interface connections. DOUT active when high impedance when high. DOUT does accept external voltages greater than VDD. external-clock mode, data clocked maximum clock rate 500kHz while conversion progress. internal-clock mode, data clocked 2MHz clock rate.
Digital Inputs logic levels MAX1108/MAX1109 digital input accept voltage levels from both systems, regardless supply voltages. Input data (control byte) clocked rising edge serial clock (SCLK). standard chipselect signal which enables communication with device. SCLK used clock data serial interface. external clock mode, SCLK also sets conversion speed. Digital Output Output data read rising edge SCLK DOUT, first (D7). unipolar input mode, output straight binary. bipolar input mode, output twos-complement (see Transfer Function section).
Modes Operation
MAX1108/MAX1109 feature single-ended pseudo-differential operation unipolar bipolar configuration. device programmed through input control-byte serial interface (Table Table shows analog-input configuration Table shows input-voltage ranges unipolar bipolar configuration.
Start Conversion
conversion started clocking control byte into DIN. With low, each rising edge SCLK clocks from into MAX1108/MAX1109's internal shift register. After falls, first arriving logic defines control byte. Until this first start arrives, number logic bits clocked into with effect. Table shows control-byte format. Using Typical Operating Circuit (Figure simplest software interface requires 8-bit transfers perform conversion (one 8-bit transfer configure ADC, 8-bit transfer clock 8-bit conversion result). Figure shows single-conversion timing diagram using external clock mode.
MISO MOSI
SCLK DOUT
MISO MOSI
MAX1108 MAX1109
Clock Modes
MAX1108/MAX1109 either external serial clock internal clock perform successiveapproximation conversion. both clock modes, external clock shifts data devices. control-byte (I/ECLK) programs clock mode. Figure shows timing characteristics common both modes.
SCLK DOUT
QSPI
MAX1108 MAX1109
SCLK DOUT
MAX1108 MAX1109
MICROWIRE
Figure Common Serial-Interface Connections
External Clock external clock mode, external clock only shifts data out, also drives analog-to-digital conversion steps. this mode clock frequency must between 50kHz 500kHz. Single-conversion timing using external clock begins with falling edge When this occurs, DOUT leaves high impedance state goes low. first clocked into SCLK after considered start bit. next seven clocks latch rest control byte. falling edge fourth clock, track mode enabled, falling edge sixth clock, acquisition complete conversion
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Table Control Byte Format
(MSB) START (MSB) SEL2 NAME START SEL2 SEL1 SEL0 I/ECLK I/EREF SEL1 SEL0 I/ECLK I/EREF REFSHDN (LSB) SHDN
DESCRIPTION first logic after goes defines beginning control byte. Selects mode operation (Table external clock, internal clock. driven internal oscillator, with SCLK signal. internal reference, external reference. Internal reference selects +2.048V (MAX1108) +4.096V (MAX1109), external reference applied pin. operational EREF reference shutdown. When using external reference, power consumption minimized powering down internal reference separately EREF REFSHDN must when SHDN operational, power down. full power down REFSHDN SHDN (See PowerDown Mode section.)
REFSHDN
(LSB)
SHDN
Table Conversion Configuration
SEL2 SEL1 SEL0 SAMPLED INPUT (SI) REFERENCE INPUT (RI) CONVERSION MODE Unipolar Unipolar Unipolar Unipolar Bipolar Bipolar Bipolar Unipolar
Table Full- Zero-Scale Voltages
UNIPOLAR MODE Zero Scale Reference Input (Table Full Scale VREF Negative Full Scale VREF BIPOLAR MODE Zero Scale Positive Full Scale VREF
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
initiated. successive-approximation decision made rising edge seventh SCLK. falling edge eighth SCLK, clocked DOUT pin; each next seven SCLK falling edges, remaining bits conversion clocked out. Zeros clocked DOUT after been clocked out, until disabled. Then DOUT becomes high impedance part ready another conversion (Figure conversion must complete 1ms, droop sample-and-hold capacitors degrade conversion results. internal clock mode serial-clock frequency less than 50kHz, serial-clock interruptions could cause conversion interval exceed 1ms.
Internal Clock Internal clock mode frees from burden running conversion clock. This allows conversion results read back processor's convenience, clock rate 2MHz. internal register stores data when conversion progress. falling edge fourth SCLK, track mode enabled, falling edge eighth SCLK, acquisition complete internal conversion initiated. internal 400kHz clock completes conversion 20µs typically (35µs max), which time conversion present DOUT pin. falling edge SCLK clocks remaining data this register time after conversion complete (Figure
SCLK
SEL2 SEL1 SEL0 I/ECLK I/EREF SHDN
SHDN
START
DOUT tACQ IDLE
STATE
tCONV
IDLE
Figure Single Conversion Timing, External Clock Mode
tCSH SCLK DOUT tCSS tCSH
Figure Detailed Serial-Interface Timing
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
does need held once conversion started. Pulling high prevents data from being clocked into MAX1108/MAX1109 three-states DOUT, does adversely affect internal clock-mode conversion already progress. this mode, data shifted MAX1108/MAX1109 clock rates 2MHz, provided that minimum acquisition time ACQ) kept above 1µs.
Quick Look
quickly evaluate MAX1108/MAX1109's analog performance, circuit Figure device requires control byte written before each conversion. Tying feeds control bytes FFH. turn, this triggers single-ended, unipolar conversions relation external clock mode without powering down between conversions. Apply external 50kHz 500kHz clock
MAX1108/MAX1109
SCLK
SEL2 SEL0 SEL1 I/EREF I/ECLK
DOUT
SHDN SHDN
START
STATE
IDLE
tACQ
tCONV IDLE 35µs
Figure Single Conversion Timing, Internal Clock Mode
0.1µF
VSUPPLY
OSCILLOSCOPE
DOUT* SCLK
MAX1108 MAX1109
ANALOG INPUT 0.01µF
SCLK
DOUT
500kHz OSCILLATOR
5µs/div
*CONVERSION RESULT 10101010
Figure Quick-Look Schematic
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
SCLK pin; varying analog input alters result conversion that clocked DOUT pin. total clock cycles required conversion. external clock mode, first high clocked into after (D5) conversion progress clocked onto DOUT pin. internal clock mode, first high clocked into after (D4) clocked onto DOUT pin. MAX1108/MAX1109 maximum speed clocks conversion. Figure shows serialinterface timing necessary perform conversion every SCLK cycles external clock mode. Many microcontrollers require that conversions occur multiples SCLK clocks; clocks conversion typically fastest that microcontroller drive MAX1108/MAX1109. Figure shows serial-interface timing necessary perform conversion every SCLK cycles external clock mode.
Data Framing
falling edge does start conversion. first logic high clocked into interpreted start defines first control byte. Acquisition starts falling edge fourth SCLK lasts SCLKs external clock mode four SCLKs internal clock mode. Conversion starts immediately after acquisition completed. start defined first high clocked into with time converter idle; e.g., after applied.
SCLK CONTROL BYTE CONTROL BYTE CONTROL BYTE
CONVERSION RESULT DOUT tACQ tCONV tACQ
CONVERSION RESULT tCONV tACQ tCONV
STATE
IDLE
Figure Continuous Conversion, External Clock Mode, Clocks/Conversion Timing
SCLK CONTROL BYTE CONVERSION RESULT DOUT CONTROL BYTE CONVERSION RESULT
Figure Continuous Conversion, External Clock Mode, Clocks/Conversion Timing
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
external clock mode, toggled before current conversion complete, current conversion terminated, next high clocked into recognized start bit. This useful extending acquisition time selecting conversion same channel with second control byte (doubleclocking mode), effectively extending acquisition SCLKs. This technique ideal analog input source high impedance, requires more than settle; also used allow device reference settle when using power downmodes (see Power-Down Modes section).
MAX1108/MAX1109
Table Power-Down Modes MAX1108/MAX1109
2-BIT CONTROL BYTE I/EREF REFSHDN SHDN Device Active/Internal Reference Active Device Active; Internal reference powered down after conversion, powered next start bit. Device Active/External Reference Mode Device internal reference powered down after conversion, powered next start bit. Device powered down after each conversion, powered next start bit. External Reference Mode. Reserved. use. OPERATING MODE
_Applications Information
Battery Monitoring Mode
This mode operation samples converts midsupply voltage, which internally generated. SEL2 SEL1 SEL0 control byte select this configuration. This allows user monitor condition battery providing VDD. reference voltage must larger than this mode operation work properly. From result conversion (CODE), determined follows: CODE VREF 128.
Don't care
Power-On Configuration
When power first applied, MAX1108/MAX1109's reference powered down SHDN enabled. device needs configured setting writing control byte. Conversion started within 20µs external reference used. When using internal reference, allow 12ms reference settle. This done first performing configuration conversion power reference then performing second conversion once reference settled. conversions should considered correct until reference voltage (internal external) stabilized.
Power-Down Modes
save power, place converter into low-current power-down mode between conversions. Minimum power consumption achieved programming REFSHDN SHDN input control byte (Table When software power-down asserted, becomes effective only after conversion. control byte contains REFSHDN then reference will turn conversion. SHDN then chip will power-down conversion this mode I/EREF REFSHDN should also zero). Table lists power-down modes MAX1108/ MAX1109.
first logical clocked into after falls powers MAX1108/MAX1109 (20µs required device power up). reference powered only internal reference selected during previous conversion. When reference powered after being disabled, consider settling time before using result conversion. Typically, 12ms required reference settle from discharge state; less time considered external capacitor discharged completely when exiting shutdown. power-down modes, interface remains active conversion results read. double clocking technique described Data Framing section allow more time reference settle before starting conversion after short power-down.
Voltage Reference
MAX1108/MAX1109 operate from single supply feature software-controlled internal reference +2.048V (MAX1108) +4.096V (MAX1109). device operate with either internal reference external reference applied pin. Power-Down Modes Modes Operation sections detailed instructions reference configuration. reference voltage determines full-scale range: unipolar mode, input range from VREF; bipolar mode, input range spans ±VREF with VREF
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
External Reference external reference, (I/EREF) (REFSHDN) control byte connect external reference (VREF between VDD) directly pin. input impedance extremely high, consisting leakage current only (typically 10nA). During conversion, reference must able deliver 20µA average load current have output impedance less conversion clock frequency. reference higher output impedance noisy, bypass close with 0.1µF capacitor. MAX1109 internal reference +4.096V. device with supply voltages below 4.5V, external reference mode required. With external reference voltage less than +2.048V (MAX1108) +4.096V (MAX1109) REF, increase ratio noise value 256) results performance degradation decreased dynamic range. Internal Reference internal reference, (I/EREF) (REFSHDN) control byte bypass with capacitor ground. internal reference powered down after conversion setting (REFSHDN) control byte When using internal reference, MAX1108 MAX1109 with supply voltage below 4.5V above 4.5V, respectively.
MAX1108/MAX1109
OUTPUT CODE 11111111 11111110 11111101
FULL-SCALE TRANSITION
VREF 1LSB VREF 00000011 00000010 00000001 00000000 (COM) INPUT VOLTAGE (LSB) 1LSB
Figure 12a. Unipolar Transfer Function
OUTPUT CODE 01111111 01111110 VREF -VREF VREF 1LSB
00000010 00000001 00000000 11111111 11111110 11111101
Transfer Function
Table shows full-scale voltage ranges unipolar bipolar modes. Figure depicts nominal, unipolar transfer function, Figure shows bipolar transfer function. zero scale determined input selection setting either COM, GND, CH1. Code transitions occur integer values. Output coding straight binary unipolar operation two's complement bipolar operation. With +2.048V reference, 1LSB (VREF 256).
10000001 10000000 INPUT VOLTAGE (LSB)
Layout, Grounding, Bypassing
best performance, printed circuit boards. Wirewrap boards recommended. Board layout should ensure that digital analog signal lines separated from each other. analog digital (especially clock) lines parallel another digital lines underneath package. Figure shows recommended system-ground connections. single-point analog ground (star-ground point) should established ground. Connect analog grounds star ground. digital-system ground should connected this point.
Figure 12b. Bipolar Transfer Function
ground return power supply star ground should impedance short possible noise-free operation. High-frequency noise power supply affect comparator ADC. Bypass supply star ground with 0.1µF capacitors close MAX1108/MAX1109. Minimize capacitor lead lengths best supply-noise rejection. power supply very noisy, resistor connected form lowpass filter.
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
Chip Information
SYSTEM POWER SUPPLIES
MAX1108/MAX1109
TRANSISTOR COUNT: 2373
+3V/+5V
0.1µF DGND
MAX1108 MAX1109
DIGITAL CIRCUITRY
Figure Power-Supply Connections
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Package Information
10LUMAXB.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MA

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