+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX

Datasheet Thumbnail

Top Searches for this datasheet

19-1387; 6/02
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX
MAX144/MAX145 low-power, 12-bit analog-todigital converters (ADCs) available 8-pin µMAX packages. Both devices operate with single +2.7V +5.25V supply feature 7.4µs successive-approximation ADC, automatic power-down, fast wake-up (2.5µs), on-chip clock, high-speed, 3-wire serial interface. Power consumption only 3.2mW (VDD +3.6V) maximum sampling rate 108ksps. slower throughput rates, automatic shutdown (0.2µA) further reduces power consumption. MAX144 provides 2-channel, single-ended operation accepts input signals from VREF. MAX145 accepts pseudo-differential inputs ranging from external clock accesses datathrough 3-wire serial interface, which SPITM, QSPITM, MICROWIRETM-compatible. Excellent dynamic performance power, combined with ease small package size, make these converters ideal battery-powered dataacquisition applications, other circuits with demanding power-consumption space requirements. pin-compatible 10-bit ADCs, MAX157 MAX159 data sheets.
Features
Single-Supply Operation (+2.7V +5.25V) Single-Ended Channels (MAX144) Pseudo-Differential Channel (MAX145) Power 0.9mA (108ksps, Supply) 100µA (10ksps, Supply) 10µA (1ksps, Supply) 0.2µA (Power-Down Mode) Internal Track/Hold 108ksps Sampling Rate SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Space-Saving 8-Pin µMAX Package Pin-Compatible 10-Bit Versions Available
MAX144/MAX145
Ordering Information
PART MAX144ACUA MAX144BCUA MAX144ACPA MAX144BCPA TEMP RANGE +70°C +70°C +70°C +70°C PIN-PACKAGE µMAX µMAX Plastic Plastic Dice* µMAX µMAX (LSB) ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5
Applications
Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process-Control Monitoring Instrumentation Test Equipment Medical Instruments System Supervision
MAX144BC/D +70°C MAX144AEUA -40°C +85°C MAX144BEUA -40°C +85°C
Configuration
VIEW
(CH+) (CH-) SCLK DOUT CS/SHDN
MAX144AEPA -40°C +85°C Plastic MAX144BEPA -40°C +85°C Plastic MAX144AMJA -55°C +125°C CERDIP** MAX144BMJA -55°C +125°C MAX145ACUA +70°C MAX145BCUA +70°C MAX145ACPA +70°C MAX145BCPA +70°C MAX145BC/D +70°C MAX145AEUA -40°C +85°C MAX145BEUA -40°C +85°C MAX145AEPA -40°C +85°C MAX145BEPA -40°C +85°C CERDIP** µMAX µMAX Plastic Plastic Dice* µMAX µMAX Plastic Plastic
MAX144 MAX145
MAX145 ONLY
µMAX/DIP
MAX145AMJA -55°C +125°C CERDIP** MAX145BMJA -55°C +125°C CERDIP** *Dice specified +25°C, parameters only. **Contact factory availability.
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
ABSOLUTE MAXIMUM RATINGS
.-0.3V CH0, (CH+, CH-) -0.3V (VDD 0.3V) -0.3V (VDD 0.3V) Digital Inputs GND. -0.3V DOUT GND. -0.3V (VDD 0.3V) DOUT Sink Current 25mA Continuous Power Dissipation +70°C) µMAX (derate 4.1mW/°C above +70°C) 330mW Plastic (derate 9.09mW/°C above +70°C) .727mW CERDIP (derate 8.00mW/°C above +70°C) 640mW Operating Temperature Ranges (TA) MAX144/MAX145_C_A .0°C +70°C MAX144/MAX145_E_A. .-40°C +85°C MAX144/MAX145_M_A -55°C +125°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX145, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching (Note ±0.8 ±0.05 ±0.05 MAX14_A MAX14_B missing codes over temperature ±0.5 ±0.75 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (fIN(sine-wave) 10kHz, 2.5Vp-p, 108ksps, fSCLK 2.17MHz, MAX145) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (including 5th-order harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Conversion Time (Note Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency fSCLK External clock mode Internal clock mode, data transfer only tCONV tACQ 2.17 External clock, fSCLK 2.17MHz, clocks/conversion cycle Internal clock SINAD SFDR 65kHz, 2.5Vp-p (Note -3dB rolloff 2.25
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX145, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ANALOG INPUTS Analog Input Voltage Range Multiplexer Leakage Current Input Capacitance EXTERNAL REFERENCE Input Voltage Range Input Current Input Resistance Shutdown Input Current DIGITAL INPUTS (CS/SHDN) OUTPUT (DOUT) 3.6V Input High Voltage 3.6V Input Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Voltage Output High Voltage Three-State Output Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Positive Supply Current Power-Supply Rejection Operating mode Shutdown, CS/SHDN 2.7V 5.25V, VREF 2.5V, full-scale input (Note ±0.15 5.25 COUT VHYS (Note ISINK ISINK 16mA ISOURCE 0.5mA CS/SHDN CS/SHDN (Note VREF (Note VREF 2.5V 0.01 50mV (Note On/off leakage current, ±0.01 VREF SYMBOL CONDITIONS UNITS
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
TIMING CHARACTERISTICS (Figure
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX145, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Wake-Up Time CS/SHDN Fall Output Enable CS/SHDN Rise Output Disable SCLK Fall Output Data Valid SCLK Clock Frequency SYMBOL tWAKE fSCLK (Note 100pF 100pF, Figure 100pF, Figure External clock Internal clock, SCLK data transfer only External clock SCLK Pulse Width High Internal clock, SCLK data transfer only (Note External clock SCLK Pulse Width SCLK CS/SHDN Setup CS/SHDN Pulse Width tSCLKS Internal clock, SCLK data transfer only (Note CONDITIONS 2.17 UNITS
Note Tested +2.7V. Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Offset nulled. Note "On" channel grounded; sine wave applied "off" channel (MAX144 only). Note Conversion time defined number clock cycles times clock period; clock duty cycle. Note common-mode range analog inputs from (MAX145 only). Note performance limited converter's noise floor, typically 300µVp-p. Note Guaranteed design. subject production testing. Note Measured VFS(2.7V) VFS(5.25V). Note SCLK must remain stable during this time.
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX
Typical Operating Characteristics
(VDD +3.0V, VREF 2.5V, 0.1µF REF, fSCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX145, +25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
MAX144/5-01
MAX144/MAX145
SUPPLY CURRENT TEMPERATURE
MAX144/5-02
SUPPLY CURRENT SAMPLING RATE
VREF 20pF CODE 101010100000
MAX144/5-03
1500
1300 SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VREF 50pF CODE 101010100000
1500 VREF 50pF CODE 101010100000
10,000
1000
1250
1100
1000
SUPPLY VOLTAGE
TEMPERATURE (°C)
100k SAMPLING RATE (sps)
SHUTDOWN CURRENT SUPPLY VOLTAGE
MAX144/5-04
SHUTDOWN CURRENT TEMPERATURE
MAX144/5-05
OFFSET ERROR SUPPLY VOLTAGE
MAX144/5-06
1000 VREF SHUTDOWN CURRENT (nA)
1000
VREF
SHUTDOWN CURRENT (nA)
OFFSET ERROR (LSB)
SUPPLY VOLTAGE
TEMPERATURE (°C)
SUPPLY VOLTAGE
OFFSET ERROR TEMPERATURE
MAX144/5-07
GAIN ERROR SUPPLY VOLTAGE
MAX144/5-08
GAIN ERROR TEMPERATURE
GAIN ERROR (LSB) -0.1 -0.2 -0.3 -0.4
MAX144/5-09
OFFSET ERROR (LSB) TEMPERATURE (°C)
GAIN ERROR (LSB) -0.1 -0.2 -0.3 -0.4
-0.5
-0.5
TEMPERATURE (°C)
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
Typical Operating Characteristics (continued)
(VDD +3.0V, VREF 2.5V, 0.1µF REF, fSCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX145, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY OUTPUT CODE
MAX144/5-10
INTEGRAL NONLINEARITY SUPPLY VOLTAGE
MAX144/5-11
INTEGRAL NONLINEARITY TEMPERATURE
MAX144/5-12
0.20 0.15 0.10 (LSB)
(LSB)
-0.05 -0.10 -0.15 -0.20 1024 2048 OUTPUT CODE 3072 4096
(LSB)
0.05
TEMPERATURE (°C)
PLOT
MAX144/5-13
AMPLITUDE (dB) -100 -120 -140
EFFECTIVE NUMBER BITS
+2.7V 10kHz fSAMPLE 108ksps
+2.7V 11.8
11.6
11.4
11.2
11.0 FREQUENCY (kHz)
FREQUENCY (kHz)
Description
NAME (CH+) (CH-) CS/SHDN DOUT SCLK Positive Supply Voltage, +2.7V +5.25V Analog Input: MAX144 single-ended (CH0); MAX145 differential (CH+) Analog Input: MAX144 single-ended (CH1); MAX145 differential (CH-) Analog Digital Ground External Reference Voltage Input. Sets analog voltage range. Bypass with 100nF capacitor close device. Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts device into shutdown with maximum current 5µA. Serial Data Output. Data changes state SCLK's falling edge. High impedance when CS/SHDN high. Serial Clock Input. DOUT changes falling edge SCLK. FUNCTION
MAX144/5-14
EFFECTIVE NUMBER BITS FREQUENCY
12.0
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
DOUT DOUT HIGH-Z V0H, V0H, HIGH-Z HIGH-Z V0L, V0L, HIGH-Z
Figure Load Circuits Enable Disable Time
_Detailed Description
MAX144/MAX145 analog-to-digital converters (ADCs) successive-approximation conversion (SAR) technique on-chip track-and-hold (T/H) structure convert analog signal serial 12-bit digital output data stream. This flexible serial interface provides easy interface microprocessors (µPs). Figure shows simplified functional diagram internal architecture both MAX144 channels, single-ended) MAX145 channel, pseudo-differential).
CS/SHDN SCLK INTERNAL CLOCK CONTROL LOGIC (CH+) (CH-) ANALOG INPUT CHANNEL) OUTPUT REGISTER DOUT
SCLK 12-BIT
MAX144 MAX145
Analog Inputs: Single-Ended (MAX144) Pseudo-Differential (MAX145)
sampling architecture ADC's analog comparator illustrated equivalent input circuit Figure single-ended mode (MAX144), both channels referred connected different signal sources. Following power-on reset, convert CH0. After been converted, will converted conversions will continue alternate between channels. Channel switching performed toggling CS/SHDN pin. Conversions performed same channel toggling CS/SHDN twice between conversions. only channel required, connected together; however, output data will still contain channel identification (before MSB). MAX145, input channels form single differential channel pair (CH+, CH-). This configuration pseudo-differential effect that only signal sampled. return side must remain stable within ±0.5LSB (±0.1LSB optimum results) with respect during conversion. accomplish this, connect 0.1µF capacitor from GND. During acquisition interval, channel selected positive input (IN+) charges capacitor CHOLD. acquisition interval spans from when CS/SHDN falls falling edge second clock cycle (external
MAX145
Figure Simplified Functional Diagram
12-BIT CAPACITIVE (CH+) (CH-) CHOLD 16pF ZERO CSWITCH TRACK HOLD
MAX144 MAX145
COMPARATOR
INPUT
SINGLE-ENDED MODE: CH0, IN+; INDIFFERENTIAL-ENDED MODE: IN+;
CONTROL LOGIC MAX145
Figure Analog Input Channel Structure
clock mode) from when CS/SHDN falls first falling edge SCLK (internal clock mode). acquisition interval, switch opens, retaining charge CHOLD sample signal IN+. conversion interval begins with input multiplexer switching CHOLD from positive input (IN+) negative input (IN-). This unbalances node ZERO comparator's positive input.
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
capacitive digital-to-analog converter (DAC) adjusts during remainder conversion cycle restore node ZERO within limits 12-bit resolution. This action equivalent transferring 16pF [(VIN+) (VIN-)] charge from CHOLD binary-weighted capacitive DAC, which turn forms digital representation analog input signal. Higher source impedances used 0.01µF capacitor connected individual analog inputs. Together with input impedance, this capacitor forms filter, limiting ADC's signal bandwidth.
Input Bandwidth
MAX144/MAX145 stage offers 2.25MHz small-signal 1MHz full-power bandwidth, which make possible parts digitizing highspeed transients measuring periodic signals with bandwidths exceeding ADCs sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, anti-alias filtering recommended. Most aliasing problems fixed easily with external resistor capacitor. However, precision required, usually best choose continuous switched-capacitor filter, such MAX7410/ MAX7414 (Figure Their Butterworth characteristic generally provides best compromise (with regard rolloff attenuation) filter configurations, easy design, provides maximally flat passband response.
Track/Hold (T/H)
ADC's stage enters tracking mode falling edge CS/SHDN. MAX144 (singleended inputs), connected converter samples positive ("+") input. MAX145 (pseudo-differential inputs), connects negative input ("-") difference [(VIN+) (VIN-)] sampled. conversion, positive input connects back CHOLD charges input signal. time required stage acquire input signal function fast input capacitance charged. input signal's source impedance high, acquisition time lengthens, more time must allowed between conversions. acquisition time, tACQ, maximum time device takes acquire signal, also minimum time required signal acquired. Calculate this with following equation: tACQ 9(RS RIN)CIN where source impedance input signal, (9k) input resistance, (16pF) input capacitance ADC. Source impedances below have significant impact performance MAX144/MAX145.
Analog Input Protection
Internal protection diodes, which clamp analog input GND, allow each input channel swing within 300mV 300mV without damage. However, accurate conversions, both inputs must exceed 50mV less than 50mV. off-channel analog input voltage exceeds supplies, limit input current 4mA.
SHDN
470**
0.1µF
EXTERNAL REFERENCE
15kHz
MAX7410 MAX7414
MAX144
0.01µF** SCLK CS/SHDN 1.5MHz OSCILLATOR µP/µC DOUT
0.01µF
**USED ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE
Figure Analog Input with Anti-Aliasing Filter Structure
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX
Selecting Clock Mode
start conversion process MAX144/ MAX145, pull CS/SHDN low. CS/SHDN's falling edge, part wakes internal enters track mode. addition, state SCLK CS/SHDN's falling edge selects internal (SCLK high) external (SCLK low) clock mode.
Internal Clock (fSCLK 100kHz fSCLK 2.17MHz) internal clock mode, MAX144/MAX145 from internal, laser-trimmed oscillator within 2MHz specified clock rate. This releases system microprocessor from running conversion clock allows conversion results read back processor's convenience, clock rate from 5MHz. Operating MAX144/MAX145 internal clock mode necessary serial interfaces operating with clock frequencies lower than 100kHz greater than 2.17MHz. Select internal clock mode (Figure holding SCLK high during high/low transition CS/SHDN. first SCLK falling edge samples data initiates conversion using integrated on-chip oscillator. After conversion, oscillator shuts DOUT goes high, signaling conversion (EOC). Data then read with SCLK.
External Clock (fSCLK 100kHz 2.17MHz) external clock mode (Figure selected transitioning CS/SHDN from high while SCLK low. external clock signal only shifts data out, also drives analog-to-digital conversion. input sampled conversion begins falling edge second clock pulse. Conversion must completed within 140µs prevent degradation conversion results caused droop capacitors. External clock mode provides best throughput clock frequencies between 100kHz 2.17MHz.
MAX144/MAX145
Output Data Format
Table illustrates 16-bit, serial data stream output format both MAX144 MAX145. first three bits always logic high (including internal clock mode), followed channel identification (CHID CH0, CHID CH1, CHID MAX145), then bits data MSB-first format. After last been read out, additional SCLK pulses will clock trailing zeros. DOUT transitions falling edge SCLK. output remains high-impedance when CS/SHDN high.
ACTIVE
POWER DOWN
ACTIVE
CS/SHDN SCLK HIGH-Z DOUT
tWAKE (tACQ)
tCONV
HIGH-Z
SAMPLING INSTANT
CHID
Figure Internal Clock Mode Timing
ACTIVE
POWER DOWN
ACTIVE SAMPLING INSTANT
ACTIVE
POWER DOWN
CS/SHDN SCLK HIGH-Z DOUT
tWAKE (tACQ)
HIGH-Z
CHID
Figure External Clock Mode Timing
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
Table Serial Output Data Stream Internal External Clock Mode
SCLK CYCLE DOUT (Internal Clock) DOUT (External Clock) CHID CHID
External Reference
external reference required both MAX144 MAX145. REF, input resistance minimum 18k. During conversion, reference must able deliver 250µA load current have output impedance less. 0.1µF bypass capacitor best performance. reference input structure allows voltage range 50mV, although noise levels will decrease effective resolution lower reference voltages.
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists only quantization noise. With input range equal full-scale range ADC, effective number bits calculated follows: ENOB (SINAD 1.76) 6.02
Total Harmonic Distortion (THD)
ratio first five harmonics input signal fundamental itself. This expressed where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Automatic Power-Down Mode
Whenever MAX144/MAX145 selected (CS/SHDN parts enter their shutdown mode. shutdown internal circuitry turns off, reducing supply current typically less than 0.2µA. With external reference stable within 1LSB, wake-up time 2.5µs. external reference stable within 1LSB, wake-up time must increased allow reference stabilize.
_Applications Information
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNR(MAX) (6.02 1.76)dB reality, there other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. Therefore, computed taking ratio signal noise which includes spectral components minus fundamental, first five harmonics, offset.
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Connection Standard Interfaces
MAX144/MAX145 interface fully compatible with SPI, QSPI, MICROWIRE standard serial interfaces. serial interface available, establish CPU's serial interface master that generates serial clock MAX144/MAX145. Select clock frequency from 100kHz 2.17MHz (external clock mode). general-purpose line pull CS/SHDN while SCLK low. Wait minimum wake-up time (tWAKE) specified before activating SCLK. Activate SCLK minimum clock cycles. serial data stream three leading ones, channel identification, digitized input signal begin first falling clock edge. DOUT transitions SCLK's falling edge available MSB-first format. Observe SCLK
Signal-to-Noise Plus Distortion (SINAD)
SINAD ratio fundamental input frequency's amplitude equivalent other output signals: SIGNALRMS SINAD(dB) (Noise Distortion)RMS
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
DOUT valid timing characteristic. Data should clocked into SCLK's rising edge. Pull CS/SHDN high after 16th falling clock edge. CS/SHDN remains low, trailing zeros will clocked after LSB. With CS/SHDN high, wait least 60ns (tCS) before starting conversion pulling CS/SHDN low. conversion aborted pulling CS/SHDN high before conversion ends; wait least 60ns before starting conversion. Data output 8-bit sequences continuously. bytes will contain result conversion padded with three leading ones channel identification before MSB. serial clock hasn't been idled after last CS/SHDN kept low, DOUT sends trailing zeros.
MICROWIRE Interface When using (Figure MICROWIRE (Figure interfaces, CPOL CPHA Conversion begins with falling edge CS/SHDN (Figure 8c). consecutive 8-bit readings necessary obtain entire 12-bit result from ADC. DOUT data transitions serial clock's falling edge clocked into SCLK's rising edge. first 8-bit data stream contains three leading ones, channel identi-
CS/SHDN
tSCLKS
SCLK
DOUT HIGH-Z
HIGH-Z
Figure Detailed Serial-Interface Timing Sequence
MISO
CS/SHDN SCLK DOUT MICROWIRE
CS/SHDN SCLK DOUT
MAX144 MAX145
MAX144 MAX145
Figure Connections
MICROWIRE Connections
BYTE READ SCLK CS/SHDN
BYTE READ
HIGH-Z DOUT* CHID SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH-Z
Figure SPI/MICROWIRE Interface Timing Sequence (CPOL CPHA
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
fication, first four data bits starting with MSB. second 8-bit data stream contains remaining bits, through
QSPI Interface Using high-speed QSPI interface with CPOL CPHA MAX144/MAX145 support maximum fSCLK 2.17MHz. QSPI circuit Figure programmed perform conversion each channels MAX144. Figure shows QSPI interface timing.
MISO QSPI
CS/SHDN SCLK DOUT
MAX144 MAX145
PIC16 with Module PIC17 Interface MAX144/MAX145 compatible with PIC16/ PIC17 controller (µC), using synchronous serial-port (SSP) module. establish communication, connect controller shown Figure configure PIC16/PIC17 system master initializing synchronous serialport control register (SSPCON) synchronous serialport status register (SSPSTAT) patterns shown Tables mode, PIC16/PIC17 allow bits data synchronously transmitted received simultaneously. consecutive 8-bit readings (Figure 10b) necessary obtain entire 12-bit result from ADC. DOUT data transitions serial clock's falling edge clocked into SCLK's rising edge. first 8-bit data stream contains three leading ones, channel identification, first four data bits starting with MSB. second 8-bit data stream contains remaining bits, through
Figure QSPI Connections
SCLK CS/SHDN
HIGH-Z DOUT CHID SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH-Z
Figure QSPI Interface Timing Sequence (CPOL CPHA
Table Detailed SSPCON Register Contents
CONTROL WCOL SSPOV SSPEN SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX144/MAX145 SETTINGS Synchronous Serial-Port Mode Select Bit. Sets master mode selects fCLK fOSC SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Receive Overflow Detect Synchronous Serial-Port Enable Bit. Disables serial port configures these pins port pins. Enables serial port configures SCK, pins serial port pins. Clock Polarity Select Bit. master mode selection.
Don't care
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX
Table Detailed SSPSTAT Register Contents
CONTROL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX144/MAX145 SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) Data Input Sample Phase. Input data sampled middle data output time. Clock Edge Select Bit. Data will transmitted rising edge serial clock. Data Address Stop Start Read/Write Information Update Address Buffer Full Status
MAX144/MAX145
Don't care
Layout, Grounding, Bypassing
best performance, printed circuit boards (PCBs). Wire-wrap configurations recommended, since layout should ensure proper separation analog digital traces. analog digital lines anti-parallel each other, don't digital signal paths underneath package. separate analog digital ground sections with only star-point (Figure connecting ground systems
(analog digital). lowest-noise operation, ensure ground return star ground's power supply impedance short possible. Route digital signals away from sensitive analog reference inputs. High-frequency noise power supply could influence proper operation ADC's fast comparator. Bypass star ground with network parallel capacitors (0.1µF 1µF) located close possible power supply MAX144/ MAX145. Minimize capacitor lead length best supply-noise rejection attenuation resistor (10) power supply extremely noisy.
SCLK DOUT CS/SHDN
MAX144 MAX145
PIC16/17
Figure 10a. Interface Connection PIC16/PIC17 Controller
BYTE READ SCLK CS/SHDN
BYTE READ
HIGH-Z DOUT* CHID SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH-Z
Figure 10b. Interface Timing with PIC16/PIC17 Master Mode (CKE SSPM3-SSPM0 0001)
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
POWER SUPPLIES
0.1µF DGND
MAX144 MAX145
OPTIONAL FILTER RESISTOR
DIGITAL CIRCUITRY
Figure Power-Supply Bypassing Grounding
Chip Information
TRANSISTOR COUNT: 2,058 SUBSTRATE CONNECTED
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
_Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
8LUMAXD.EPS
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX MAX144/MAX145
_Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
PDIPN.EPS

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs 8-Pin µMAX

Top Searches for this datasheet

Other recent searches