+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX

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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX

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19-1388; 11/98
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
MAX157/MAX159 low-power, 10-bit analog-to-digital converters (ADCs) available 8-pin µMAX packages. Both devices operate with single +2.7V +5.25V supply feature 7.4µs successive-approximation ADC, automatic power-down, fast wake-up (2.5µs), on-chip clock, high-speed, 3-wire serial interface. Power consumption only 3.2mW (VDD +3.6V) maximum sampling rate 108ksps. slower throughput rates, 0.2µA automatic shutdown further reduces power consumption. MAX157 provides 2-channel, single-ended operation accepts input signals from VREF. MAX159 accepts pseudo-differential inputs ranging from external clock accesses data through 3-wire serial interface, which SPITM, QSPITM, MICROWIREcompatible. Excellent dynamic performance power, combined with ease small package size, make these converters ideal battery-powered data acquisition applications, other circuits with demanding power-consumption space requirements. pin-compatible 12-bit upgrades, MAX144/MAX145 data sheet.
Features
Single-Supply Operation (+2.7V +5.25V) Single-Ended Channels (MAX157) Single Pseudo-Differential Channel (MAX159) Power 0.9mA 108ksps, +3V) 100µA 10ksps, +3V) 10µA 1ksps, +3V) <0.2µA (power-down mode) Internal Track/Hold 108ksps Sampling Rate SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Space-Saving 8-Pin µMAX Package Pin-Compatible 12-Bit Upgrades Available
MAX157/MAX159
Ordering Information
PART TEMP. RANGE +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PINPACKAGE µMAX µMAX Plastic Plastic µMAX µMAX Plastic Plastic CERDIP* CERDIP* µMAX µMAX Plastic Plastic µMAX µMAX Plastic Plastic CERDIP* CERDIP* (LSB) ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5
Applications
Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process-Control Monitoring Instrumentation Test Equipment Medical Instruments System Supervision
MAX157ACUA MAX157BCUA MAX157ACPA MAX157BCPA MAX157AEUA MAX157BEUA MAX157AEPA MAX157BEPA
Configuration
VIEW
(CH+) (CH-) SCLK DOUT CS/SHDN
MAX157AMJA -55°C +125°C MAX157BMJA -55°C +125°C MAX159ACUA +70°C MAX159BCUA +70°C MAX159ACPA +70°C MAX159BCPA +70°C MAX159AEUA -40°C +85°C MAX159BEUA -40°C +85°C MAX159AEPA MAX159BEPA MAX159AMJA MAX159BMJA -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C
MAX157 MAX159
µMAX/DIP
MAX159 ONLY.
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
*Contact factory availability.
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
ABSOLUTE MAXIMUM RATINGS
GND. .-0.3V CH0, (CH+, CH-) GND.-0.3V (VDD 0.3V) .-0.3V (VDD 0.3V) Digital Inputs .-0.3V DOUT GND.-0.3V (VDD 0.3V) DOUT Sink Current 25mA Continuous Power Dissipation +70°C) µMAX (derate 4.1mW/°C above +70°C) .330mW Plastic (derate 9.09mW/°C above +70°C) .727mW CERDIP (derate 8.00mW/°C above +70°C) .640mW Operating Temperature Ranges MAX157/MAX159_C_A .0°C +70°C MAX157/MAX159_E_A .-40°C +85°C MAX157/MAX159_MJA. -55°C +125°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX159, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching External reference, VREF 2.5V ±0.8 ±0.02 ±0.02 MAX15_A MAX15_B missing codes over temperature ±0.5 ±0.5 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (fIN (sine wave) 10kHz, 2.5Vp-p, 108ksps, external fSCLK 2.17MHz, MAX159) Signal-to-Noise Ratio plus Distortion Total Harmonic Distortion (including 5th-order harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD SFDR 65kHz, 2.5Vp-p (Note -3dB rolloff 2.25
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX159, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER CONVERSION RATE Conversion Time (Note Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUTS Analog Input Voltage Range (Note Multiplexer Leakage Current Input Capacitance EXTERNAL REFERENCE Input Voltage Range (Note Input Current Input Resistance Shutdown Input Current DIGITAL INPUTS (CS/SHDN, SCLK) DIGITAL OUTPUT (DOUT) 3.6V Input High Voltage 3.6V Input Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Voltage Output High Voltage Three-State Output Leakage Current Three-State Output Capacitance COUT VHYS (Note ISINK ISINK 16mA ISOURCE 0.5mA CS/SHDN CS/SHDN (Note VREF VREF 2.5V 50mV 0.01 On/off-leakage current, ±0.01 VREF fSCLK External clock mode Internal clock mode, data transfer only tCONV tACQ 2.17 External clock, fSCLK 2.17MHz, clock cycles conversion Internal clock SYMBOL CONDITIONS UNITS
MAX157/MAX159
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
ELECTRICAL CHARACTERISTICS (continued)
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX159, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER POWER REQUIREMENTS Positive Supply Voltage Positive Supply Current Positive Supply Current Power-Supply Rejection (Note Operating mode Shutdown, CS/SHDN 2.7V 5.25V, full-scale input +2.7 ±0.15 +5.25 SYMBOL CONDITIONS UNITS
TIMING CHARACTERISTICS (Figure
+2.7V +5.25V, 2.5V, 0.1µF capacitor REF, SCLK 2.17MHz, clocks/conversion cycle (108ksps), MAX159, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Wake-Up Time CS/SHDN Fall Output Enable CS/SHDN Rise Output Disable SCLK Fall Output Data Valid SCLK Clock Frequency SYMBOL tWAKE fSCLK 100pF (Figure 100pF (Figure 100pF External clock Internal clock, SCLK data transfer only External clock SCLK Pulse Width High Internal clock, SCLK data transfer only (Note External clock SCLK Pulse Width SCLK CS/SHDN Setup CS/SHDN Pulse Width tSCLKS Internal clock, SCLK data transfer only (Note CONDITIONS 2.17 UNITS
Note Tested +2.7V. Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Offset nulled. Note channel grounded; sine wave applied channel (MAX157 only). Note Conversion time defined number clock cycles times clock period; clock duty cycle. Note common-mode range analog inputs from (MAX159 only). Note performance limited converter's noise floor, typically 300µVp-p. Note Guaranteed design. subject production testing. Note Measured VFS(2.7V) VFS(5.25V).
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
Typical Operating Characteristics
(VDD +3.0V, VREF 2.5V, 0.1µF capacitor REF, fSCLK 2.17MHz, clocks/conversion cycle (108ksps); MAX159; +25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
MAX157/159 toc01
MAX157/MAX159
SUPPLY CURRENT TEMPERATURE
MAX157/159 toc02
SUPPLY CURRENT SAMPLING RATE
VREF CODE 1010101000 50pF
MAX157/159 toc03
1500 VREF 50pF CODE 1010101000
1500 VREF 50pF CODE 1010101000
10,000
1300 SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
1100
SUPPLY CURRENT (µA)
1250
1000
1000
TEMPERATURE (°C)
100k SAMPLING RATE (sps)
SHUTDOWN CURRENT SUPPLY VOLTAGE
VREF SHUTDOWN CURRENT (nA)
MAX157/159 toc04
SHUTDOWN CURRENT TEMPERATURE
VREF SHUTDOWN CURRENT (nA)
MAX157/159 toc05
1000
1000
TEMPERATURE (°C)
OFFSET ERROR SUPPLY VOLTAGE
MAX157/159 toc06
OFFSET ERROR TEMPERATURE
MAX157/159 toc07
0.20
0.20
OFFSET ERROR (LSB)
OFFSET ERROR (LSB)
0.15
0.15
0.10
0.10
0.05
0.05
TEMPERATURE (°C)
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
Typical Operating Characteristics (continued)
(VDD +3.0V, VREF 2.5V, 0.1µF capacitor REF, fSCLK 2.17MHz, clocks/conversion cycle (108ksps); MAX159; +25°C, unless otherwise noted.)
GAIN ERROR SUPPLY VOLTAGE
MAX157/159 toc08
GAIN ERROR TEMPERATURE
MAX157/159 toc09
INTEGRAL NONLINEARITY OUTPUT CODE
MAX157/8 toc10
0.03 0.02 0.01 (LSB)
GAIN ERROR (LSB)
GAIN ERROR (LSB)
-0.01
-0.1
-0.1 -0.02
-0.2
-0.2 TEMPERATURE (°C)
-0.03 OUTPUT CODE 1000
INTEGRAL NONLINEARITY SUPPLY VOLTAGE
MAX157/159 toc11
INTEGRAL NONLINEARITY TEMPERATURE
MAX157/159 toc12
0.20
0.20
0.15 (LSB)
0.15 (LSB)
0.10
0.10
0.05
0.05
TEMPERATURE (°C)
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
Description
NAME (CH+) (CH-) CS/SHDN DOUT SCLK Positive Supply Voltage, +2.7V +5.25V Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+). Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-). Analog Digital Ground External Reference Voltage Input. Sets analog voltage range. Bypass with 100nF capacitor close part. Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into shutdown with maximum current 5µA. Serial Data Output. Data changes state SCLK's falling edge. High impedance when CS/SHDN high. Serial Clock Input. DOUT changes falling edge SCLK. FUNCTION
MAX157/MAX159
DOUT DOUT HIGH-Z V0H, V0H, HIGH-Z HIGH-Z V0L, V0L, HIGH-Z
Figure Load Circuits Enable Disable Time
Detailed Description
MAX157/MAX159 analog-to-digital converters (ADCs) successive-approximation conversion (SAR) technique on-chip track/hold (T/H) structure convert analog signal serial, 10-bit digital output data stream. This flexible serial interface provides easy interface microprocessors (µPs). Figure shows simplified functional diagram internal architecture both MAX157 channels, single-ended) MAX159 channel, pseudo-differential).
same channel toggling CS/SHDN twice between conversions. only channel required, connected together; however output data will still contain channel identification (before MSB). MAX159, input channels form single differential channel pair (CH+, CH-). This configuration pseudo-differential effect that only signal sampled. return side must remain stable within ±0.5LSB (±0.1LSB optimum results) with respect during conversion. accomplish this, connect 0.1µF capacitor from GND. During acquisition interval, channel selected positive input (IN+) charges capacitor CHOLD. acquisition interval spans from when CS/SHDN falls falling edge second clock cycle (external clock mode) from when CS/SHDN falls first falling edge SCLK (internal clock mode). acquisition interval, switch opens, retaining charge CHOLD sample signal IN+. conversion interval begins with input multiplexer switching CHOLD from positive input (IN+) negative input (IN-). This unbalances node ZERO comparator's positive input.
Single-Ended (MAX157) PseudoDifferential (MAX159) Analog Inputs
sampling architecture ADC's analog comparator illustrated equivalent input circuit Figure single-ended mode (MAX157), both channels referred connected different signal sources. Following power-on reset, convert CH0. After been converted, will converted, conversions will continue alternate between channels. Channel switching performed toggling CS/SHDN pin. Conversions performed
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
capacitive digital-to-analog converter (DAC) adjusts during remainder conversion cycle restore node ZERO within limits 10-bit resolution. This action equivalent transferring 16pF [(VIN+) (VIN-)] charge from CHOLD binary-weighted capacitive DAC, which turn forms digital representation analog input signal. Higher source impedances used 0.01µF capacitor connected individual analog inputs. Together with input impedance, this capacitor forms filter, limiting ADC's signal bandwidth.
Input Bandwidth
MAX157/MAX159 stage offers both 2.25MHz small-signal 1MHz full-power bandwidth, which makes possible parts digitizing highspeed transients measuring periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, anti-alias filtering recommended. Most aliasing problems fixed easily with external resistor capacitor. However, precision required, usually best choose continuous switched-capacitor filter, such MAX7410/ MAX7414 (Figure Their Butterworth characteristic generally provides best compromise (with regard rolloff attenuation) filter configurations, easy design, provides maximally flat passband response.
Track/Hold
ADC's stage enters tracking mode falling edge CS/SHDN. MAX157 (singleended inputs), connected converter samples positive ("+") input. MAX159 (pseudo-differential inputs), connects negative input ("-"), difference [(VIN+) (VIN-)] sampled. conversion, positive input connects back CHOLD charges input signal. time required stage acquire input signal function fast input capacitance charged. input signal's source impedance high, acquisition time lengthens more time must allowed between conversions. acquisition time, tACQ, maximum time device takes acquire signal, also minimum time required signal acquired. Calculate this with following equation: tACQ 7(RS RIN)CIN where source impedance input signal, (9k) input resistance, (16pF) input capacitance ADC. Source impedances below have significant impact performance MAX157/MAX159.
Analog Input Protection
Internal protection diodes, which clamp analog input GND, allow each input channel swing within 300mV 300mV without damage. However, accurate conversions both inputs must exceed 50mV less than 50mV. off-channel analog input voltage exceeds supplies, limit input current 4mA.
CAPACITIVE CS/SHDN SCLK INTERNAL CLOCK CONTROL LOGIC (CH+) (CH-) MAX159 ANALOG INPUT CHANNEL) OUTPUT REGISTER DOUT (CH-) (CH+) CSWITCH SCLK 10+2 TRACK HOLD SINGLE-ENDED MODE: CHO, IN+; INDIFFERENTIAL MODE: IN+; INCONTROL LOGIC MAX159 INPUT COMPARATOR CHOLD 16pF ZERO
MAX157 MAX159
Figure MAX157/MAX159 Simplified Functional Diagram
Figure Analog Input Channel Structure
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
Selecting Clock Mode
start conversion process MAX157/ MAX159, pull CS/SHDN low. CS/SHDN's falling edge, part wakes internal enters track mode, conversion begins. addition, state SCLK CS/SHDN's falling edge selects internal (SCLK high) external (SCLK low) clock mode. SCLK high during high/low transition CS/SHDN. first SCLK falling edge samples data initiates conversion using integrated on-chip oscillator. After conversion, oscillator shuts DOUT goes high, signaling conversion (EOC). Data then read with SCLK.
MAX157/MAX159
Internal Clock (fSCLK 100kHz fSCLK 2.17MHz) internal clock mode, MAX157/MAX159 from internal, laser-trimmed oscillator within 2MHz specified clock rate. This releases system microprocessor from running conversion clock allows conversion results read back processor's convenience, clock rate from 5MHz. Operating MAX157/MAX159 internal clock mode necessary serial interfaces operating with clock frequencies lower than 100kHz greater than 2.17MHz. Select internal clock mode (Figure hold-
External Clock (fSCLK 100kHz 2.17MHz) External clock mode (Figure selected transitioning CS/SHDN from high while SCLK low. external clock signal only shifts data out, also drives analog-to-digital conversion. input sampled conversion begins falling edge second clock pulse. Conversion must completed within 140µs prevent degradation conversion results caused droop capacitors. External clock mode provides best throughput clock frequencies between 100kHz 2.17MHz.
SHDN
0.1µF
EXTERNAL REFERENCE
fCORNER 15kHz
MAX7410 MAX7414
MAX157
0.01µF DOUT
0.01µF
1.5MHz CLOCK
SCLK
CS/SHDN
µP/µC
Figure Analog Input with Anti-Aliasing Filter Structure
ACTIVE
POWER DOWN
ACTIVE tWAKE (tACQ) tCONV
CS/SHDN SCLK HIGH-Z
DOUT
HIGH-Z SAMPLING INSTANT
CHID
Figure Internal Clock Mode Timing
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
Output Data Format
Table illustrates 16-bit, serial data-stream output format both MAX157 MAX159. first three bits always logic high (including internal clock mode), followed channel identification (CHID CH0, CHID CH1, CHID MAX159), bits data first format, sub-LSB bits S0). After last been read out, additional SCLK pulses will clock trailing zeros. DOUT transitions falling edge SCLK. output remains high impedance when CS/SHDN high.
Automatic Power-Down Mode
Whenever MAX157/MAX159 selected (CS/SHDN VDD), parts enter their shutdown mode. shutdown internal circuitry turned off, which reduces supply current typically less than 0.2µA. With external reference stable within 1LSB, wake-up time 2.5µs. external reference stable within 1LSB, wake-up time must increased allow reference stabilize.
Applications Information
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNR(MAX) (6.02 1.76)dB reality, there other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
External Reference
external reference required both MAX157 MAX159. REF, input resistance minimum 18k. During conversion, reference must able deliver 250µA load current have output impedance less. 0.1µF bypass capacitor best performance. reference input structure allows voltage range (VDD 50mV) although noise levels will decrease effective resolution lower reference voltages.
ACTIVE
POWER DOWN
ACTIVE SAMPLING INSTANT tWAKE (tACQ)
CS/SHDN SCLK HIGH-Z DOUT HIGH-Z
CHID
Figure External Clock Mode Timing
CS/SHDN
tSCLKS
SCLK
DOUT HIGH-Z
HIGH-Z
Figure Detailed Serial-Interface Timing Sequence
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
Table Serial Output Data Stream Internal External Clock Mode
SCLK CYCLE DOUT (Internal Clock) DOUT (External Clock) CHID CHID
MAX157/MAX159
etc. Therefore, computed taking ratio signal noise (which includes spectral components minus fundamental), first five harmonics, offset.
serial clock MAX157/MAX159. Select clock frequency from 100kHz 2.17MHz (external clock mode). general-purpose line pull CS/SHDN while SCLK low. Wait minimum wake-up time (tWAKE) specified before activating SCLK. Activate SCLK minimum clock cycles. first falling clock edge will generate serial datastream three leading ones, followed channel identification, digitized input signal, sub-bits. DOUT transitions SCLK's falling edge available MSB-first format. Observe SCLK DOUT valid timing characteristic. Data should clocked into SCLK's rising edge. Pull CS/SHDN high after 16th falling clock edge. CS/SHDN remains low, trailing zeros will clocked after sub-bits. With CS/SHDN high, wait least 60ns (tCS), before starting conversion pulling CS/SHDN low. conversion aborted pulling CS/SHDN high before conversion ends; wait least 60ns before starting conversion. Data output either 8-bit sequences continuously. bytes will contain result conversion padded with three leading ones, channel identification before MSB, trailing subbits. serial clock hasn't been idled after last sub-bit (S0) CS/SHDN kept low, DOUT sends trailing zeros.
Signal-to-Noise Plus Distortion (SINAD)
Signal-to-noise plus distortion ratio fundamental input frequency's amplitude equivalent other output signals: SINAD(dB)
(Noise SignalRMS Distortion)
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists quantization noise only. With input range equal full-scale range ADC, calculate effective number bits follows: ENOB (SINAD 1.76) 6.02
Total Harmonic Distortion (THD)
ratio first five harmonics input signal fundamental itself. This expressed
where fundamental amplitude through amplitudes through 5th-order harmonics.
MICROWIRE Interface
When using (Figure MICROWIRE (Figure interfaces, CPOL CPHA Conversion begins with falling edge CS/SHDN (Figure 8c). consecutive 8-bit readings necessary obtain entire 10-bit result from ADC. DOUT data transitions serial clock's falling edge clocked into SCLK's rising edge. first 8-bit data stream contains three leading ones, followed channel identification first four data bits starting with MSB. second 8-bit data stream contains remaining bits, through sub-bits
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Connection Standard Interfaces
MAX157/MAX159 interface fully compatible with SPI/QSPI MICROWIRE standard serial interfaces. serial interface available, establish CPU's serial interface master that generates
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
MISO CS/SHDN SCLK DOUT CS/SHDN SCLK DOUT
MICROWIRE
MAX157 MAX159
MAX157 MAX159
Figure Connections
Figure MICROWIRE Connections
BYTE READ SCLK CS/SHDN DOUT* SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH
BYTE READ
CHID
HIGH-Z
Figure SPI/MICROWIRE Interface Timing Sequence (CPOL CPHA
QSPI Interface
Using high-speed QSPI interface with CPOL CPHA MAX157/MAX159 supports maximum fSCLK 2.17MHz. QSPI circuit Figure programmed perform conversion each channels MAX157. Figure shows QSPI interface timing.
MISO CS/SHDN SCLK DOUT
QSPI
PIC16 with Module PIC17 Interface
MAX157/MAX159 compatible with PIC16/ PIC17 microcontroller (µC), using synchronous serial port (SSP) module. establish communication, connect controller shown Figure configure PIC16/PIC17 system master initializing synchronous serial port control register (SSPCON) synchronous serial port status register (SSPSTAT) patterns shown Tables mode, PIC16/PIC17 allow eight bits data synchronously transmitted received simultaneously. consecutive 8-bit readings (Figure 10b) necessary obtain entire 10-bit result from ADC. DOUT data transitions serial clock's falling edge clocked into SCLK's rising edge. first 8-bit data stream contains
MAX157 MAX159
Figure QSPI Connections
three leading ones, channel identification, first four data bits starting with MSB. second 8bit data stream contains remaining bits, through sub-bits
Layout, Grounding, Bypassing
best performance printed circuit boards (PCBs), wire-wrap configurations recommended, since layout should ensure proper separation analog digital traces. analog digital lines anti-parallel each other, don't layout digital signal paths underneath package. separate analog digital ground sections with only
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
SCLK CS/SHDN
HIGH-Z DOUT CHID SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH
Figure QSPI Interface Timing Sequence (CPOL CPHA
SCLK DOUT CS/SHDN
MAX157 MAX159
PIC16/PIC17
Figure 10a. Interface Connection PIC16/PIC17 Controller
star-point (Figure connecting ground systems (analog digital). lowest-noise operation, ensure ground return star ground's power supply impedance short possible. Route digital signals away from sensitive analog reference inputs. High-frequency noise power supply (VDD) could influence proper operation ADC's fast comparator. Bypass star ground with network parallel capacitors, 0.1µF 1µF, located close possible power supply MAX157/MAX159. Minimize capacitor lead length best supply-noise rejection attenuation resistor (10) power supply extremely noisy.
BYTE READ SCLK CS/SHDN
BYTE READ
HIGH-Z DOUT* CHID SAMPLING INSTANT *WHEN CS/SHDN HIGH, DOUT HIGH
Figure 10b. Interface Timing Sequence with PIC16/17 Master Mode (CKE SSPM3-SSPM0 0001)
POWER SUPPLIES
0.1µF DGND
MAX157 MAX159
OPTIONAL FILTER RESISTOR
DIGITAL CIRCUITRY
Figure Power-Supply Bypassing Grounding
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
Table Detailed SSPCON Register Content
CONTROL WCOL SSPOV SSPEN SSPM3 SSPM2 SSPM1 SSPM0 MAX157/MAX159 SETTINGS Synchronous Serial Port Mode Select Bit. Sets master mode selects fCLK fOSC SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) Write Collision Detection Receive Overflow Detect Synchronous Serial Port Enable Disables serial port configures these pins port pins. Enables serial port configures SCK, pins serial port pins. Clock Polarity Select Bit. master mode selection.
Don't care
Table Detailed SSPSTAT Register Content
CONTROL MAX157/MAX159 SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) Data Input Sample Phase. Input data sampled middle data output time. Clock Edge Select Bit. Data will transmitted rising edge serial clock. Data Address Stop Start Read/Write Information Update Address Buffer Full Status
Don't care
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX
Chip Information
TRANSISTOR COUNT: 2,058 SUBSTRATE CONNECTED
MAX157/MAX159
Package Information
8LUMAXD.EPS
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX MAX157/MAX159
Package Information (continued)
PDIPN.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs 8-Pin µMAX

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