IND: -15/25 PALCE22V10Z Family Zero-Power 24-Pin CMOS Versat

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

IND: -15/25 PALCE22V10Z Family Zero-Power 24-Pin CMOS Versat

Datasheet Thumbnail

Top Searches for this datasheet

COM'L:
IND: -15/25
PALCE22V10Z Family
Zero-Power 24-Pin CMOS Versatile Device
DISTINCTIVE CHARACTERISTICS
Zero-power CMOS technology standby current fast first-access propagation delay fMAX (external) Unused product term disable reduced power consumption Available Industrial operating range -40°C +85°C +4.5 +5.5 HCT-compatible inputs outputs Electrically-erasable technology provides reconfigurable logic full testability macrocells programmable registered combinatorial, active high active match application needs Varied product term distribution allows product terms output complex functions Global asynchronous reset synchronous preset initialization Power-up reset initialization register preload testability Extensive third-party software programmer support through FusionPLD partners 24-pin SKINNYDIP, 28-pin PLCC, 24-pin SOIC packages save space
GENERAL DESCRIPTION
PALCE22V10Z advanced device built with zero-power, high-speed, electrically-erasable CMOS technology. provides user-programmable logic replacing conventional zero-power CMOS SSI/MSI gates flip-flops reduced chip count. PALCE22V10Z provides zero standby power high speed. maximum standby current, PALCE22V10Z allows battery powered operation extended period. ZPALdevice implements familiar Boolean logic transfer function, products. device programmable array driving fixed array. array programmed create custom product terms, while array sums selected terms outputs. product terms connected fixed array with varied distribution from to16 across outputs (see Block Diagram). products feeds output macrocell. Each macrocell programmed registered combinatorial, active high active low. output configuration determined bits controlling multiplexers each macrocell. AMD's FusionPLD program allows PALCE22V10Z designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar. Please refer Software Reference Guide Compliers certified development systems, Programmer Reference Guide approved programmers.
2-244
Publication# 15700 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I0
PROGRAMMABLE ARRAY 132)
RESET
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9 15700E-1
CONNECTION DIAGRAMS View SKINNYDIP/SOIC
CLK/I0 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
PLCC
CLK/I0 I/O9 I/O8 I/O0 I/O1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2
15700E-3
15700E-2
Note: marked orientation.
DESCRIPTION
Clock Ground Input Input/Output Connect Supply Voltage
PALCE22V10Z Family
2-245
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination these elements:
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Zero Power standby)
OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028) 24-Pin Plastic Gull-Wing Small Outline Package SPEED
Valid Combinations PALCE22V10Z-15 PALCE22V10Z-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations, check newly released combinations.
2-246
PALCE22V10Z Family
FUNCTIONAL DESCRIPTION
PALCE22V10Z zero-power version PALCE22V10. architectural features PALCE22V10. addition, PALCE22V10Z zero standby power unused product term disable. PALCE22V10Z allows systems engineer implement design on-chip, programming cells configure gates within device, according desired logic function. Complex interconnections between gates, which previously required time-consuming layout, lifted from board placed silicon, where they easily modified during prototyping production. Product terms with connections opened assume logical HIGH state; product terms connected both true complement single input assume logical state. PALCE22V10Z inputs macrocells. macrocell (Figure allows four potential output configurations; registered output combinatorial I/O, active high active (see Figure configuration choice made according user's design specification corresponding programming configuration bits Multiplexer controls connected ground through programmable bit, selecting path through multiplexer. Erasing disconnects control line from floats (1), selecting path.
device produced with cell link each input gate array, connections selectively removed applying appropriate voltages circuit. Utilizing easily-implemented programming algorithm, these products rapidly programmed customized pattern.
Variable Input/Output Ratio
PALCE22V10Z twelve dedicated input lines, each macrocell output pin. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Unused input pins should tied GND.
Registered Output Configuration
Each macrocell PALCE22V10Z includes D-type flip-flop data storage synchronization. flipflop loaded LOW-to-HIGH transition clock input. registered configuration array feedback from flip-flop.
Combinatorial Configuration
macrocell configured combinatorial selecting multiplexer path that bypasses flip-flop combinatorial configuration feedback from pin.
Output Configuration Registered/Active Registered/Active High Combinatorial/Active Combinatorial/Active High I/On
Programmed Erased (charged)
15700E-4
Figure Output Logic Macrocell
PALCE22V10Z Family
2-247
Registered/Active Registered/Active High Combinatorial/Active High
15700E-5
Combinatorial/Active
Figure Macrocell Configuration Options
Programmable Three-State Outputs
Each output three-state output buffer with threestate control. product term controls buffer, allowing enable disable function product device inputs output feedback. combinatorial output provides bidirectional pin, configured dedicated input buffer always disabled.
Preset/Reset
initialization, PALCE22V10Z additional Preset Reset product terms. These terms connected registered outputs. When Synchronous Preset (SP) product term asserted high, output registers will loaded with HIGH next LOW-toHIGH clock transition. When Asynchronous Reset (AR) product term asserted high, output registers will immediately loaded with independent clock. Note that preset reset control flip-flop, output pin. output level determined output polarity selected.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection controlled programmable output macrocell, affects both registered combinatorial outputs. Selection automatic, based design specification definitions. definition output equation have same polarity, output programmed active high
Zero-Standby Power Mode
PALCE22V10Z features zero-standby power mode. When none inputs switch extended period (typically ns), PALCE22V10Z will into standby mode, shutting down most internal circuitry. current will almost zero (ICC µA). outputs will maintain states held before device went into standby mode.
2-248
PALCE22V10Z Family
When input switches, internal circuitry fully enabled power consumption returns normal. This feature results considerable power savings operation medium frequencies. This savings illustrated frequency graph.
Security
After programming verification, PALCE22V10Z design secured programming security bit. Once programmed, this defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. When security programmed, array will read every erased, preload will disabled. only erased conjunction with erasure entire pattern.
Product-Term Disable
programmed PALCE22V10Z, product terms that used disabled. Power from these product terms that they draw current. shown frequency graph, product-term disabling results considerable power savings. This savings greater higher frequencies. Further hints minimizing power consumption found Application Note "Minimizing Power Consumption with Zero-Power PLDs."
Programming Erasing
PALCE22V10Z programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Power-Up Reset
flip-flops power-up logic predictable system initialization. Outputs PALCE22V10Z will depend programmed output polarity. rise must monotonic reset delay time 1000 maximum.
Quality Testability
PALCE22V10Z offers very high level built-in quality. erasability CMOS PALCE22V10Z allows direct testing device array guarantee 100% programming functional yields.
Register Preload
registers PALCE22V10Z preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE22V10Z fabricated with AMD's advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input-clamp diodes, output slew-rate control, grounded substrate clean switching.
PALCE22V10Z Family
2-249
LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts
CLK/I
(28)
(27)
(26)
(25)
(24)
(23)
(21)
(20)
(19)
(10)
(18)
(11)
(17)
(12) (13)
(16)
(14)
15700E-6
2-250
PALCE22V10Z Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output -0.5 Voltage Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Operating Case Temperature (TC) -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions Output Voltage IOZH Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note Outputs Open (IOUT -150 3.84 VCC- 0.33 Unit
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE22V10Z-15 (Ind)
2-251
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Maximum Frequency Internal Feedback (fCNT) (Notes Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 58.8 62.5 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-252
PALCE22V10Z-15 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Operating Case Temperature (TC) -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions Output Voltage IOZH Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT (Note Outputs Open (IOUT -150 3.84 VCC- 0.33 Unit
Notes: These absolute values with respect device ground overshoots system tester noise included. Represents worst case standards, allowing compatibility with either. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE22V10Z-25 (Com'l, Ind)
2-253
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Condition VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Clock Width HIGH External Feedback Maximum Frequency Internal Feedback (fCNT) (Notes Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 33.3 35.7 Parameter Description Input Feedback Combinatorial Output (Note Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. This parameter tested Standby Mode. When device Standby Mode, will typically faster. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-254
PALCE22V10Z-25 (Com'l, Ind)
SWITCHING WAVEFORMS
Input Feedback Input Feedback Clock Combinatorial Output
15700E-7
Registered Output
15700E-8
Combinatorial Output
Registered Output
Input Clock
15700E-9
0.5V 0.5V
15700E-10
Output
Clock Width
Input Output Disable/Enable
Input Asserting Asynchronous Reset
tARW
Input Asserting Synchronous Preset
tSPR
Registered Output
tARR
Clock
Clock
15700E-11
Registered Output
15700E-12
Asynchronous Reset
Synchronous Preset
Notes: input signals VCC/2 output signals. Input pulse amplitude Input rise fall times ns-5 typical.
PALCE22V10Z Family
2-255
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
15700E-13
Specification tPD,
Closed Open Closed Open Closed
Closed Closed Open Closed Open
Measured Output Value VCC/2
VCC/2
2-256
PALCE22V10Z Family
TYPICAL CHARACTERISTICS PALCE22V10Z-15 25°C
100%* 50%*
25%*
(mA)
Frequency (MHz)
*Percent product terms used.
15700E-14
Frequency Graph PALCE22V10Z-15
PALCE22V10Z-25
2-257
TYPICAL CHARACTERISTICS PALCE22V10Z-25 25°C
100%* 50%* 25%*
(mA)
Frequency (MHz)
*Percent product terms used.
15700E-15
Frequency Graph PALCE22V10Z-25
2-258
PALCE22V10Z-15
ENDURANCE CHARACTERISTICS
PALCE22V10Z manufactured using AMD's advanced Electrically Erasable process. This technology
uses cell replace fuse link used bipolar parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Unit Years Years Cycles
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
ROBUSTNESS FEATURES
PALCE22V10Z some unique features that make extremely robust, especially when operating high speed design environments. Input clamping circuitry limits negative overshoot, eliminating possibility false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Input Protection Transition Detection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input Input Transition Detection
Typical Output
15700E-16
PALCE22V10Z Family
2-259
POWER-UP RESET PALCE22V10Z FAMILY
power-up reset feature ensures that flip-flops will reset after device been powered output state will depend programmed pattern. This feature valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways rise steady state, four conditions required ensure valid power-up reset. These conditions are:
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width Supply Voltage Prior Power-Up
supply voltage prior rise must exceed off. rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met. inputs switching time power-up, input transition must take place assure proper data set-up registers outputs.
1000
Unit
Switching Characteristics
Power
Registered Active-Low Output
Clock
15700E-17
Power-Up Reset Waveform
2-260
PALCE22V10Z Family

IND: -15/25 PALCE22V10Z Family Zero-Power 24-Pin CMOS Versat

Top Searches for this datasheet

Other recent searches