ANUAL LUATIO SHEET FOLLO Multirange, +5V, 8-Channel, Serial 12-Bi

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ANUAL LUATIO SHEET FOLLO Multirange, +5V, 8-Channel, Serial 12-Bi

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19-4782; 3/99
ANUAL LUATIO SHEET FOLLO
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
12-Bit Resolution, 1/2LSB Linearity Single-Supply Operation SPI/QSPI MICROWIRE-Compatible 3-Wire Interface Four Software-Selectable Input Ranges MAX1270: +10V, +5V, ±10V, MAX1271: VREF, VREF/2, ±VREF, ±VREF/2 Eight Analog Input Channels 110ksps Sampling Rate ±16.5V Overvoltage-Tolerant Input Multiplexer Internal 4.096V External Reference Power-Down Modes Internal External Clock 24-Pin Narrow 28-Pin SSOP Packages
General Description
MAX1270/MAX1271 multirange, 12-bit dataacquisition systems (DAS) that require only single supply operation, accept signals their analog inputs that span above power-supply rail below ground. These systems provide eight analog input channels that independently software programmable variety ranges: ±10V, ±5V, +10V, MAX1270; ±VREF, ±VREF/2, VREF, VREF/2 MAX1271. This range switching increases effective dynamic range bits provides flexibility interface 4-20mA, ±12V, ±15V powered sensors directly single system. addition, these converters fault protected ±16.5V; fault condition channel will affect conversion result selected channel. Other features include 5MHz bandwidth track/hold, softwareselectable internal/external clock, 110ksps throughput rate, internal 4.096V external reference operation. MAX1270/MAX1271 serial interface directly connects SPITM/QSPIand MICROWIREdevices without external logic. hardware shutdown input (SHDN) softwareprogrammable power-down modes, standby (STBYPD) full power-down (FULLPD), provided low-current shutdown between conversions. standby mode, reference buffer remains active, eliminating start-up delays. MAX1270/MAX1271 available 24-pin narrow space-saving 28-pin SSOP packages.
MAX1270/MAX1271
Typical Operating Circuit
0.1µF
SHDN
Applications
Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments
ANALOG INPUTS
MAX1270 MAX1271
MC68HCXX SCLK DOUT SSTRB AGND MOSI MISO
REFADJ 4.7µF 0.01µF DGND
Ordering Information
PART TEMP. RANGE PIN-PACKAGE (LSB) ±1/2 ±1/2
MAX1270ACNG +70°C Narrow Plastic MAX1270BCNG +70°C Narrow Plastic +70°C SSOP MAX1270ACAI MAX1270BCAI +70°C SSOP Ordering Information continued data sheet.
Configurations appear data sheet. QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp. 7-169
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
ABSOLUTE MAXIMUM RATINGS
AGND.-0.3V AGND DGND.-0.3V +0.3V CH0-CH7 AGND ±16.5V REF, REFADJ AGND .-0.3V (VDD 0.3V) SSTRB, DOUT DGND.-0.3V (VDD 0.3V) SHDN, DIN, SCLK DGND.-0.3V Current into .50mA Continuous Power Dissipation +70°C) 24-Pin Narrow (derate 13.33mW/°C above +70°C) .1067mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) .762mW Operating Temperature Ranges MAX127_C_ .0°C +70°C MAX127_E_ _.-40°C +85°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2.0MHz (50% duty cycle), clock/conversion cycle, 110ksps; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETERS ACCURACY (Note ACCURACY (Note Resolution Integral Nonlinearity Differential Nonlinearity MAX127_A MAX127_B missing codes over temperature Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note Bipolar Gain Error Temperature Coefficient (Note MAX127_A MAX127_B MAX127_A MAX127_B MAX127_A MAX127_B MAX127_A MAX127_B ±0.1 ±0.3 ppm/°C ±0.5 ±1.0 bits SYMBOL CONDITIONS UNITS
Unipolar, external reference Bipolar, external reference
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX1270), ±4.096Vp-p (MAX1271), fSAMPLE 110ksps) SPECIFICATIONS Signal-to-Noise Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter 7-170 SINAD SFDR 50kHz (Note ±16.5V External clock mode External clock mode Internal clock mode harmonic
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2.0MHz (50% duty cycle), clock/conversion cycle, 110ksps; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETERS ANALOG INPUT INPUT Track/Hold Acquisition Time tACQ fCLK 2.0MHz ±10V ±VREF range Small-Signal Bandwidth -3dB rolloff ±VREF/2 range VREF range VREF/2 range Unipolar (BIP Table Input Voltage Range Bipolar (BIP Table MAX1270 MAX1271 MAX1270 MAX1271 Input Current Bipolar MAX1271 Dynamic Resistance Input Capacitance INTERNAL REFERENCE INTERNAL REFERENCE Output Voltage Output Tempco Output Short Circuit Current Load Regulation (Note Capacitive Bypass Capacitive Bypass REFADJ REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain REFERENCEINPUT (Reference buffer disabled, reference input applied REF) REFERENCE INPUT (Reference Input Voltage Range Input Current VREF 4.18V Normal STBYPD FULLPD 2.40 4.18 Figure 0.5mA output current 0.01 2.465 2.500 ±1.5 1.638 2.535 VREF VREF +25°C MAX1270_C/MAX1271_C MAX1270_E/MAX1271_E 4.076 4.096 4.116 ppm/°C VIN/IIN Unipolar Bipolar (Note MAX1270 ±10V range range ±VREF range ±VREF/2 range MAX1270 MAX1271 range range -VREF -VREF/2 -1200 -600 -1200 -600 1.25 VREF VREF/2 VREF VREF/2 SYMBOL CONDITIONS UNITS
MAX1270/MAX1271
Unipolar
7-171
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
ELECTRICAL CHARACTERISTICS (continued)
(VDD +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2.0MHz (50% duty cycle), clock/conversion cycle, 110ksps; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETERS Input Resistance REFADJ Threshold Buffer Disable POWER REQUIREMENT POWER REQUIREMENT Supply Voltage Normal Supply Current Bipolar range Unipolar range ±0.1 ±0.5 4.75 5.25 ±0.5 SYMBOL VREF 4.18V CONDITIONS Normal STBYPD FULLPD 4.18 UNITS
STBYPD power down mode (Note FULLPD power down mode External reference 4.096V Internal reference
Power-Supply Rejection Ratio (Note TIMING External Clock Frequency Range Acquisition Phase Conversion Time Throughput Rate Bandgap Reference Start-Up Time (Note Reference Buffer Settling Time
PSRR
fCLK External clock mode (Note Internal clock mode, Figure tCONV External clock mode (Note Internal clock mode, Figure External clock mode Internal clock mode Power-up 0.1mV, bypass capacitor fully discharged VHYS (Note ISINK ISINK 16mA ISOURCE 0.5mA (Note CREF 4.7µF CREF 33µF
ksps
DIGITAL INPUTS: DIN, SCLK, SHDN INPUTS: DIN, SCLK, Input High Threshold Voltage Input Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS: DOUT, SSTRB OUTPUTS: DOUT, Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance COUT
7-172
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
TIMING CHARACTERISTICS
(VDD +4.75V +5.25; unipolar/bipolar range; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2MHz; TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figures PARAMETERS SCLK Setup SCLK Hold SCLK Fall Output Data Valid Fall Output Enable Rise Output Disable SCLK Rise Setup SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width SCLK Fall SSTRB SSTRB Output Enable SSTRB Output Disable SSTRB Rise SCLK Rise (Note SYMBOL tCSS tCSH tSSTRB tSDV tSTR tSCK CLOAD 100pF CLOAD 100pF External clock mode only CLOAD 100pF External clock mode only Internal clock mode only CLOAD 100pF CLOAD 100pF CLOAD 100pF CONDITIONS UNITS
MAX1270/MAX1271
Note Accuracy specifications tested +5.0V. Performance power-supply tolerance limit guaranteed Power-Supply Rejection test. Note External reference: VREF 4.096V, offset error nulled. Ideal last-code transition 3/2LSB. Note Ground "on" channel; sine wave applied "off" channels. (MAX1270), (MAX1271). Note Guaranteed design, production tested. Note static external loads during conversion specified accuracy. Note Tested using internal reference. Note PSRR measured full scale. Tested ±10V (MAX1270) ±4.096V (MAX1271) input ranges. Note Acquisition phase conversion time dependent clock period; clock duty cycle (Figure Note production tested. Provided design guidance only.
7-173
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Typical Operating Characteristics
(Typical Operating Circuit, +5V; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2MHz; 110ksps; +25°C; unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
MAX1270/1 toc01
SUPPLY CURRENT TEMPERATURE
MAX1270/1 toc02
STANDBY SUPPLY CURRENT TEMPERATURE
MAX1270/1 toc03
STANDBY SUPPLY CURRENT (µA) EXTERNAL REFERENCE INTERNAL REFERENCE
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX1270/1 toc05
MAX1270/1 toc04
FULL POWER-DOWN SUPPLY CURRENT (µA)
BIPOLAR MODE
NORMALIZED REFERENCE VOLTAGE
0.30 0.25 0.20 0.15 0.10 0.05 UNIPOLAR MODE
EXTERNAL REFERENCE
1.000
0.999
INTERNAL REFERENCE
0.998
0.997
TEMPERATURE (°C)
0.996 TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING TEMPERATURE
MAX1270/1 toc07
INTEGRAL NONLINEARITY DIGITAL CODE
MAX1270/1 toc08
PLOT
10kHz fSAMPLE 110ksps
MAX1270/1 toc09
UNIPOLAR MODE
0.15 INTEGRAL NONLINEARITY (LSB) 0.10 0.05 -0.05 -0.10 -0.15
AMPLITUDE (dB) -100 -120
BIPOLAR MODE
1638
2457
3276
4095
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (Hz)
7-174
MAX1270/1 toc06
1.001
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
FULL POWER-DOWN SUPPLY CURRENT TEMPERATURE
NORMALIZED REFERENCE VOLTAGE TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING TEMPERATURE
0.35
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Typical Operating Characteristics (continued)
(Typical Operating Circuit, +5V; external reference mode, VREF +4.096V; 4.7µF REF; external clock, fCLK 2MHz; 110ksps; +25°C; unless otherwise noted.) AVERAGE SUPPLY CURRENT AVERAGE SUPPLY CURRENT CONVERSION RATE (USING FULLPD) CONVERSION RATE (USING STANDBY)
MAX1270-toc10
AVERAGE SUPPLY CURRENT (mA)
AVERAGE SUPPLY CURRENT (mA)
INTERNAL REFERENCE, fCLK 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_
INTERNAL REFERENCE, fCLK 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_
1000
1000
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
Description
SSOP 15-21, NAME DGND N.C. FUNCTION Supply. Bypass with 0.1µF capacitor AGND. Digital Ground Connect. internal connection.
13-20
SCLK SSTRB DOUT SHDN AGND CH0- REFADJ
Serial Clock Input. Clocks data serial interface. external clock mode, SCLK also sets conversion speed. Active-Low Chip-Select Input. Data clocked into unless low. When high, DOUT high impedance. Serial Data Input. Data clocked rising edge SCLK. Serial Strobe Output. internal clock mode, SSTRB goes after falling edge eighth SCLK returns high when conversion done. external clock mode, SSTRB pulses high clock period before decision. High impedance when high external clock mode. Serial Data Output. Data clocked falling edge SCLK. High impedance when high. Shutdown Input. When low, device FULLPD mode. Connect high normal operation. Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with 0.01µF capacitor AGND. Connect when using external reference REF. Reference-Buffer Output/ADC Reference Input. internal reference mode, reference buffer provides 4.096V nominal output, externally adjustable REFADJ. external reference mode, disable internal reference pulling REFADJ applying external reference REF. 7-175
MAX1270-toc11
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
510k 100k 0.01µF HIGH-Z VOH, VOH, HIGH-Z HIGH-Z VOH, VOH, HIGH-Z REFADJ
MAX1270 MAX1271
DOUT SSTRB 0.5mA CLOAD
DOUT SSTRB
CLOAD
Figure Reference-Adjust Circuit
Figure Output Load Circuit Timing Characteristics
Detailed Description
Converter Operation
MAX1270/MAX1271 multirange, fault-tolerant ADCs successive approximation internal track/hold (T/H) circuitry convert analog signal 12-bit digital output. Figure shows block diagram MAX1270/MAX1271.
Analog-Input Track/Hold
enters tracking/acquisition mode falling edge sixth clock 8-bit input control word, enters hold/conversion mode when timed acquisition interval (six clock cycles, minimum) ends. internal clock mode, acquisition timed external clock cycles four internal clock cycles. When operating bipolar (MAX1270 MAX1271)
unipolar mode (MAX1270) signal applied input channel rescaled through resistor-divider network formed (Figure lowimpedance (<4) input source recommended minimize gain error. When MAX1271 configured unipolar mode, channel input resistance (RIN) becomes fixed 5.12k (typ). Source impedances below VREF) VREF/2) significantly affect performance ADC. acquisition time (tACQ) function source output resistance, channel input resistance, capacitance. Higher source impedances used input capacitor connected between analog inputs AGND. Note that input capacitor forms filter with input source impedance, limiting ADC's signal bandwidth.
SSTRB
DOUT
SCLK
SHDN
SERIAL INTERFACE LOGIC
CLOCK AGND DGND CLOCK 12-BIT
ANALOG INPUT SIGNAL CONDITIONING
+4.096V
2.5V REFERENCE REFADJ
1.638
MAX1270 MAX1271
Figure Block Diagram 7-176
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Input Bandwidth
ADC's input small-signal bandwidth depends selected input range varies from 1.5MHz 5MHz (see Electrical Characteristics). MAX1270/ MAX1271 maximum sampling rate 110ksps. using undersampling techniques, possible digitize high-speed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate. avoid high-frequency signals being aliased into frequency band interest, anti-aliasing filtering recommended.
Digital Interface
MAX1270/MAX1271 feature serial interface that fully compatible with SPI/QSPI MICROWIRE devices. SPI/QSPI, CPOL CPHA control registers microcontroller. Figure shows detailed serial interface timing information. Refer Table programming input control byte.
MAX1270/MAX1271
BIPOLAR UNIPOLAR 5.12k HOLD TRACK TRACK CHOLD
VOLTAGE REFERENCE
Input Range Protection
MAX1270/MAX1271 have software-selectable input ranges. Each analog input channel independently programmed four ranges setting appropriate control bits (RNG, BIP) control byte (Table MAX1270 selectable input ranges extending ±10V (±VREF 2.441), while MAX1271 selectable input ranges extending ±VREF. Figure shows equivalent input circuit. resistor network each analog input provides ±16.5V fault protection channels. Whether channel this circuit limits current going into less than 2mA. This provides added layer protection when momentary overvoltages occur selected input channel, when negative signal applied input, when device configured unipolar mode. overvoltage protection active even device power-down mode
HOLD
BIPOLAR/UNIPOLAR SWITCH INPUT SWITCH SWITCH
12.5k (MAX1270) 5.12k (MAX1271) 8.67k (MAX1270) (MAX1271)
Figure Equivalent Input Circuit
tCSH SCLK
tCSS
tCSH
DOUT
Figure Detailed Serial-Interface Timing 7-177
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Table Control-Byte Format
(MSB) START (MSB) (LSB) SEL2 NAME START SEL2, SEL1, SEL0 PD1, SEL1 SEL0 (LSB)
DESCRIPTION First logic after goes defines beginning control byte. These three bits select desired "on" channel (Table Selects full-scale input voltage range (Table Selects unipolar bipolar conversion mode (Table Select clock power-down modes (Table
Table Channel Selection
SEL2 SEL1 SEL0 CHANNEL
Table Power Down Clock Selection
MODE Normal Operation (always on), Internal Clock Mode Normal Operation (always on), External Clock Mode Standby Power-Down Mode (STBYPD), Clock Mode Unaffected Full Power-Down Mode (FULLPD), Clock Mode Unaffected
Table Range Polarity Selection MAX1270/MAX1271
RANGE POLARITY SELECTION MAX1270 Range Polarity INPUT RANGE ±10V NEGATIVE FULL SCALE -VREF 1.2207 -VREF 2.4414 NEGATIVE FULL SCALE -VREF/2 -VREF ZERO SCALE FULL SCALE VREF 1.2207 VREF 2.4414 VREF 1.2207 VREF 2.4414
Range Polarity RANGE POLARITY SELECTION MAX1271 INPUT RANGE VREF/2 VREF ±VREF/2 ±VREF ZERO SCALE FULL SCALE VREF/2 VREF VREF/2 VREF
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Input Data Format Input data (control byte) clocked rising edge SCLK. enables communication with MAX1270/MAX1271. After falls, first arriving logic represents start (MSB) input control byte. start defined first high clocked into with anytime converter idle; e.g., after applied. first high clocked into after (D6) conversion progress clocked onto DOUT. Output Data Format Output data clocked falling edge SCLK DOUT, first (D11). unipolar mode, output straight binary. bipolar mode, output two'scomplement binary. output binary codes, refer Transfer Function section. Start Conversion MAX1270/MAX1271 either external serial clock internal clock complete acquisition perform conversion. both clock modes, external clock shifts data out. Refer Table programming clock modes. falling edge does start conversion MAX1270/MAX1271; control byte required each conversion. Acquisition starts after sixth programmed input control byte. Conversion starts when acquisition time, clock cycles, expires. Keep during successive conversions. startbit received after transitions from high low, before output (D6) becomes available, current conversion will terminate conversion will begin. External Clock Mode (PD1 external clock mode, clock shifts data MAX1270/MAX1271 controls acquisition conversion timings. When acquisition done, SSTRB pulses high clock cycle conversion begins. Successive-approximation decisions appear DOUT each next SCLK falling edges (Figure Additional SCLK falling edges will result zeros appearing DOUT. Figure shows SSTRB timing external clock mode. SSTRB DOUT into high-impedance state when goes high; after next falling edge, SSTRB DOUT will output logic low. conversion must completed some minimum time, droop sample-and-hold capacitors degrade conversion results. internal clock mode clock period exceeds 10µs, serial-clock interruptions could cause conversion interval exceed 120µs. fastest MAX1270/MAX1271 clocks conversion external clock mode, with clock rate 2MHz, maximum sampling rate ksps (Figure order achieve maximum throughput, keep low, external clock mode with continuous SCLK, start following control byte after (D6) conversion progress clocked onto DOUT. SCLK continuous, guarantee start first clocking zeros.
MAX1270/MAX1271
SCLK
SSTRB HIGH-Z DOUT HIGH-Z
START SEL2 SEL1 SEL0
HIGH-Z FILLED WITH HIGH-Z ZEROS
STATE
ACQUISITION SCLK
CONVERSION SCLK
Figure External Clock Mode, Clocks/Conversion Timing 7-179
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
tSDV SSTRB HIGH-Z tSTR HIGH-Z
tSSTRB tSSTRB SCLK
SCLK
Figure External Clock Mode SSTRB Detailed Timing
SCLK
CONTROL BYTE
CONTROL BYTE
START SEL2 SEL1 SEL0
CONTROL BYTE
START SEL2
START SEL2 SEL1 SEL0
HIGH-Z SSTRB
SCLK
RESULT
RESULT
HIGH-Z DOUT
SCLK STATE ACQUISITION SCLK CONVERSION SCLK ACQUISITION SCLK CONVERSION SCLK
Figure External Clock Mode, Clocks/Conversion Timing
Internal Clock Mode (PD1 internal clock mode, MAX1270/MAX1271 generate their conversion clock internally. This frees microprocessor from burden running acquisition conversion clock, allows conversion results read back processor's convenience, clock rate from typically 10MHz. SSTRB goes after falling edge last (PD0) control byte been shifted returns high when conversion complete. Acquisition completed conversion begins falling edge internal clock pulse after control byte; conversion ends falling edge
7-180
16th internal clock pulse internal clock cycle pulses used conversion). SSTRB will remain maximum 15µs, during which time SCLK should remain best noise performance. internal register stores data while conversion progress. result byte (D11) present DOUT starting falling edge last internal clock conversion. Successive falling edges SCLK will shift remaining data this register (Figure Additional SCLK edges will result zeros DOUT. When internal clock mode selected, SSTRB does into high-impedance state when goes high. Pulling high prevents data from being clocked three-states DOUT, does adversely affect
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
SCLK
SSTRB
START SEL2 SEL1 SEL0
DOUT HIGH-Z HIGH-Z ACQUISITION CONVERSION STATE SCLK
FILLED WITH ZEROS
HIGH-Z
Figure Internal Clock Mode, SCLK/Conversion Timing
tCSS tCSH tSCK
SSTRB tSSTRB SCLK
SCLK
NOTE: BEST NOISE PERFORMANCE, KEEP SCLK DURING CONVERSION.
Figure Internal Clock Mode SSTRB Detailed Timing
conversion progress. Figure shows SSTRB timing internal clock mode. Internal clock mode conversions completed with external clocks conversion require waiting period 15µs conversion completed (Figure 11). Most microcontrollers require that conversions occur multiples SCLK clock cycles; clock cycles conversion, shown Figure will typically most convenient microcontroller drive MAX1270/MAX1271.
Applications Information
Power-On Reset
MAX1270/MAX1271 power normal operation (all internal circuitry active) internal clock mode, waiting start bit. contents output data register cleared power-up.
Internal External Reference
MAX1270/MAX1271 operate with either internal external reference. external reference connected either REFADJ (Figure 13). REFADJ internal buffer gain trimmed 1.638V provide 4.096V from 2.5V reference.
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
CONTROL BYTE
START SEL2 SEL1 SEL0
SCLK
CONTROL BYTE
START SEL2 SEL1 SEL0
CONTROL BYTE
START SEL2 SEL1 SEL0
SCLK SSTRB RESULT HIGH-Z DOUT
RESULT
SCLK ACQUISITION CONVERSION STATE ACQUISITION CONVERSION
Figure Internal Clock Mode, Clocks/Conversion Timing
START
SCLK
CONTROL BYTE
START SEL2 SEL1 SEL0
CONTROL BYTE
START SEL2 SEL1 SEL0
SCLK SSTRB RESULT DOUT HIGH-Z HIGH-Z
RESULT HIGH-Z
SCLK ACQUISITION CONVERSION STATE IDLE ACQUISITION CONVERSION
Figure Internal Clock Mode, Clocks/Conversion Timing
Internal Reference internally trimmed 2.50V reference amplified through REFADJ buffer provide 4.096V REF. Bypass with 4.7µF capacitor AGND REFADJ with 0.01µF capacitor AGND (Figure 13a). internal reference voltage adjustable ±1.5% (±65 LSBs) with reference-adjust circuit Figure External Reference input directly, disable internal buffer tying REFADJ (Figure 13b). Using REFADJ input eliminates need buffer reference externally. When reference applied REFADJ, bypass REFADJ with 0.01µF capacitor AGND. Note that when external reference applied REFADJ, voltage given
7-182
VREF 1.6384 VREFADJ (2.4 VREF 4.18) (Figure 13c). REFADJ, input impedance minimum currents. During conversions, external reference must able deliver 400µA load currents must have output impedance less. reference higher output impedance noisy, bypass with 4.7µF capacitor AGND close chip possible. With external reference voltage less than 4.096V less than 2.5V REFADJ, increase ratio noise value (full-scale 4096) results performance degradation (loss effective bits).
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Power-Down Mode
4.7µF CREF 1.638 REFADJ 0.01µF
MAX1270/MAX1271
MAX1270 MAX1271
2.5V
Figure 13a. Internal Reference
save power, configure converter into low-current shutdown mode between conversions. programmable power-down modes available addition hardware shutdown. Select STBYPD FULLPD programming input control byte (Table When software power-down asserted, becomes effective only after conversion. example, control byte contains then chip will remain powered then chip will power-down conversion. powerdown modes, interface remains active conversion results read. Input overvoltage protection active power-down modes. first logical after falls interpreted start condition, powers MAX1270/ MAX1271 from software selected STBYPD FULLPD condition. hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown asserted, becomes effective immediately, conversion progress aborted. Choosing Power-Down Modes bandgap reference reference buffer remain active STBYPD mode, maintaining voltage 4.7µF capacitor REF. This "DC" state that does degrade after power-down duration. FULLPD mode, only bandgap reference active. Connect 33µF capacitor between AGND maintain reference voltage between conversions reduce transients when buffer enabled disabled. Throughput rates down 1ksps achieved without allotting extra acquisition time reference recovery prior conversion. This allows conversion begin immediately after power-up. discharge capacitor during FULLPD exceeds desired limits accuracy (less than fraction LSB), STBYPD power-down cycle prior starting conversions. Take into account that reference buffer recharges bypass capacitor 80mV/ms slew rate, 50µs settling time. Auto-Shutdown Selecting STBYPD every conversion automatically shuts down MAX1270/MAX1271 after each conversion without requiring start-up time next conversion.
4.096V 4.7µF CREF
MAX1270 MAX1271
1.638 REFADJ
2.5V
Figure 13b. External Reference, Reference
MAX1270 MAX1271
1.638 REFADJ
4.7µF CREF
2.5V 0.01µF
2.5V
Figure 13c. External Reference, Reference REFADJ
7-183
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
OUTPUT CODE 000. 000. 111. FULL-SCALE TRANSITION OUTPUT CODE 4096 011. 011. 4096
INPUT VOLTAGE (LSB)
100. 100. 100. INPUT VOLTAGE (LSB)
Figure 14a. Unipolar Transfer Function
Figure 14b. Bipolar Transfer Function
Transfer Function
Output data coding MAX1270/MAX1271 binary unipolar mode with 1LSB 4096) two's complement binary bipolar mode with 1LSB 4096]. Code transitions occur halfway between successive-integer values. Figures show input/output (I/O) transfer functions unipolar bipolar operations, respectively. full-scale values, refer Table
SUPPLY
4.7µF 0.1µF AGND DGND DGND
Layout, Grounding, Bypassing
Careful printed circuit board layout essential best system performance. ground plane best performance. reduce crosstalk noise injection, keep analog digital signals separate. Connect analog grounds DGND star configuration AGND. noise-free operation, ensure ground return from AGND supply ground impedance short possible. Connect logic grounds directly supply ground. Bypass with 0.1µF 4.7µF capacitors AGND minimize highand low-frequency fluctuations. supply excessively noisy, connect resistor between supply VDD, shown Figure
MAX1270 MAX1271
DIGITAL CIRCUITRY
OPTIONAL CONNECT AGND DGND WITH GROUND PLANE SHORT TRACE.
Figure Power-Supply Grounding Connections
7-184
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Configurations
VIEW
DGND N.C. DGND SCLK SSTRB N.C. DOUT SHDN AGND N.C. N.C. REFADJ DGND DGND N.C. SCLK N.C. N.C. SSTRB N.C. DOUT SHDN AGND N.C. REFADJ N.C. N.C.
MAX1270/MAX1271
MAX1270 MAX1271
MAX1270 MAX1271
N.C.
SSOP
Ordering Information (continued)
PART TEMP. RANGE PIN-PACKAGE (LSB) ±1/2 ±1/2 ±1/2 ±1/2 ±1/2
Chip Information
TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED AGND
MAX1270AENG -40°C +85°C Narrow Plastic MAX1270BENG -40°C +85°C Narrow Plastic MAX1270AEAI -40°C +85°C SSOP MAX1270BEAI -40°C +85°C SSOP MAX1271ACNG +70°C Narrow Plastic MAX1271BCNG +70°C MAX1271ACAI +70°C MAX1271BCAI +70°C MAX1271AENG -40°C +85°C Narrow Plastic SSOP SSOP Narrow Plastic
MAX1271BENG -40°C +85°C Narrow Plastic MAX1271AEAI -40°C +85°C SSOP ±1/2 MAX1271BEAI -40°C +85°C SSOP
7-185
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
_Package Information
PDIPN.EPS
7-186
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Package Information (continued)
MAX1270/MAX1271
7-187
SSOP.EPS
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
NOTES
7-188

ANUAL LUATIO SHEET FOLLO Multirange, +5V, 8-Channel, Serial 12-Bi

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