ATION EVALU ILABLE Multirange, Single +5V, 12-Bit with 12-Bit Int

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ATION EVALU ILABLE Multirange, Single +5V, 12-Bit with 12-Bit Int

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19-0435; 9/95
ATION EVALU ILABLE
Multirange, Single +5V, 12-Bit with 12-Bit Interface
12-Bit Resolution, 1/2LSB Linearity Single Supply Operation Software-Selectable Input Ranges: ±10V, ±5V, +10V, (MAX196) ±VREF, ±VREF/2, +VREF, +VREF/2 (MAX198) Internal 4.096V External Reference Fault-Protected Input Multiplexer Analog Input Channels Conversion Time, 100ksps Sampling Rate Internal External Acquisition Control Power-Down Modes Internal External Clock
_General Description
MAX196/MAX198 multirange, 12-bit data-acquisition systems (DAS) require only single supply operation, convert analog signals their inputs ±10V (MAX196) (MAX198). These systems provide analog input channels that independently software programmable variety ranges: ±10V, ±5V, +10V, MAX196; ±VREF, ±VREF/2, +VREF, +VREF/2 MAX198. This range switching increases effective dynamic range bits provides flexibility interface ±12V, ±15V, 20mA powered sensors single system. addition, these converters fault protected ±16.5V; fault condition channel will affect conversion result selected channel. Other features include 5MHz bandwidth track/hold, 100ksps throughput rate, software-selectable internal/external clock, internal/external acquisition control, 12-bit parallel interface, internal 4.096V external reference. programmable power-down modes (STBYPD, FULLPD) provide low-current shutdown between conversions. STBYPD mode, reference buffer remains active, eliminating start-up delays. MAX196/MAX198 employ standard microprocessor (µP) interface. three-state data port configured operate with 16-bit data buses, dataaccess bus-release timing specifications compatible with most popular µPs. logic inputs outputs TTL/CMOS compatible. These devices available 28-pin DIP, wide SSOP (55% smaller area than wide SO), ceramic packages. interface, MAX197 MAX199 data sheets. evaluation will available after December 1995 (MAX196EVKIT-DIP).
MAX196/MAX198
_Ordering Information
PART MAX196ACNI MAX196BCNI MAX196ACWI MAX196BCWI MAX196ACAI MAX196BCAI TEMP. RANGE +70°C +70°C +70°C +70°C +70°C +70°C PIN-PACKAGE Narrow Plastic Narrow Plastic Wide Wide SSOP SSOP
Ordering Information continued data sheet.
_Pin Configuration
VIEW
DGND
_Applications
Industrial-Control Systems Robotics Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications
MAX196 MAX198
REFADJ AGND
Functional Diagram appears data sheet.
DIP/SO/SSOP/Ceramic
Maxim Integrated Products
Call toll free 1-800-722-8266 free samples literature.
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
ABSOLUTE MAXIMUM RATINGS
AGND.-0.3V AGND DGND.-0.3V +0.3V AGND.-0.3V (VDD 0.3V) REFADJ AGND.-0.3V (VDD 0.3V) Digital Inputs DGND.-0.3V (VDD 0.3V) Digital Outputs DGND .-0.3V (VDD 0.3V) CH0-CH5 AGND .±16.5V Continuous Power Dissipation +70°C) Narrow Plastic (derate 14.29mW/°C above +70°C).1143mW Wide (derate 12.50mW/°C above +70°C).1000mW SSOP (derate 9.52mW/°C above +70°C) .762mW Narrow Ceramic (derate 20.00mW/°C above +70°C).1600mW Operating Temperature Ranges MAX196_C_ I/MAX198_C_ .0°C +70°C MAX196_E_ I/MAX198_E_ .-40°C +85°C MAX196_MYI/MAX198_MYI.-55°C +125°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 2.0MHz with duty cycle; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note Bipolar Gain Temperature Coefficient (Note Unipolar Bipolar MAX196A/MAX198A MAX196B/MAX198B harmonic 50kHz, (MAX196) (MAX198) (Note External mode/external acquisition control External mode/external acquisition control Aperture Jitter Internal mode/internal acquisition control (Note MAX196A/MAX198A MAX196B/MAX198B MAX196A/MAX198A MAX196B/MAX198B MAX196A/MAX198A MAX196B/MAX198B MAX196A/MAX198A MAX196B/MAX198B ±0.1 ±0.5 ppm/°C MAX196A/MAX198A MAX196B/MAX198B ±1/2 Bits SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX196) ±4.096Vp-p (MAX198), fSAMPLE 100ksps) Signal-to-Noise Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay SINAD SFDR
Multirange, Single +5V, 12-Bit with 12-Bit Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 2.0MHz with duty cycle; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER ANALOG INPUT Track/Hold Acquisition Time fCLK 2.0MHz ±10V ±VREF range Small-Signal Bandwidth -3dB rolloff ±VREF/2 range VREF range VREF/2 range MAX196 Unipolar MAX198 Input Voltage Range (see Table MAX196 Bipolar MAX198 MAX196 MAX198 Input Current Bipolar MAX198 Input Resistance Input Capacitance INTERNAL REFERENCE Output Voltage Output Tempco (Contact Maxim Applications guaranteed temperature drift specifications) Output Short-Circuit Current Load Regulation Capacitive Bypass REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain With recommended circuit (Figure VREF VREF +25°C MAX196_C/MAX198_C MAX196_E/MAX198_E MAX196_M/MAX198_M 0.5mA output current (Note 2.465 2.500 ±1.5 1.6384 2.535 4.076 4.096 ppm/°C 4.116 Unipolar Bipolar (Note MAX196 ±10V range range ±VREF range ±VREF/2 range -1200 -600 -1200 -600 range range -VREF -VREF/2 1.25 VREF VREF/2 VREF VREF/2 SYMBOL CONDITIONS UNITS
MAX196/MAX198
Unipolar
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 2.0MHz with duty cycle; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER Input Voltage Range Input Current VREF 4.18V Normal, STANDBY power-down mode FULL power-down mode 50mV SYMBOL CONDITIONS 4.18 UNITS
REFERENCE INPUT (buffer disabled, reference input applied pin)
Input Resistance REFADJ Threshold Buffer Disable POWER REQUIREMENTS Supply Voltage
Normal, STANDBY power-down mode FULL power-down mode
4.75 Normal mode, bipolar ranges Normal mode, unipolar ranges STANDBY power-down mode FULL power-down mode (Note External reference 4.096V Internal reference CCLK 100pF External Internal 1.25 Internal acquisition CREF 4.7µF CREF 33µF ±0.1 ±1/2 1.56
5.25 ±1/2
Supply Current
Power-Supply Rejection Ratio (Note TIMING Internal Clock Frequency External Clock Frequency Range
PSRR
fCLK fCLK tACQI
2.00
Acquisition Time tACQE Conversion Time Throughput Rate Bandgap Reference Start-Up Time Reference Buffer Settling tCONV
External acquisition (Note After FULLPD STBYPD External Internal CLK, CCLK 100pF External Internal CLK, CCLK 100pF Power-up (Note 0.1mV bypass capacitor fully discharged
10.0
ksps
DIGITAL INPUTS (D7-D0, CLK, (Note Input High Voltage Input Voltage Input Leakage Current Input Capacitance VINH VINL (Note
Multirange, Single +5V, 12-Bit with 12-Bit Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 2.0MHz with duty cycle; TMIN TMAX; unless otherwise noted. Typical values +25°C.) PARAMETER Output Voltage Output High Voltage Three-State Output Capacitance SYMBOL COUT CONDITIONS 4.75V, ISINK 1.6mA 4.75V, ISOURCE (Note UNITS DIGITAL OUTPUTS (D11-D0, INT)
MAX196/MAX198
TIMING CHARACTERISTICS
(VDD ±5%; unipolar/bipolar range; external reference mode, VREF 4.096V; 4.7µF pin; external clock, fCLK 2.0MHz with duty cycle; TMIN TMAX; unless otherwise noted.) PARAMETER Pulse Width Pulse Width Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time Data Valid Setup Data Valid Hold Output Data Valid High Output Disable High Delay Note Note Note Note Note Note Note Note Note Note Note Note Note SYMBOL tCSWS tCSWH tCSRS tCSRH tCWS tCWH tINT1 Figure 100pF (Note (Note CONDITIONS UNITS
Accuracy specifications tested 5.0V. Performance power-supply tolerance limits guaranteed Power-Supply Rejection test. Tested ±10V (MAX196) ±4.096V (MAX198) input ranges. External reference: VREF 4.096V, offset error nulled, ideal last code transition 3/2LSB. Ground "on" channel; sine wave applied "off" channels. Maximum full-power input frequency 1LSB error with 10ns jitter 3kHz. Guaranteed design. tested. static loads only. Tested using internal reference. PSRR measured full-scale. External acquisition timing: starts data valid ACQMOD control byte; ends rising edge with ACQMOD high control byte. subject production testing. Provided design guidance only. input control signals specified with from voltage level 0.8V 2.4V. measured with load circuits Figure defined time required output cross 0.8V 2.4V. defined time required data lines change 0.5V.
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
_Typical Operating Characteristics
+25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY DIGITAL CODE
MAX196/8-1
PLOT
MAX196/8-2
EFFECTIVE NUMBER BITS INPUT FREQUENCY
fSAMPLE 100kHz EFFECTIVE NUMBER BITS 11.5
MAX196/8-3
0.250 INTEGRAL NONLINEARITY (LSB) 0.200 0.150
AMPLITUDE (dB) -100 -120 fTONE 10kHz fSAMPLE 100kHz
12.0
0.100 0.050 -0.050 -0.100 -0.150 1000 2000 3000 4000 DIGITAL CODE
11.0
10.5
10.0 FREQUENCY (kHz) INPUT FREQUENCY (kHz)
REFERENCE OUTPUT VOLTAGE (VREF) TEMPERATURE
MAX196/8-4
POWER-SUPPLY REJECTION RATIO TEMPERATURE
±0.25V PSRR (LSB) 100Hz -0.2 120Hz
MAX196/8-5 MAX196/8-7
4.100
4.095 VREF
4.090 1.6384 +2.5V INTERNAL REFERENCE REFADJ
4.085
-0.4
4.080 TEMPERATURE (°C)
-0.6 TEMPERATURE (°C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
MAX196/8-6
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING TEMPERATURE
0.33 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) 0.32 0.31 0.30 0.29 0.28 0.27 TEMPERATURE (°C)
0.20
0.18
0.16
0.14
0.12
0.10 TEMPERATURE (°C)
Multirange, Single +5V, 12-Bit with 12-Bit Interface
_Pin Description
3-14 16-21 NAME D11-D0 AGND CH0-CH5 REFADJ FUNCTION Clock Input. external clock mode, drive with TTL/CMOS-compatible clock. internal clock mode, place capacitor (CCLK) from this ground internal clock frequency; fCLK 1.56MHz typical with CCLK 100pF. Chip Select, active Three-State Digital I/O, Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with 0.01µF capacitor AGND. Connect when using external reference pin. Reference Buffer Output/ADC Reference Input. internal reference mode, reference buffer provides 4.096V nominal output, externally adjustable REFADJ. external reference mode, disable internal buffer pulling REFADJ VDD. goes when conversion complete output data ready. low, falling edge will enable read operation data bus. internal acquisition mode, when low, rising edge latches configuration data starts acquisition plus conversion cycle. external acquisition mode, when CSis low, first rising edge starts acquisition, second rising edge ends acquisition starts conversion cycle. Supply. Bypass with 0.1µF capacitor AGND. Digital Ground
MAX196/MAX198
DGND
510k 100k 0.01µF REFADJ
_Detailed Description
Converter Operation
MAX196/MAX198 multirange, fault-tolerant ADCs successive approximation internal input track/hold (T/H) circuitry convert analog signal 12-bit digital output. 12-bit parallel-output format provides easy interface microprocessors (µPs). Figure shows MAX196/MAX198 simplest operational configuration.
MAX196 MAX198
Figure Reference-Adjust Circuit
Analog-Input Track/Hold
DOUT CLOAD DOUT CLOAD
High-Z
High-Z
Figure Load Circuits Enable Time
internal acquisition control mode (control enters tracking mode WR's rising edge, enters hold mode when internally timed clock cycles) acquisition interval ends. bipolar mode unipolar mode (MAX196 only), lowimpedance input source, which settles less than 1.5µs, required maintain conversion accuracy maximum conversion rate. When MAX198 configured unipolar mode, input does need driven from low-impedance source. acquisition time (tAZ) function source output resistance (RS), channel input resistance (RIN), capacitance.
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
Acquisition time calculated follows: VREF: RIN) 16pF VREF/2: RIN) 32pF where never less than VREF range) VREF/2 range). external acquisition control mode enters tracking mode first rising edge enters hold mode when detects second rising edge with (see External Acquisition section).
100pF CONTROL INPUTS
Input Bandwidth
ADC's input tracking circuitry 5MHz smallsignal bandwidth. When using internal acquisition mode with external clock frequency 2MHz, 100ksps throughput rate achieved. possible digitize high-speed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, anti-alias filtering recommended (MAX274/MAX275 continuous-time filters).
Input Range Protection
DGND
MAX196 MAX198
4.7µF REFADJ 0.01µF AGND
4.7µF
0.01µF OUTPUT STATUS
ANALOG INPUTS
DATA
Figure shows equivalent input circuit. fullscale input voltage depends voltage reference (VREF). MAX196 uses scaling factor, which allows input voltage ranges ±10V, ±5V, +10V, with 4.096V voltage reference (Table Program desired range setting appropriate control bits (D3, control byte (Tables MAX198 does scaling factor, input voltage range directly corresponds with reference voltage. programmed input voltages ±VREF, ±VREF/2, VREF, VREF/2 (Table When external reference applied REFADJ, voltage given VREF 1.6384 VREFADJ (2.4V VREF 4.18V). input channels overvoltage protected ±16.5V. This protection active even device power-down mode. Even with input resistive network provides current-limiting that adequately protects device.
Figure Operational Diagram
Digital Interface
Input data (control byte) output data multiplexed three-state parallel interface. This parallel easily interfaced with control write read operations. standard chip-select signal, which enables address MAX196/MAX198 port. When high, disables inputs forces interface into high-Z state.
BIPOLAR UNIPOLAR 5.12k HOLD TRACK TRACK CHOLD
VOLTAGE REFERENCE
HOLD
Table Full Scale Zero Scale (MAX196 only)
RANGE ZERO SCALE -FULL SCALE +FULL SCALE VREF 1.2207 VREF 2.4414
BIPOLAR/UNIPOLAR SWITCH 12.5k (MAX196) 5.12k (MAX198) INPUT SWITCH 8.67k (MAX196) (MAX198) SWITCH
-VREF 1.2207 VREF 1.2207 -VREF 2.4414 VREF 2.4414
Figure Equivalent Input Circuit
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
Table Control-Byte Format
(MSB) ACQMOD (LSB)
NAME PD1, ACQMOD
DESCRIPTION These bits select clock power-down modes (Table internally controlled acquisition clock cycles), externally controlled acquisition Selects full-scale voltage magnitude input (Table Selects unipolar bipolar conversion mode (Table These address bits input select "on" channel (Table
Table Range Polarity Selection
INPUT RANGE (MAX196) INPUT RANGE (MAX198) VREF/2 VREF ±VREF/2 ±VREF
Table Clock Power-Down Selection
DEVICE MODE Normal Operation External Clock Mode Normal Operation Internal Clock Mode Standby Power-Down (STBYPD); clock mode unaffected Full Power-Down (FULLPD); clock mode unaffected
Table Channel Selection
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
Input Format control byte latched into device, pins D7-D0, during write cycle. Table shows controlbyte format. Output Data Format output data format binary unipolar mode twos-complement binary bipolar mode. When reading output data, must low.
duration internally timed. Conversion starts when this six-clock-cycle acquisition interval (3µs with 2MHz) ends (see Figure
Start Conversion
Conversions initiated with write operation, which selects channel configures MAX196/ MAX198 either unipolar bipolar input range. write pulse either start acquisition interval initiate combined acquisition plus conversion. sampling interval occurs acquisition interval. ACQMOD input control byte offers options acquiring signal: internal external. conversion period lasts clock cycles either internal external clock acquisition mode. Writing control byte during conversion cycle will abort conversion start acquisition interval.
External Acquisition external acquisition timing mode precise control sampling aperture and/or independent control acquisition conversion times. user controls acquisition start-of-conversion with separate write pulses. first pulse, written with ACQMOD starts acquisition interval indeterminate length. second write pulse, written with ACQMOD terminates acquisition starts conversion WR's rising edge (Figure However, second control byte contains ACQMOD indefinite acquisition interval restarted. address bits input must have same values first second write pulses. Power-down mode bits (PD0, PD1) assume values second write pulse (see Power-Down Mode section).
Read Conversion
standard interrupt signal, INT, provided allow device flag when conversion ended valid result available. goes when conversion complete output data ready (Figures returns high first read cycle control byte written. tCSRH
Internal Acquisition Select internal acquisition writing control byte with ACQMOD cleared (ACQMOD This causes write pulse initiate acquisition interval whose
tCSRS tACQI
tCSWS
tCSWH
CONTROL BYTE
tCONV
D7-D0
ACQMOD ="0"
tINT1
HIGH-Z DOUT DATA VALID
HIGH-Z
Figure Conversion Timing Using Internal Acquisition Mode
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
tCSRS
tCSRH
tCSWS
tACQI tCSHW
tCONV
D7-D0
CONTROL BYTE ACQMOD
CONTROL BYTE ACQMOD
tINT1
DOUT DATA VALID
Figure Conversion Timing Using External Acquisition Mode
Clock Modes
MAX196/MAX198 operate with either internal external clock. Control bits (D6, select either internal external clock mode. Once desired clock mode selected, changing these bits program power-down will affect clock mode. each mode, internal external acquisition used. power-up, external clock mode selected.
INTERNAL CLOCK PERIOD (ns)
2000
1500
Internal Clock Mode Select internal clock mode free from burden running conversion clock. select this mode, write control byte with 100pF capacitor between ground sets this frequency 1.56MHz nominal. Figure shows linear relationship between internal clock period value external capacitor used. External Clock Mode Select external clock mode writing control byte with Figure shows timing relationships internal external acquisition modes, with external clock. 100kHz 2.0MHz external clock with duty cycle required proper operation. Operating clock frequencies lower than 100kHz will cause voltage droop across hold capacitor, subsequently degrade performance.
1000
CLOCK CAPACITANCE (pF)
Figure Internal Clock Period Clock Capacitance
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS
tCWS
ACQMOD GOES HIGH WHEN HIGH
tCWH
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
ACQMOD GOES HIGH WHEN
Figure External Clock Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
ACQMOD GOES HIGH WHEN HIGH ACQUISITION STARTS ACQUISITION ENDS
tCWS
ACQMOD
CONVERSION STARTS
ACQMOD GOES HIGH WHEN
tCWH
ACQMOD
Figure External Clock Timing (External Acquisition Mode)
Multirange, Single +5V, 12-Bit with 12-Bit Interface
_Applications Information
Power-On Reset
power-up, internal power-on reset circuitry sets high puts device normal operation/external clock mode. This state selected keep internal clock from loading external clock driver when part used external clock mode.
MAX196 MAX198
1.638 REFADJ 0.01µF 4.096V 4.7µF CREF
MAX196/MAX198
Internal External Reference
MAX196/MAX198 operate with either internal external reference. external reference connected either REFADJ (Figure input directly, disable internal buffer tying REFADJ VDD. Using REFADJ input eliminates need buffer reference externally. When reference applied REFADJ, bypass REFADJ with 0.01µF capacitor AGND. REFADJ internal buffer gain trimmed 1.6384 provide 4.096V from 2.5V reference.
2.5V
Figure Internal Reference
4.096V 4.7µF CREF
Internal Reference internally trimmed 2.50V reference gained through REFADJ buffer provide 4.096V REF. Bypass with 4.7µF capacitor AGND REFADJ with 0.01µF capacitor AGND. internal reference voltage adjustable ±1.5% (±65 LSBs) with reference-adjust circuit Figure External Reference REFADJ, input impedance minimum currents. During conversions, external reference must able deliver 400µA load currents, must have output impedance less. reference higher output impedance noisy, bypass close with 4.7µF capacitor AGND. With external reference voltage less than 4.096V less than 2.5V REFADJ pin, increase ratio noise value 4096) results performance degradation (loss effective bits).
MAX196 MAX198
1.638 REFADJ
2.5V
Figure External Reference, Reference
4.096V 4.7µF CREF
MAX196 MAX198
1.638 REFADJ
Power-Down Mode
save power, converter into lowcurrent shutdown mode between conversions. programmable power-down modes available: STBYPD FULLPD. Select STBYPD FULLPD programming input control byte. When power-down asserted, becomes effective only after conversion. power-down modes, interface remains active conversion
2.5V 0.01µF
2.5V
Figure external reference overdrives internal reference.
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
results read. Input overvoltage protection active power-down modes. device returns normal operation first falling edge during write operation. than fraction LSB), STBYPD power-down cycle prior starting conversions. Take into account that reference buffer recharges bypass capacitor 80mV/ms slew rate, 50µs settling time. Throughput rates 10ksps offer typical supply currents 470µA, using recommended 33µF capacitor value.
Choosing Power-Down Modes bandgap reference reference buffer remain active STBYPD mode, maintaining voltage 4.7µF capacitor pin. This "DC" state that does degrade after power-down duration. Therefore, sampling rate with this mode, without regard start-up delays. However, FULLPD mode, only bandgap reference active. Connect 33µF capacitor between AGND maintain reference voltage between conversions reduce transients when buffer enabled disabled. Throughput rates down 1ksps achieved without allotting extra acquisition time reference recovery prior conversion. This allows conversion begin immediately after power-down ends. discharge capacitor during FULLPD exceeds desired limits accuracy (less
Auto-Shutdown Selecting STBYPD every conversion automatically shuts MAX196/MAX198 down after each conversion without requiring start-up time next conversion.
Transfer Function
Output data coding MAX196/MAX198 binary unipolar mode with 1LSB 4096) twoscomplement binary bipolar mode with 1LSB |FS|) 4096]. Code transitions occur halfway between successive-integer values. Figures show input/output (I/O) transfer functions unipolar bipolar operations, respectively. full-scale (FS) values, refer Table
OUTPUT CODE FULL-SCALE TRANSITION
4096
OUTPUT CODE 011. 011.
4096
000. 000. 111.
INPUT VOLTAGE (LSB)
100. 100. 100. INPUT VOLTAGE (LSB)
Figure Unipolar Transfer Function
Figure Bipolar Transfer Function
Multirange, Single +5V, 12-Bit with 12-Bit Interface
Layout, Grounding, Bypassing
Careful printed circuit board layout essential best system performance. best performance, ground plane. reduce crosstalk noise injection, keep analog digital signals separate. Digital ground lines between digital signal lines minimize interference. Connect analog grounds DGND star configuration AGND. noise-free operation, ensure ground return from AGND supply ground impedance short possible. Connect logic grounds directly supply ground. Bypass with 0.1µF 4.7µF capacitors AGND minimize high- low-frequency fluctuations. supply excessively noisy, connect resistor between supply shown Figure
SUPPLY
MAX196/MAX198
4.7µF 0.1µF AGND DGND DGND
MAX196 MAX198
DIGITAL CIRCUITRY
OPTIONAL CONNECT AGND DGND WITH GROUND PLANE SHORT TRACE
Figure Power-Supply Grounding Connection
_Functional Diagram
REFADJ
SIGNAL CONDITIONING BLOCK OVERVOLTAGE TOLERANT
1.638
+2.5V REFERENCE
CHARGE REDISTRIBUTION 12-BIT COMP
CLOCK
SUCCESSIVEAPPROXIMATION REGISTER CONTROL LOGIC LATCHES THREE-STATE, BIDIRECTIONAL INTERFACE D0-D11 12-BIT DATA
MAX196 MAX198
AGND DGND
Multirange, Single +5V, 12-Bit with 12-Bit Interface MAX196/MAX198
_Ordering Information (continued)
PART MAX196BC/D MAX196AENI MAX196BENI MAX196AEWI MAX196BEWI MAX196AEAI MAX196BEAI MAX196AMYI MAX196BMYI MAX198ACNI MAX198BCNI MAX198ACWI MAX198BCWI MAX198ACAI MAX198BCAI MAX198BC/D MAX198AENI MAX198BENI MAX198AEWI MAX198BEWI MAX198AEAI MAX198BEAI MAX198AMYI MAX198BMYI TEMP. RANGE +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C PIN-PACKAGE Dice* Narrow Plastic Narrow Plastic Wide Wide SSOP SSOP Narrow Ceramic SB** Narrow Ceramic SB** Narrow Plastic Narrow Plastic Wide Wide SSOP SSOP Dice* Narrow Plastic Narrow Plastic Wide Wide SSOP SSOP Narrow Ceramic SB** Narrow Ceramic SB**
0.144" (3.659mm) AGND 0.231" (5.870mm) REFADJ
_Chip Topography
DGND
TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED
Dice specified +25°C, parameters only. Contact factory availability processing MIL-STD-883.
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 (408) 737-7600 1995 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

ATION EVALU ILABLE Multirange, Single +5V, 12-Bit with 12-Bit Int

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