Laser-Configured ASIC Family Laser-Configured ASIC (LASIC®) techn
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CL8452A
Laser-Configured ASIC Family
Laser-Configured ASIC (LASIC®) technology offers ultimate combination performance, flexibility, cost Functionally, architecturally, electrically compatible with industry-standard FLEX® 8000 series FPGAs High Density 4,000 Usable gates Flip-flops Maximum user pins Laser fuse technology provides very fast, dense interconnect routing Optional Instant-On configuration eliminates need external configuration EPROM Fabricated using micron CMOS process Very current consumption (active standby) Alpha particle immune
CL8000 Product Family Overview
Parameter
Available Gates Useable Gates Flip-flops Logic Elements user pins Packages
CL8282A
5,000 2,500 PLCC TQFP
CL8452A
8,000 4,000 PLCC TQFP PQFP
CL8636A
12,000 6,000 PLCC PQFP PQFP
CL8820A
16,000 8,000 TQFP PQFP PQFP
CL81188A
24,000 12,000 1,188 1,008 PQFP PQFP
December 2000
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CL8452A Laser-Configured ASIC
Description
Clear Logic CL8000 Laser-Configured ASIC (LASIC®) family offers ultimate combination performance, flexibility, cost. This family system level second source Altera FLEX® 8000 products. designs requiring in-system reprogrammability, design verification performed using programmable Altera devices, Clear Logic LASICs used cost, high volume production. Clear Logics innovative laser ASIC technology eliminates costs, test vector development, ordering minimums long lead times. re-simulation re-layout required, device engineered using cell-based, PLD-like architecture. Clear Logics TestCell technology ensures complete test coverage through specialized testing modes which transparent user. Clear Logic CL8000 Laser-Configured ASIC family based upon large array logic elements. Each logic element contains configurable look table combinatorial functions register sequential operations. group eight logic elements forms block. Laser-configured metal fuses implement logical functions control signal routing Laser configuration provides reduced cost enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, improved immunity noise upset events.
Configuration
Clear Logics CL8000 LASIC® family compatible with configuration modes defined FLEX® 8000 product family. These configuration modes include following: Active Serial Active Parallel Active Parallel Down Passive Parallel Synchronous Passive Parallel Asynchronous Passive Serial
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CL8452A Laser-Configured ASIC CL8000 already configured when shipped, configured bypass FLEX® 8000 configuration modes. This Instant-On configuration mode eliminates need external EPROMs microcode. Instant-On mode, CL8000 device begins Initialization immediately upon low-tohigh transition nCONFIG pin.
Additional Information
further information designing with CL8000 LASIC family, please refer following documents: AN-01: Requesting First Article. This document provides instructions submit bitstream file generation first articles. AN-02: Clear Logic Packaging Guide. This document provides specifications drawings packages used CL10K family other Clear Logic devices. AN-03: CL8000 System Configuration. This document contains detailed discussion aspects configuring CL8000-based systems. AN-04: CL8000 Technology White Paper. This document outlines technologies employed CL8000 LASIC family. AN-05: Calculating CL8000 Power Consumption. This document provides guidelines calculating power consumption based CL8000 design characteristics. AN-06: Eliminating Serial EPROM from FLEX 8000 Designs. This document outlines additional savings achieve removing EPROM from CL8000 LASIC family. AN-07: CL8000 Test Methodology. This document describes Clear Logic provides 100% stuck-at fault coverage. AN-08: CL8000 LASIC Timing Function Compatibility. This document shows seamless conversion from FPGA ASIC achieve with additional engineering achieved with Clear Logic. Page
CL8452A Laser-Configured ASIC
Block Diagram
MSEL0 MSEL1 nCONFIG CLKUSR nSTATUS DCLK CONF_DONE DATA7 DATA[0:6] RDCLK RDYnBUSY ADD[0:17] nTRST
Configuration Emulation Logic Array Size: LBBs Rows Columns)
User-Defined Input/Outputs
LBB: Logic Building Block IOE: Input/Output Element Dedicated Input
User-Defined Input/Outputs
8452A
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CL8452A Laser-Configured ASIC
Configuration
Name
MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE RDCLK RDYnBUSY CLKUSR ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6
PLCC
TQFP
PQFP
8452A
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CL8452A Laser-Configured ASIC
Configuration
Name
ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 TCLK nTRST Dedicated Inputs VCCINT Connect) Total user pins
PLCC
TQFP
PQFP
100, 121, 133, 147, 107, 108, 126, 140,
118, 119,
8452A
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CL8452A Laser-Configured ASIC
Electrical Specifications
Absolute Maximum Ratings
Symbol
IOUT TSTG TAMB Supply voltage input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias Under bias
Parameter
Conditions
-2.0 -2.0
Unit
Recommended Operating Conditions
Symbol
VCCINT
Parameter
Supply voltage, internal logic input buffers Commercial Grade Devices Industrial Grade Devices input voltage volt commercial volt industrial volt operation Input voltage Output voltage Operating temperature Commercial temperature range Industrial temperature range Input signal rise time Input signal fall time rise time
Conditions
4.75 4.50
5.25 5.50
Unit
VCCIO
4.75 4.50 3.00
5.25 5.50 3.60 VCCINT VCCIO
tRVCC
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CL8452A Laser-Configured ASIC
Electrical Specifications cont.
Electrical Characteristics (over operating range)
Symbol
ICC0
Parameter
Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Input Leakage Current Output Leakage Current Standby Current
Conditions
-0.3
Typ[3]
VCCINT
Unit
-4.0 VCCIO VCCIO[Min] 12.0 VCCIO VCCIO[Min] GND, load
0.45
Capacitance
Symbol
COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VOUT
Unit
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CL8452A Laser-Configured ASIC
Electrical Specifications
Element Timing Parameters
Symbol
tIOD tIOC tIOE tIOCO
Speed:
Speed:
Speed:
Parameter
register data delay register control signal delay Output enable delay register clock output delay
Conditions
Unit
tIOCOMB combinatorial delay tIOSU tIOH tIOCLR tOD1 register setup time before clock register hold time after clock register clear delay Input buffer delay Output buffer delay
Slow Slew Rate off, VCCIO 5.0v, Slow Slew Rate off, VCCIO 5.0v, Slow Slew Rate off, VCCIO 5.0v, Slow Slew Rate off, VCCIO 5.0v, Slow Slew Rate off, VCCIO 5.0v, Slow Slew Rate off, VCCIO 5.0v,
tOD2
Output buffer delay
tOD3 tZX1
Output buffer delay[6] Output buffer disable delay[6] Output buffer delay
tZX2
Output buffer delay[6]
tZX3
Output buffer delay[6]
External Timing Parameters[4]
Symbol
tDRR tODH
Speed:
Speed:
Speed
Parameter
Register register delay four LEs, three interconnects, four local interconnects Output data hold time after clock
Conditions
Unit
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CL8452A Laser-Configured ASIC
Electrical Specifications cont.
Logic Element Timing Parameters[5]
Symbol
tLUT tCLUT tRLUT tGATE tCASC tCICO tCGEN tCGENR tCOMB tPRE tCLR
Speed:
Speed:
Speed:
Parameter
Look table delay data-in Look table delay carry-in
Conditions
Unit
Look table delay register feedback Cascade gate delay Cascade chain routing delay Carry-in carry-out delay Data-in carry-out delay register feedback carry-out delay register control signal delay Clock high time Clock time register clock-to-output delay Combinatorial delay register setup time before clock register hold time after clock register preset delay register clear delay
Interconnect Timing Parameters[5]
Symbol Parameter Conditions
tLABCASC Cascade delay between different LABs tLABCARRY Carry delay between different LABs tLOCAL tROW tCOL tDIN_C tDIN_D tDIN_IO local interconnect delay interconnect routing delay Column interconnect routing delay Dedicated input control delay Dedicated input data delay Dedicated input control delay
Speed:
Speed:
Speed:
Unit
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CL8452A Laser-Configured ASIC
Test Conditions
VCCIO OUTPUT Includes capacitance VCCIO OUTPUT Includes capacitance
3.0V
Input Pulses
Test fixture set-up general testing. Test fixture set-up high testing (tZX#).
Notes Tables
During transitions, inputs undershoot -2.0V periods shorter than 20ns. Otherwise, minimum input voltage -0.3V. following devices have VCCIO pins: CL8282A, CL8452A. these devices, references VCCIO should changed VCCINT Typical values volts ambient temperature Guaranteed tested. Characterized initially, after design changes which affect these parameters. Internal timing delays based characterization, cannot explicitly tested. Internal timing parameters should used performance estimation only. Test Conditions set-up these parameters.
Revision History
Jan. 1998: Jul. 1999: Nov. 1999: Dec. 2000:
Created document Recompiled databook, 8820 package update. Remove reference 8282AV device which supported. Review reprint.
Ordering Information
Part Number
CL8452ALC84-4 CL8452ALC84-3 CL8452ATC100-4 CL8452ATC100-3 CL8452AQC160-4 CL8452AQC160-3 CL8452AQC160-2 CL8452ALI84-4 CL8452AQI160-3 Industrial 84-pin PLCC 160-pin PQFP 160-pin Plastic 100-pin Thin
Temperature Range
Commercial
Package Type
84-pin PLCC
Speed
Altera Equivalent
(slowest) EPF8452ALC84-4 (fastest) EPF8452ALC84-3 (slowest) EPF8452ATC100-4 (fastest) EPF8452ATC100-3 (slowest) EPF8452AQC160-4 EPF8452AQC160-3
(fastest) EPF8452AQC160-2 EPF8452ALI84-4 EPF8452AQI160-3
8452A
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CL8452A Laser-Configured ASIC
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