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CL10K200E

LIBERATOR

CL10K200E
Key Features
u Fully Compatible to the Altera® FLEX® 10KE Family u Prototype Your System With Altera FPGAs u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development u Very Fast, Dense Signal Routing Using Vertical Link Interconnect u "Gate Array" Option Eliminates Configuration EPROMs u Fabricated Using 0.25 Micron CMOS Process
LIBERATOR
CL10KE Product Family Overview
Parameter
Typical Gates (Logic and RAM) Maximum System Gates Logic Elements Embedded Array Blocks Total RAM Bits Max User I / O pins Speed Grades
CL10K30E
30, 000 119, 000 1, 728 6 24, 576 220 -1, -2, -3 144-pin TQFP 208-pin PQFP 256-pin FBGA 484-pin FBGA
u Very Low Power Consumption (Active And Standby) u High Density - 200, 000 Usable Gates - 9, 984 Logic Elements - 98, 304 RAM Bits - 470 Maximum User I / O Pins
CL10K50E CL10K50S
50, 000 199, 000 2, 880 10 40, 960 254 -1, -2, -3 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA
CL10K100E
100, 000 257, 000 4, 992 12 49, 152 338 -1, -2, -3 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA
CL10K200E CL10K200S
200, 000 513, 000 9, 984 24 98, 304 470 -1, -2, -3 240-pin PQFP 356-pin SBGA 484-pin FBGA 600-pin SBGA 672-pin FBGA
10KE tbl 01
Packages
January 2001
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LIBERATOR CL10K200E (PRELIMINARY)
Description
Configuration
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LIBERATOR CL10K200E (PRELIMINARY)
Additional Information
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LIBERATOR CL10K200E (PRELIMINARY)
Block Diagram
Embedded Array Block (EAB) I / O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE IOE Column Interconnect EAB
IOE IOE Logic Array Logic Building Block (LBB) IOE IOE Logic Element (LE)
IOE IOE
Row Interconnect Logic Array
EAB Local Interconnect
10KE drw 01
IOE IOE
Logical Memory Array (LMA)
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LIBERATOR CL10K200E (PRELIMINARY)
Pin Configuration
Pin Name
600-Pin SBGA
F5 C1 D32 D4 AP1 AM32 AE32 AN2 AP35 AR29 AM28 AL29 AN29 AG35 AM34 AM13 AR12 AN12 AP11 AM11 AR10 AN10 AM4 AN1 AN34
672-Pin FBGA
W6 Y6 AA21 V9 G7 H20 M21 G6 G21 G19 H19 F21 F20 M19 J20 G10 J9 F9 G9 H8 F7 G8 F6 H7 H21
10K200E tbl 01A
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LIBERATOR CL10K200E (PRELIMINARY)
Pin Configuration
Pin Name
600-Pin SBGA
AL31 C35 C34 C18, D18, AM18, AN18 AL18, E18 AR17 AR19 A11, A19, B1, D24, E2, F31, F35, H1, K32, M2, N34, P5, T35, U3, V32, Y2, AA33, AB5, AD35, AE4, AF32, AG5, AK31, AK35, AL3, AP24, AR11, AR18
672-Pin FBGA
G20 W20 Y21 Y13, U14, G14, K13 T13, F14 J13 H14 E13, E17, H2, H25, K16, L10, L12, L14, L17, M2, M25, N11, N12, N15, P12, P15, R14, T2, T10, T12, T17, T25, U16, Y7, AA23, AB10, AC14
VCCINT
VCCIO
A20, A27, C2, C3, C4, C8, C15, C23, C32, C8, C15, D7, G3, J3, J17, K11, K22, L13, L15, C33, D5, D31, E5, E12, E31, AL5, AL12, AM5, M11, M13, M16, M22, N16, P11, R5, R11, R13, AM19, AM26, AM31, AN3, AN4, AN8, AN15, R16, R22, T15, U3, U11, V5, V17, V24, Y2, AN32, AN33, AP34, AR23 Y24, AA26, AD15 B18 T14
GNDINT
A1, A2, A3, A4, A5, A31, A32, A33, A34, A35, A2, A25, B2, B25, C3, C10, C24, D3, D4, D19, B2, B3, B4, B5, B6, B31, B32, B33, B34, B35, D23, D24, E4, E23, G23, J5, J23, K4, K10, C5, C6, C30, C31, D6, D30, E6, E30, AL6, K17, L11, L16, L22, M5, M12, M14, M15, N13, AL30, AM6, AM30, AN5, AN6, AN30, AN31, N14, P13, P14, P22, R12, R15, T11, T16, U10, AN35, AP2, AP3, AP4, AP5, AP6, AP30, AP31, U17, U24, V3, Y5, AA22, AB23, AB4, AB5, AP32, AP33, AR1, AR2, AR3, AR4, AR5, AR30, AB23, AB24, AC3, AC8, AC24, AD13, AD18, AR31, AR32, AR33, AR34, AR35 AE2, AE25, AF2, AF25 A18 AA13 A4, A5, A6, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B16, B19, B20, B21, B22, B23, B24, C1, AE4, AE5, AE6, AE7, AE8, AE9, AE10, AE11, AE12, AE14, AE15, AE16, AE17, AE19, AE20, AE21, AE22, AE23, AF4, AF5, AF6, AF7, AF8, AF9, AF10, AF12, AF13, AF14, AF15, AF16, AF18, AF20, AF21, AF23, AF24
No Connect
Total user I / O Pins
10K200E tbl 01B
Page 6
LIBERATOR CL10K200E (PRELIMINARY)
DC Electrical Specifications
Absolute Maximum Ratings
Symbol
VCC VI IOUT TSTG TAMB TJ Supply Voltage DC Input Voltage 1 DC Output Current, per Pin Storage Temperature Ambient Temperature Junction Temperature No Bias Under Bias Under Bias
Parameter
Conditions
10KE tbl 02
Recommended Operating Conditions
Symbol
VCCINT
Parameter
Supply Voltage, Internal Logic and Input Buffers Commercial Grade Devices Industrial Grade Devices DC Input Voltage for 3.3V Operation Commercial Grade Devices Industrial Grade Devices DC Input Voltage for 2.5V Operation Commercial Grade Devices Industrial Grade Devices Input Voltage Output Voltage Operating Temperature Commercial Temperature Range Industrial Temperature Range Input Signal Rise Time Input Signal Fall Time
Conditions
VCCIO
2.70 2.70 5.75 VCCIO 70 85 40 40
10KE tbl 03A
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LIBERATOR CL10K200E (PRELIMINARY)
DC Electrical Specifications cont.
DC Electrical Characteristics (over the operating range)
Symbol
VIH VIL
Parameter
Input HIGH Voltage Input LOW Voltage 3.3-V High-Level TTL Output Voltage 3.3-V High-Level CMOS Output Voltage 3.3-V High-Level PCI Output Voltage
Conditions
Lower of 1.7 or 0.5 x VCCINT -0.5
5.75 0.3 x VCCIO
2.4 VCCIO-0.2 0.9 x VCCIO 2.1 2.0 1.7 0.45 0.2 0.1 x VCCIO 0.2 0.4 0.7 -10 -10 5
10KE tbl 04
2.5-V High-Level Output Voltage
3.3-V Low-Level TTL Output Voltage 3.3-V Low-Level CMOS Output Voltage 3.3-V Low-Level PCI Output Voltage
2.5-V Low-Level Output Voltage
IIN IOZ ICC0
Input Leakage Current Output Leakage Current Standby Current
Capacitance4
Symbol
C IN COUT
Parameter
Input Capacitance Output Capacitance
Conditions
10KE tbl 05
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LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications
I / O Element Timing Parameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX tZX1
Speed: -1
Speed: -2
Speed: -3
Parameter
tZX3 tINREG tIOFD tINCOMB
IOE Input Pad and Buffer to IOE Register Delay IOE Register Feedback Delay IOE Input Pad and Buffer to Interconnect Delay
10KE tbl 06B
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LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications cont.
External Timing Parameters4
Symbol
tDRR Speed: -1 Speed: -2 Speed: -3
Parameter
Register to Register Delay via Four LEs, Three Row Interconnects, and Four Local Interconnects Setup Time with Global Clock at IOE Register Hold time with Global Clock at IOE Register Output Data Hold Time After Clock
tINSU tINH tOUTCO
10KE tbl 07D
Logic Element Timing Parameters5
Speed: -1 Speed: -2 Speed: -3
Symbol
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Parameter
Look-up Table Delay for Data-in Look-up Table Delay for Carry-in Look-up Table Delay for LE Register Feedback Data-in to Packed Register Delay LE Register Enable Delay Carry-in to Carry-out Delay Data-in to Carry-out Delay LE Register Feedback to Carry-out Delay Cascade Chain Routing Ddelay LE Register Control Signal Delay LE Register Clock-to-output Delay Combinatorial Delay LE Register Setup Time Before Clock LE Register Hold Time After Clock LE Register Preset Delay LE Register Clear Delay Clock High Time Clock Low Time
10KE tbl 08B
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LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications cont.
Interconnect Timing Parameters5
Speed: -1 Speed: -2 Speed: -3
Symbol
tDIN2IOE tDIN2LE tDIN2DATA
Parameter
Delay from Dedicated Input Pin to IOE Control Input Delay from Dedicated Input Pin to LE or EAB Control Input Delay from Dedicated Input or Clock Pin to LE or EAB Data
tDCLK2IOE Delay from Dedicated Clock Pin to IOE Clock tDCLK2LE tSAMELAB Delay from Dedicated Clock Pin to LE or EAB Clock Delay from an LE to LE in Same LAB Delay for Driving a Row IOE, LE or EAB to a Row IOE, LE or EAB in the Same Row Delay from an LE to IOE in the Same Column Delay for Driving a Column IOE, LE or EAB to an LE or EAB in a Different Row Delay for Driving a Row IOE or EAB to an LE or EAB in a Different Row Delay from an LE to IOE Control Signal via the Peripheral Dontol Bus Delay from an LE Carry-out Signal to an LE Carry-in Signal in a Different LAB Delay from an LE Cascade-out Signal to an LE Cascade-in Signal in a Different LAB
tSAMEROW
tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY
tLABCASC
10KE tbl 09D
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LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications cont.
EAB Timing Parameters5
Speed: -1 Speed: -2 Speed: -3
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO
Parameter
Delay from Data or Address to EAB for Combinatorial Input Delay from Data or Address to EAB for Registered Input WE Delay to EAB for Combinatorial Input WE Delay to EAB for Registered Input EAB Register Clock Delay EAB Register Clock-to-output Delay
tEABBYPASS Bypass Register Delay tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL EAB Register Setup Time EAB Register Hold Time Address Access Delay Write Pulse Width Data Setup Time Before Falling Edge of Write Pulse Data Hold Time After Falling Edge of Write Pulse Address Setup Time Before Rising Edge of Write Pulse Address Hold After Falling Edge of Write Pulse Write Enable to Date Output Delay Data-in to Date-out Delay Data-out Delay Clock High Time Clock Low Time 1.5 1.5 3.3 0.9 0.1 1.3 2.1 0.9 0.4
10KE tbl 10B
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LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications cont.
EAB Timing Parameters5
Speed: -1 Speed: -2 Speed: -3
Symbol
tEABAA
Parameter
EAB Address Access Delay
tEABRCCOMB EAB Asynchronous Read Cycle Time tEABRCREG EAB Synchronous Read Cycle Time tEABWP EAB Write Pulse Width
tEABWCCOMB EAB Asynchronous Write Cycle Time tEABWCREG EAB Synchronous Write Cycle Time tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWESH EAB Data-in to Data-out Delay EAB Clock-to-output Delay Using Output Registers EAB Data / Address Setup Time Using Input Register EAB Data / Address Hold Time Using Input Register EAB WE Setup When Using Input Register EAB WE Hold Time When Using Input Register EAB Data Setup Time to Falling Edge of Write Pulse When Not Using Input Registers EAB Data Hold Time After Falling Edge of Write Pulse When Not Using Input Registers EAB Address Setup Time to Rising Edge of Write Pulse When Not Using Input Registers EAB Address Hold Time After Falling Edge of Write Pulse When Not Using Input Registers EAB WE to Data Output Delay
tEABWDSU
tEABWDH
tEABWASU
tEABWAH tEABWO
10KE tbl 11B
Page 13
LIBERATOR CL10K200E (PRELIMINARY)
AC Electrical Specifications cont.
External Bidirectional Timing Parameters5
Speed: -1 Speed: -2 Speed: -3
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Parameter
10KE tbl 12A
AC Test Conditions
VCCIO OUTPUT Includes jig capacitance 35 pF 481 481
VCCIO OUTPUT Includes jig capacitance 5 pF
All Input Pulses
10KE drw 02
A: Test fixture set-up A is for general testing. B: Test fixture set-up B is for high Z testing (tZX#).
Notes to Tables
Revision History
02 Dec. 2000:
Created new document
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LIBERATOR CL10K200E (PRELIMINARY)
Ordering Information
Part Number
CL10K200EBC600-3 CL10K200EBC600-2 CL10K200EBC600-1 CL10K200EBI600-2 CL10K200EFC672-3 CL10K200EFC672-2 CL10K200EFC672-1 Industrial Commercial 672-pin FBGA
Temperature Range
Commercial
Package Type
600-pin SBGA
Speed
Altera Equivalent
EPF10K200EBC600-3 EPF10K200EBC600-2 EPF10K200EBC600-1 EPF10K200EBI600-2 EPF10K200EFC672-3 EPF10K200EFC672-2 EPF10K200EFC672-1
10K200E tbl 02A
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LIBERATOR CL10K200E (PRELIMINARY)
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