400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit AD

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400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit AD

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19-1684; 5/00
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281 12-bit ADCs combine 8-channel analog-input multiplexer, high-bandwidth track/hold, serial interface with high conversion speed power consumption. MAX1280 operates from single +4.5V +5.5V supply; MAX1281 operates from single +2.7V +3.6V supply. Both devices' analog inputs software configurable unipolar/bipolar singleended/pseudo-differential operation. 4-wire serial interface connects directly SPITM/QSPITM/MICROWIREdevices without external logic. serial strobe output allows direct connection TMS320-family digital signal processors. MAX1280/ MAX1281 external serial-interface clock perform successive-approximation analog-to-digital conversions. Both parts feature internal +2.5V reference reference-buffer amplifier with ±1.5% voltageadjustment range. external reference with VDD1 range also used. MAX1280/MAX1281 provide hard-wired SHDN four software-selectable power modes (normal operation, reduced power, fast power-down, full power-down). These devices programmed automatically shut down conversion operate with reduced power. When using powerdown modes, accessing serial interface automatically powers devices, quick turn-on time allows them powered down between conversions. This technique supply current under 100µA reduced sampling rates. MAX1280/MAX1281 available 20-pin TSSOP packages. These devices higher-speed versions MAX146/MAX147 (for more information, respective data sheet).
Features
8-Channel Single-Ended 4-Channel Pseudo-Differential Inputs Internal Multiplexer Track/Hold Single-Supply Operation +4.5V +5.5V (MAX1280) +2.7V +3.6V (MAX1281) Internal +2.5V Reference 400ksps Sampling Rate (MAX1280) Power 2.5mA (400ksps) 1.3mA (Reduced-Power Mode) 0.9mA (Fast Power-Down Mode) (Full Power-Down) 4-Wire Serial Interface Software-Configurable Unipolar Bipolar Inputs 20-Pin TSSOP Package
MAX1280/MAX1281
Ordering Information
PART MAX1280BCUP MAX1280BEUP TEMP. RANGE +70°C -40°C +85°C PINPACKAGE TSSOP TSSOP (LSB)
Ordering Information continued data sheet.
Configuration
VIEW
VDD1 VDD2 SCLK
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Digitizers Process Control
MAX1280 MAX1281
SSTRB DOUT REFADJ
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
SHDN
TSSOP
Maxim Integrated Products
free samples latest literature, visit www.maxim-ic.com phone 1-800-998-8800. small orders, phone 1-800-835-8769.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ABSOLUTE MAXIMUM RATINGS
VDD_ -0.3V VDD1 VDD2 -0.3V +0.3V CH0-CH7, GND. -0.3V (VDD1 0.3V) REF, REFADJ -0.3V (VDD1 0.3V) Digital Inputs -0.3V Digital Outputs -0.3V (VDD2 0.3V) Digital Output Sink Current .25mA Continuous Power Dissipation +70°C) 20-Pin TSSOP (derate 7.0mW/°C above +70°C) .559mW Operating Temperature Ranges MAX128_BCUP +70°C MAX128_BEUP -40°C +85°C Storage Temperature Range -60°C +150°C Lead Temperature (soldering, 10s) +300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS-MAX1280
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching ±0.8 ±0.1 missing codes over temperature ±1.0 ±1.0 ±6.0 ±6.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle fSCLK tCONV tACQ SINAD SFDR fIN1 99kHz, fIN2 102kHz 200kHz, 2.5Vp-p -3dB point SINAD 68dB harmonic
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS-MAX1280 (continued)
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER SYMBOL CONDITIONS Unipolar, VCOM VCH_ Bipolar, VCOM VCH_ VREF/2, referenced On/off leakage current, VCH_ VDD1 ±0.001 VREF +25°C 2.480 2.500 VREF output load 0.01 1.22 small adjustments, from 1.22V power down internal reference 2.05 VDD1 50mV VDD2 ISINK ISOURCE ±100 VDD1 2.520 VREF ±VREF/2 ppm/°C mV/mA UNITS ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, SingleEnded Differential (Note Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Temperature Coefficient Load Regulation (Note Capacitive Bypass Capacitive Bypass REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (Reference buffer disabled, reference applied REF) Input Voltage Range (Note VREF 2.500V, fSCLK 6.4MHz Input Current DIGITAL INPUTS (DIN, SCLK, SHDN) Input High Voltage Input Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance COUT VINH VINL VHYST VREF 2.500V, fSCLK power-down, fSCLK
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ELECTRICAL CHARACTERISTICS-MAX1280 (continued)
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER POWER SUPPLY Positive Supply Voltage (Note VDD1, VDD2 Operating mode (Note Supply Current Supply Current Power-Supply Rejection IVDD1 IVDD2 VDD1 VDD2 5.5V Reduced-power mode (Note Fast power-down (Note Full power-down (Note VDD1 VDD2 ±10%, midscale input ±0.5 ±2.0 SYMBOL CONDITIONS UNITS
ELECTRICAL CHARACTERISTICS-MAX1281
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain-Error Temperature Coefficient Channel-to-Channel OffsetError Matching ±1.6 ±0.2 missing codes over temperature ±1.0 ±1.0 ±6.0 ±6.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note Full-Power Bandwidth Full-Linear Bandwidth SINAD SFDR fIN1 73kHz, fIN2 77kHz 150kHz, 2.5Vp-p -3dB point SINAD 68dB harmonic
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS-MAX1281 (continued)
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, SingleEnded Differential (Note Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Temperature Coefficient Load Regulation (Note Capacitive Bypass Capacitive Bypass REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (Reference buffer disabled, reference applied REF) Input Voltage Range (Note VREF 2.500V, fSCLK 4.8MHz Input Current DIGITAL INPUTS (DIN, SCLK, SHDN) Input High Voltage Input Voltage Input Hysteresis Input Leakage Input Capacitance VINH VINL VHYST VDD2 VREF 2.500V, fSCLK power-down, fSCLK VDD1 50mV small adjustments, from 1.22V power down internal reference 2.05 VREF 0.75mA output load 0.01 1.22 ±100 VDD1 VREF +25°C 2.480 2.500 2.520 ppm/°C mV/mA Unipolar, VCOM VCH_ Bipolar, VCOM VCH_ VREF/2, referenced On/off leakage current, VCH_ AVDD ±0.001 VREF ±VREF/2 fSCLK Normal operating mode tCONV tACQ Normal operating mode Normal operating mode SYMBOL CONDITIONS UNITS
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ELECTRICAL CHARACTERISTICS-MAX1281 (continued)
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note VDD1, VDD2 Operating mode (Note Supply Current IVDD1 IVDD2 Reduced-power mode (Note VDD1 VDD2 3.6V Fast power-down (Note Full power-down (Note VDD1 VDD2 2.7V 3.6V, midscale input ±0.5 ±2.0 SYMBOL COUT ISINK ISOURCE 0.5mA VDD2 0.5V CONDITIONS UNITS DIGITAL OUTPUTS (DOUT, SSTRB)
Power-Supply Rejection
TIMING CHARACTERISTICS-MAX1280
(Figures VDD1 VDD2 +4.5V +5.5V; TMIN TMAX; unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width SCLK Setup SCLK Hold Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall Ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise SSTRB Hold SCLK Rise DOUT Valid SCLK Rise SSTRB Valid Rise DOUT Disable Rise SSTRB Disable Fall DOUT Enable Fall SSTRB Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS-MAX1281
(Figures VDD1 VDD2 +2.7V +3.6V; TMIN TMAX; unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width SCLK Setup SCLK Hold Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise SSTRB Hold SCLK Rise DOUT Valid SCLK Rise SSTRB Valid Rise DOUT Disable Rise SSTRB Disable Fall DOUT Enable Fall SSTRB Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
MAX1280/MAX1281
Note MAX1280 tested VDD1 VDD2 +5V, MAX1281 tested VDD1 VDD2 +3V; GND; unipolar single-ended input mode. Note Relative accuracy deviation analog value code from theoretical value after gain error offset error have been nulled. Note Offset nulled. Note Ground "on" channel; sine wave applied "off" channels. Note Conversion time defined number clock cycles multiplied clock period; clock duty cycle. Note absolute voltage range analog inputs (CH7-CH0, COM) from VDD1. Note External load should change during conversion specified accuracy. Guaranteed specification 2mV/mA result production test limitations. Note performance limited converter's noise floor, typically 300µVp-p. Note Electrical characteristics guaranteed from VDD1(MIN) VDD2(MIN) VDD1(MAX) VDD2(MAX). operations beyond this range, Typical Operating Characteristics. guaranteed specifications beyond limits, contact factory. Note midscale. Unipolar mode. MAX1280 tested with 20pF DOUT, 20pF SSTRB, fSCLK 6.4MHz, MAX1281 tested with same loads, fSCLK 4.8MHz, DOUT hex. Note SCLK GND, VDD1.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Typical Operating Characteristics
(MAX1280: VDD1 VDD2 5.0V, fSCLK 6.4MHz; MAX1281: VDD1 VDD2 3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, 0.01µF capacitor REFADJ, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1280/1-01
DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1280/1-02
SUPPLY CURRENT SUPPLY VOLTAGE (CONVERTING)
MAX1280/1-03
(LSB) -0.2
(LSB)
-0.1 -0.2 -0.3 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE
SUPPLY CURRENT (mA) 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE
-0.4 -0.6 SUPPLY VOLTAGE
SUPPLY CURRENT TEMPERATURE
MAX1280/1-04
SUPPLY CURRENT SUPPLY VOLTAGE (STATIC)
MAX1280/1-05
SUPPLY CURRENT TEMPERATURE (STATIC)
MAX1280/1-06
SUPPLY CURRENT (mA) MAX1281 MAX1280
NORMAL OPERATION (PD1
MAX1280 (PD1 MAX1281 (PD1 MAX1280 (PD1 MAX1281 (PD1
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
REDP (PD1
FASTDP (PD1
MAX1280 (PD1 MAX1281 (PD1
TEMPERATURE (°C) SUPPLY VOLTAGE
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE
MAX1280/1-07
SHUTDOWN SUPPLY CURRENT TEMPERATURE
MAX1280/1-08
REFERENCE VOLTAGE SUPPLY VOLTAGE
MAX1280/1-09
(PD1 SHUTDOWN CURRENT (µA)
(PD1 SHUTDOWN CURRENT (µA) MAX1280
2.5005
2.5003 REFERENCE VOLTAGE
MAX1281
2.5001
2.4999
2.4997
SUPPLY VOLTAGE
TEMPERATURE (°C)
2.4995 SUPPLY VOLTAGE
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1280: VDD1 VDD2 5.0V, fSCLK 6.4MHz; MAX1281: VDD1 VDD2 3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, 0.01µF capacitor REFADJ, +25°C, unless otherwise noted.)
REFERENCE VOLTAGE TEMPERATURE
MAX1280/1-10
MAX1280/MAX1281
OFFSET ERROR SUPPLY VOLTAGE
MAX1280/1-11
OFFSET ERROR TEMPERATURE
MAX1280/1-12
2.5002 2.5000 MAX1280 REFERENCE VOLTAGE 2.4998 2.4996 2.4994 2.4992 MAX1281
OFFSET ERROR (LSB) -0.5 -1.0 -1.5 -2.0 -2.5
-0.5 OFFSET ERROR (LSB)
-1.0
-1.5
-2.0 2.4990 2.4988 TEMPERATURE (°C) -2.5
TEMPERATURE (°C)
GAIN ERROR SUPPLY VOLTAGE
MAX1280/1-13
GAIN ERROR TEMPERATURE
MAX1281 GAIN ERROR (LSB)
MAX1280/1-14
GAIN ERROR (LSB) -0.5
-1.0
-1.5
-2.0 TEMPERATURE (°C)
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Description
NAME CH0-CH7 SHDN Sampling Analog Inputs Ground Reference Analog Inputs. sets zero-code voltage single-ended mode. Must stable ±0.5LSB. Active-Low Shutdown Input. Pulling SHDN shuts down device, reducing supply current (typ). Reference-Buffer Output/ADC Reference Input. Reference voltage analog-to-digital conversion. internal reference mode, reference buffer provides +2.500V nominal output, externally adjustable REFADJ. external reference mode, disable internal buffer pulling REFADJ VDD1. Input Reference-Buffer Amplifier. disable reference-buffer amplifier, REFADJ VDD1. Analog Digital Ground Serial Data Output. Data clocked SCLK's rising edge. High impedance when high. Serial Strobe Output. SSTRB pulses high clock period before decision. High impedance when high. Serial Data Input. Data clocked SCLK's rising edge. Active-Low Chip Select. Data will clocked into unless low. When high, DOUT SSTRB high impedance. Serial Clock Input. Clocks data serial interface sets conversion speed. (Duty cycle must 60%.) Positive Supply Voltage Positive Supply Voltage FUNCTION
REFADJ DOUT SSTRB SCLK VDD2 VDD1
VDD2
VDD2 DOUT CLOAD 20pF High-Z DOUT CLOAD 20pF High-Z
DOUT CLOAD 20pF High-Z
DOUT
CLOAD 20pF High-Z
Figure Load Circuits Enable Time
Figure Load Circuits Disable Time
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Detailed Description
MAX1280/MAX1281 analog-to-digital converters (ADCs) successive-approximation conversion technique input track/hold (T/H) circuitry convert analog signal 12-bit digital output. flexible serial interface provides easy interface microprocessors (µPs). Figure shows functional diagram MAX1280/MAX1281. order maintain ±0.5LSB accuracy. Assuming sinusoidal signal IN-, input voltage determined VIN- sin(2ft) maximum voltage variation determined dIN1LSB VREF VIN- CONV CONV
MAX1280/MAX1281
Pseudo-Differential Input
equivalent input circuit Figure shows MAX1280/MAX1281's input architecture, which composed T/H, input multiplexer, input comparator, switched-capacitor DAC, reference. single-ended mode, positive input (IN+) connected selected input channel negative input (IN-) COM. differential mode, selected from following pairs: CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7. Configure channels according Tables MAX1280/MAX1281 input configuration pseudodifferential that only signal sampled. return side (IN-) connected sampling capacitor while converting must remain stable within ±0.5LSB (±0.1LSB best results) with respect during conversion. varying signal applied selected IN-, amplitude frequency must limited maintain accuracy. following equations determine relationship between maximum signal amplitude frequency
650mVp-p 60Hz signal will generate ±0.5LSB error when using +2.5V reference voltage 2.5µs conversion time (15/fSCLK). When reference voltage used IN-, connect 0.1µF capacitor minimize noise input. During acquisition interval, channel selected positive input (IN+) charges capacitor CHOLD. acquisition interval spans three SCLK cycles ends falling SCLK edge after last input control word been entered. acquisition interval, switch opens, retaining charge CHOLD sample signal IN+. conversion interval begins with input multiplexer switching CHOLD from IN-. This unbalances node ZERO comparator's input. capacitive adjusts during remainder conversion cycle restore node ZERO within limits 12-bit resolution. This action equivalent transferring 12pF (VIN+ VIN-) charge from CHOLD binaryweighted capacitive DAC, which turn forms digital representation analog input signal.
SCLK SHDN
+1.22V REFERENCE INPUT SHIFT REGISTER CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT CLOCK 12-BIT 2.05* DOUT SSTRB
+2.500V VDD1 VDD2
CAPACITATIVE CHOLD 12pF
INPUT
ZERO
COMPARATOR
CSWITCH* HOLD
TRACK SAMPLING INSTANT, INPUT SWITCHES FROM SELECTED CHANNEL SELECTED CHANNEL. VDD1/2
REFADJ
MAX1280 MAX1281
SINGLE-ENDED MODE: CH0-CH7, COM. PSEUDO-DIFFERENTIAL MODE: SELECTED FROM PAIRS CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7. *INCLUDES INPUT PARASITICS
Figure Functional Diagram
Figure Equivalent Input Circuit
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Track/Hold
enters tracking mode falling clock edge after fifth 8-bit control word been shifted enters hold mode falling clock edge after eighth control word been shifted converter single-ended inputs, connected converter converts input. converter differential inputs, difference [(IN+) (IN-)] converted. conversion, positive input connects back CHOLD charges input signal. time required acquire input signal function quickly input capacitance charged. input signal's source impedance high, acquisition time lengthens, more time must allowed between conversions. acquisition time, tACQ, maximum time device takes acquire signal also minimum time needed signal acquired. calculated following equation: tACQ RIN) 12pF where 800, source impedance input signal; tACQ never less than 468ns (MAX1280) 625ns (MAX1281). Note that source impedances below significantly affect ADC's performance.
Input Bandwidth
ADC's input tracking circuitry 6MHz (MAX1280) 3MHz (MAX1281) small-signal bandwidth, possible digitize high-speed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, antialias filtering recommended.
Analog Input Protection
Internal protection diodes, which clamp analog input VDD1 GND, allow channel input pins swing from 0.3V VDD1 0.3V without damage. However, accurate conversions near full scale, inputs must exceed VDD1 more than 50mV lower than 50mV. analog input exceeds 50mV beyond supplies, allow input current exceed 2mA.
Quick Look
quickly evaluate MAX1280/MAX1281's analog performance, circuit Figure MAX1280/ MAX1281 require control byte written before each conversion. Connecting VDD2 feeds control bytes (HEX), which trigger singleended unipolar conversions without powering down between conversions. SSTRB output pulses
OSCILLOSCOPE
2.500V ANALOG INPUT 0.01µF
MAX1280 MAX1281
VDD1 VDD2
0.1µF 10µF
SCLK
SSTRB DOUT* VDD2 EXTERNAL CLOCK
REFADJ 0.01µF 2.5V 4.7µF
SCLK DOUT SSTRB SHDN VDD2
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT $FFF (HEX)
Figure Quick-Look Circuit
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
tACQ SCLK
UNI/ SGL/ START
SSTRB
HIGH-Z
HIGH-Z
HIGH-Z DOUT ACQUISITION IDLE
HIGH-Z
IDLE
CONVERSION
Figure Single-Conversion Timing
high clock period before 12-bit conversion result shifted DOUT. Varying analog input will alter sequence bits from DOUT. total clock cycles required conversion. transitions SSTRB DOUT outputs typically occur 20ns after rising edge SCLK.
clock frequency from 500kHz 6.4MHz (MAX1280) 4.8MHz (MAX1281). control byte call TB1. should format 1XXXXXXX binary, where denote particular channel, selected conversion mode, power mode. general-purpose line pull low. Transmit and, simultaneously, receive byte call RB1. Ignore RB1. Transmit byte zeros ($00 hex) and, simultaneously, receive byte RB2. Transmit byte zeros ($00 hex) and, simultaneously, receive byte RB3. Pull high. Figure shows timing this sequence. Bytes contain result conversion, padded with three leading zeros trailing zero. total conversion time function serial-clock frequency amount idle time between 8-bit transfers. avoid excessive droop, make sure total conversion time does exceed 120µs. Digital Output unipolar input mode, output straight binary (Figure 14). bipolar input mode, output two's complement (Figure 15). Data clocked rising edge SCLK MSB-first format.
Starting Conversion
Start conversion clocking control byte into DIN. With low, each rising edge SCLK clocks from into MAX1280/MAX1281's internal shift register. After falls, first arriving logic defines control byte's MSB. Until this first "start" arrives, number logic bits clocked into with effect. Table shows control-byte format. MAX1280/MAX1281 compatible with SPI/QSPI MICROWIRE devices. SPI, select correct clock polarity sampling edge control registers: CPOL CPHA MICROWIRE, SPI, QSPI transmit byte receive byte same time. Using Typical Operating Circuit, simplest software interface requires only three 8-bit transfers perform conversion (one 8-bit transfer configure ADC, more 8-bit transfers clock 12-bit conversion result). Figure MAX1280/MAX1281 QSPI connections. Simple Software Interface Make sure CPU's serial interface runs master mode, generates serial clock. Choose
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Table Control-Byte Format
(MSB) START (MSB) SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP SEL1 SEL0 UNI/BIP DESCRIPTION first logic after goes defines beginning control byte. These three bits select which eight channels used conversion (Tables SGL/DIF (LSB)
unipolar, bipolar. Selects unipolar bipolar conversion mode. unipolar mode, analog input signal from VREF converted; bipolar mode, differential signal range from -VREF/2 +VREF/2. single ended, differential. Selects single-ended differential conversions. singleended mode, input signal voltages referred COM. differential mode, voltage difference between channels measured (Tables Select operating mode. Mode Full power-down Fast power-down Reduced Power Normal Operation
SGL/DIF
(LSB)
Table Channel Selection Single-Ended Mode (SGL/DIF
SEL2 SEL1 SEL0
Table Channel Selection Psuedo-Differential Mode (SGL/DIF
SEL2 SEL1 SEL0
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
tCSW tCSS tCSO SCLK tDOH tDOV tDOE DOUT tSTH tSTV tDOD tCSH tCS1
tSTE SSTRB
tSTD
Figure Detailed Serial-Interface Timing
Serial Clock external serial clock only shifts data out, also drives analog-to-digital conversion steps. SSTRB pulses high clock period after last control byte. Successive-approximation decisions made appear DOUT each next SCLK falling edges (Figure SSTRB DOUT into high-impedance state when goes high; after next rising edge, SSTRB outputs logic low. Figure shows detailed serial-interface timing. conversion must complete 120µs less, droop sample-and-hold capacitors degrade conversion results. Data Framing falling edge does start conversion. first logic high clocked into interpreted start defines first control byte. conversion starts SCLK's falling edge after eighth control byte (the bit) clocked into DIN. start defined follows: first high clocked into with time converter idle, e.g., after VDD1 VDD2 applied. first high clocked into after conversion progress clocked onto DOUT pin. Once start been recognized, current conversion only terminated pulling SHDN low.
fastest MAX1280/MAX1281 with held between conversions clocks conversion. Figure shows serial-interface timing necessary perform conversion every SCLK cycles. tied SCLK continuous, guarantee start first clocking zeros.
Applications Information
Power-On Reset
When power first applied, SHDN pulled low, internal power-on reset circuitry activates MAX1280/MAX1281 normal operating mode, ready convert with SSTRB low. MAX1280/MAX1281 require 10µs reset after power supplies stabilize; conversions should initiated during this time. low, first logic interpreted start bit. Until conversion takes place, DOUT shifts zeros. Additionally, wait reference stabilize when using internal reference.
Power Modes
save power placing converter low-current operating modes full powerdown between conversions. Select power mode through control byte (Tables force converter into hardware shutdown driving SHDN GND. software power-down modes take effect after conversion completed; SHDN overrides software power mode immediately stops conversion
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
CONTROL BYTE
CONTROL BYTE
CONTROL BYTE
SCLK
DOUT
HIGH-Z
CONVERSION RESULT
CONVERSION RESULT
SSTRB
HIGH-Z
Figure Continuous 16-Clock/Conversion Timing
Table Software-Controlled Power Modes
TOTAL SUPPLY CURRENT PD1/PD0 MODE CONVERTING Full Power-Down (FULLPD) Fast Power-Down (FASTPD) Reduced-Power Mode (REDPD) Operating Mode 2.5mA 2.5mA 2.5mA 2.5mA AFTER CONVERSION 0.9mA 1.3mA 2.0mA CIRCUIT SECTIONS* INPUT COMPARATOR Reduced Power Reduced Power Full Power REFERENCE
*Circuit operation between conversions; during conversion, circuits fully powered
progress. software power-down mode, serial interface remains active, waiting control byte start conversion switch full-power mode. Once conversion completed, device goes into programmed power mode until control byte written. power-up delay dependent power-down state. Software low-power modes will able start conversion immediately when running decreased clock rates (see Power-Down Sequencing). During power-on reset, when exiting software full power-down mode exiting hardware shutdown, device goes immediately into full-power mode ready convert after when using external reference. When using internal reference, wait typical power16
delay from full power-down (software hardware), shown Figure Software Power-Down Software power-down activated using bits control byte. When software shutdown asserted, completes conversion progress powers down into specified lowquiescent-current state (2µA, 0.9mA, 1.3mA). first logic interpreted start puts MAX1280/MAX1281 into their full-power mode. Following start bit, data input word control byte also determines next power-down state. example, word contains 0.9mA power-down starts after conversion.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Table details four power modes with corresponding supply current operating sections. data rates achievable software power-down modes, Power-Down Sequencing. Hardware Power-Down Pulling SHDN places converter hardware power-down. Unlike software power-down mode, conversion terminated immediately. When returning normal operation from SHDN with external reference, MAX1280/MAX1281 considered fully powered-up within actively pulling SHDN high. When using internal reference, conversion should initiated only after reference settled; recovery time depends external bypass capacitors shutdown duration. less than maximum sample rates. Figures show average supply current function sampling rate. Using Full Power-Down Mode Full power-down mode (FULLPD) achieves lowest power consumption 1000 conversions channel second. Figure shows MAX1281's power consumption 8-channel conversions using full power-down mode (PD1 with internal reference maximum clock speed. 0.01µF bypass capacitor plus internal reference resistor REFADJ forms filter with 200µs time constant. achieve full 12-bit accuracy, time constants required after power-up bypass capacitor fully discharged between conversions. Waiting this FASTPD mode reducedpower mode (REDP) instead full power-down mode further reduce power consumption. This achieved using sequence shown Figure 12a. Figure shows MAX1281's power consumption 8-channel conversions using FULLPD mode (PD1 external reference, maximum clock speed. dummy conversion power-up device needed, wait-time necessary start second conversion, thereby achieving lower power consumption full sampling rate. Using Fast Power-Down Reduced-Power Modes FASTPD REDP modes achieve lowest power consumption speeds close maximum sample rate. Figure shows MAX1281's power consumption FASTPD mode (PD1 REDP mode (PD1 (for comparison) normal operating mode figure shows
10,000 MAX1281 VDD1 VDD2 3.0V CLOAD 20pF CODE 101010000000 MAX1281 VDD1 VDD2 3.0V CLOAD 20pF CODE 101010000000 CHANNELS CHANNEL
MAX1280/MAX1281
Power-Down Sequencing
MAX1280/MAX1281's automatic power-down modes save considerable power when operating
1.50 REFERENCE POWER-UP DELAY (ms) 1.25 1.00 0.75 0.50 0.25 0.0001
0.001
0.01
TIME SHUTDOWN
Figure Reference Power-Up Delay Time Shutdown
1000
SUPPLY CURRENT (µA)
CHANNELS CHANNEL
SUPPLY CURRENT (µA)
1000
SAMPLING RATE (sps)
100k SAMPLING RATE (sps)
Figure 10a. Average Supply Current Sample Rate (Using FULLPD Internal Reference)
Figure 10b. Average Supply Current Sampling Rate (Using FULLPD External Reference)
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
power consumption using specified power-down mode, with internal reference maximum clock speed. clock speed FASTPD REDP should limited 4.8MHz MAX1280/ MAX1281. FULLPD mode provide increased power
NORMAL OPERATION SUPPLY CURRENT (mA) REDP FASTPD
savings applications where MAX1280/ MAX1281 inactive long periods time, where intermittent bursts high-speed conversions required.
Internal External References
MAX1280/MAX1281 used with internal external reference. external reference connected directly REFADJ pin. internal buffer designed provide 2.5V both MAX1280/MAX1281. internally trimmed 1.22V reference buffered with gain +2.05V/V. Internal Reference MAX1280/MAX1281's full-scale range with internal reference 2.5V unipolar inputs ±1.25V bipolar inputs. internal reference voltage adjustable ±100mV with circuit Figure
MAX1281, VDD1 VDD2 3.0V CLOAD 20pF CODE 101010000000
SAMPLING RATE (sps)
Figure Average Supply Current Sampling Rate (Using REPD, FASTPD, Normal Operation Internal Reference)
External Reference external reference placed either input (REFADJ) output (REF) internal referencebuffer amplifier. REFADJ input impedance typically 17k. REF, input resistance minimum
WAIT
FULLPD
REDP
FULLPD 1.22V
1.22V FADJ 2.5V IVDD1 IVDD2 2.5mA
DUMMY CONVERSION
0.01µF
2.5V
2.5mA 1.3mA 0.9mA
2.5mA
Figure 12a. Full Power-Down Timing
REDPD
REDP
FASTPD
2.5V (ALWAYS 2.5mA 2.5mA 0.9mA 0.9mA 2.5mA 1.3mA
IVDD1 IVDD2
Figure 12b. Reduced-Power/Fast Power-Down Timing
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
+3.3V
OUTPUT CODE
MAX1281 510k 100k 0.01µF REFADJ
VREF VCOM -VREF VCOM 1LSB 4096
Figure MAX1281 Reference-Adjust Circuit
OUTPUT CODE FULL-SCALE TRANSITION
COM* INPUT VOLTAGE (LSB) *VCOM VREF VREF VCOM VCOM 1LSB 4096 1LSB
Figure Bipolar Transfer Function, Full Scale (FS) VREF VCOM, Zero Scale (ZS) VCOM
(COM) INPUT VOLTAGE (LSB)
tions occur halfway between successive-integer values. Output coding binary, with 1LSB 610µV unipolar bipolar operation.
Layout, Grounding, Bypassing
3/2LSB
Figure Unipolar Transfer Function, Full Scale (FS) VREF VCOM, Zero Scale (ZS) VCOM
18k. During conversion, external reference must deliver 350µA load current have less output impedance. reference higher output impedance noisy, bypass close with 4.7µF capacitor. Using REFADJ input makes buffering external reference unnecessary. direct input, disable internal buffer connecting REFADJ VDD1.
Transfer Function
Table shows full-scale voltage ranges unipolar bipolar modes. Figure depicts nominal, unipolar input/output (I/O) transfer function, Figure shows bipolar transfer function. Code transi-
best performance, printed circuit boards; wirewrap boards recommended. Board layout should ensure that digital analog signal lines separated from each other. analog digital (especially clock) lines parallel another, digital lines underneath package. Figure shows recommended system ground connections. Establish single-point analog ground (star ground point) GND. Connect analog grounds star ground. Connect digital system ground star ground this point only. lowest-noise operation, ground return star ground's power supply should impedance short possible. High-frequency noise VDD1 power supply affect high-speed comparator ADC. Bypass supply star ground with 0.1µF 10µF capacitors, located close MAX1280/ MAX1281. Minimize capacitor lead lengths best supply-noise rejection. power supply very noisy, resistor connected lowpass filter (Figure 16).
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Table Full Scale Zero Scale
UNIPOLAR MODE Full Scale VREF VCOM Zero Scale Positive Full Scale VREF VCOM BIPOLAR MODE Zero Scale VCOM Negative Full Scale -VREF VCOM
connected with MAX1280/MAX1281's SCLK input.
SUPPLIES VDD1 VDD2
VDD1
VDD2
DGND
MAX1280 MAX1281
*OPTIONAL
DIGITAL CIRCUITRY
Figure Power-Supply Grounding Connection
MAX1280/MAX1281's driven TMS320's port enable data clocked into MAX1280/MAX1281's pin. 8-bit word (1XXXXX11) should written MAX1280/MAX1281 initiate conversion place device into normal operating mode. Table select proper XXXXX values your specific application. MAX1280/MAX1281's SSTRB output monitored through TMS320's input. falling edge SSTRB output indicates that conversion progress data ready received from MAX1280/MAX1281. TMS320 reads data each next rising edges SCLK. These data bits represent 12-bit conversion result followed four trailing bits, which should ignored. Pull high disable MAX1280/MAX1281 until next conversion initiated.
High-Speed Digital Interfacing with QSPI
MAX1280/MAX1281 interface with QSPI using circuit Figure (fSCLK 4.0MHz, CPOL CPHA This QSPI circuit programmed conversion each eight channels. result stored memory without taxing CPU, since QSPI incorporates microsequencer.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) deviation values actual transfer function from straight line. This straight line either best-straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1280/MAX1281 measured using endpoint method.
TMS320LC3x Interface
Figure shows application circuit that interfaces MAX1280/MAX1281 TMS320 external clock mode. timing diagram this interface circuit shown Figure following steps initiate conversion MAX1280/MAX1281 read results: TMS320 should configured with CLKX (transmit clock) active-high output clock with CLKR (TMS320 receive clock) active-high input clock. CLKX CLKR TMS320
Differential Nonlinearity
Differential nonlinearity (DNL) difference between actual step width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) sample-to-sample variation time between samples.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
MAX1280
VDD1 VDD2 SCLK SSTRB DOUT REFADJ
0.1µF
10µF (POWER SUPPLIES) PCS0 MOSI
ANALOG INPUTS
VDD1
MAX1281
MC683XX
MISO
SHDN
4.7µF
0.01µF
(GND)
Figure QSPI Connections
Signal-to-Noise Ratio
waveform perfectly reconstructed from digital samples, Signal-to-noise ratio (SNR) ratio fullscale analog input (RMS value) quantization error (residual error). ideal theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits):
MAX1280 MAX1281
DOUT SSTRB
CLKX
SCLK
TMS320LC3x
CLKR
(6.02 1.76)dB reality, there other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, calculated taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
Signal-to-Noise Plus Distortion
Signal-to-noise ratio plus distortion (SINAD) ratio fundamental input frequency's amplitude equivalent other output signals. SINAD (dB) (SignalRMS NoiseRMS)
Figure MAX1280/MAX1281-to-TMS320 Serial Interface
Aperture Delay
Aperture delay (tAD) time defined between falling edge sampling clock instant when actual sample taken.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
SCLK START SEL2 SEL1 SEL0 UNI/BIP SGI/DIF HIGH IMPEDANCE HIGH IMPEDANCE
SSTRB DOUT
Figure MAX1280/MAX1281-to-TMS320 Serial Interface
Effective Number Bits
Effective number bits (ENOB) indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists quantization noise only. With input range equal fullscale range ADC, calculate effective number bits follows: ENOB (SINAD 1.76) 6.02
Ordering Information (continued)
PART MAX1281BCUP MAX1281BEUP TEMP. RANGE +70°C -40°C +85°C PINPACKAGE TSSOP TSSOP (LSB)
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) ratio first five harmonics input signal fundamental itself. This expressed
Typical Operating Circuit
VDD1 VDD2 0.1µF
where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics, respectively.
+2.5V ANALOG INPUTS
MAX1280 MAX1281
SCLK REFADJ DOUT SSTRB SHDN
4.7µF
(SK) MOSI (SO) MISO (SI)
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) ratio amplitude fundamental (maximum signal component) value next-largest distortion component.
0.01µF
_Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
_Package Information
TSSOP.EPS
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2000 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit AD

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