300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit AD

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300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit AD

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300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
MAX1080/MAX1081 10-bit analog-to-digital converters (ADCs) combine 8-channel analog-input multiplexer, high-bandwidth track/hold (T/H), serial interface with high conversion speed power consumption. MAX1080 operates from single +4.5V +5.5V supply; MAX1081 operates from single +2.7V +3.6V supply. Both devices' analog inputs software configurable unipolar/bipolar operation. 4-wire serial interface connects directly SPITM/QSPIand MICROWIREdevices without external logic. serial strobe output allows direct connection TMS320-family digital signal processors. MAX1080/ MAX1081 external serial-interface clock perform successive-approximation analog-to-digital conversions. devices feature internal +2.5V reference reference-buffer amplifier with ±1.5% voltage-adjustment range. external reference with VDD1 range also used. MAX1080/MAX1081 provide hard-wired SHDN four software-selectable power modes (normal operation, reduced power (REDP), fast power-down (FASTPD), full power-down (FULLPD)). These devices programmed automatically shut down conversion operate with reduced power. When using power-down modes, accessing serial interface automatically powers devices, quick turnon time allows them shut down between conversions. This technique supply current below 100mA lower sampling rates. MAX1080/MAX1081 available 20-pin TSSOP package. These devices higher-speed versions MAX148/MAX149. more information, refer respective data sheet.
Features
8-Channel Single-Ended 4-Channel Pseudo-Differential Inputs Internal Multiplexer Track/Hold Single-Supply Operation +4.5V +5.5V (MAX1080) +2.7V +3.6V (MAX1081) Internal +2.5V Reference 400ksps Sampling Rate (MAX1080) Power: 2.5mA (400ksps) 1.3mA (REDP) 0.9mA (FASTPD) (FULLPD) 4-Wire Serial Interface Software-Configurable Unipolar Bipolar Inputs 20-Pin TSSOP Package
MAX1080/MAX1081
Ordering Information
PART MAX1080ACUP MAX1080BCUP MAX1080AEUP TEMP. RANGE +70°C +70°C -40°C +85°C PINPACKAGE TSSOP TSSOP TSSOP (LSB) ±1/2 ±1/2
Ordering Information continued data sheet.
Configuration
VIEW
VDD1 VDD2 SCLK
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Digitizers Process Control
MAX1080 MAX1081
SSTRB DOUT REFADJ
Typical Operating Circuit appears data sheet. QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
SHDN
TSSOP
Maxim Integrated Products
free samples latest literature, visit www.maxim-ic.com phone 1-800-998-8800. small orders, phone 1-800-835-8769.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
ABSOLUTE MAXIMUM RATINGS
VDD_ -0.3V VDD1 VDD2 -0.3V 0.3V CH0-CH7, GND. -0.3V (VDD1 0.3V) REF, REFADJ -0.3V (VDD1 0.3V) Digital Inputs GND. -0.3V Digital Outputs -0.3V (VDD2 0.3V) Digital Output Sink Current .25mA Continuous Power Dissipation +70°C) 20-Pin TSSOP (derate 7.0mW/°C above +70°C) 559mW Operating Temperature Ranges MAX108_ _CUP +70°C MAX108_ _EUP. -40°C +85°C Storage Temperature Range -60°C +150°C Lead Temperature (soldering, 10s) +300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS-MAX1080
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching ±0.8 ±0.1 MAX1080A MAX1080B missing codes over temperature ±0.5 ±1.0 ±1.0 ±3.0 ±3.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle fSCLK tCONV tACQ SINAD SFDR fIN1 99kHz, fIN2 =102kHz 200kHz, 2.5Vp-p -3dB point SINAD 58dB harmonic
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
ELECTRICAL CHARACTERISTICS-MAX1080 (continued)
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER SYMBOL CONDITIONS Unipolar, VCOM VCH_ Bipolar, VCOM VCH_ VREF/2, referenced On/off leakage current, VCH_ VDD1 ±0.001 VREF +25°C 2.480 2.500 VREF output load 0.01 1.22 small adjustments, from 1.22V power down internal reference +2.05 VDD1 50mV VDD2 ISINK ISOURCE ±100 VDD1 2.520 VREF ±VREF/2 ppm/°C mV/mA UNITS ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, Single Ended Differential (Note Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Temperature Coefficient Load Regulation (Note Capacitive Bypass Capacitive Bypass REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (reference buffer disabled, reference applied REF) Input Voltage Range (Note VREF 2.500V, fSCLK 6.4MHz Input Current DIGITAL INPUTS (DIN, SCLK, SHDN) Input High Voltage Input Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance COUT VINH VINL VHYST VREF 2.500V, fSCLK power-down mode, fSCLK
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
ELECTRICAL CHARACTERISTICS-MAX1080 (continued)
(VDD1 VDD2 +4.5V +5.5V, GND, fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER POWER SUPPLY Positive Supply Voltage (Note VDD1, VDD2 Normal operating mode (Note Supply Current IVDD1+ IVDD2 VDD1 VDD2 5.5V Reduced-power mode (Note Fast power-down mode (Note Full power-down mode (Note Power-Supply Rejection VDD1 VDD2 ±10%, midscale input ±0.5 ±2.0 SYMBOL CONDITIONS UNITS
ELECTRICAL CHARACTERISTICS-MAX1081
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching ±1.6 ±0.2 MAX1081A MAX1081B missing codes over temperature ±0.5 ±1.0 ±1.0 ±3.0 ±3.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note Full-Power Bandwidth Full-Linear Bandwidth SINAD SFDR fIN1 73kHz, fIN2 77kHz 150kHz, 2.5Vp-p -3dB point SINAD 58dB harmonic
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS-MAX1081 (continued)
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, Single Ended Differential (Note Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Temperature Coefficient Load Regulation (Note Capacitive Bypass Capacitive Bypass REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (reference buffer disabled, reference applied REF) Buffer Voltage Gain Input Voltage Range (Note VREF 2.500V, fSCLK 4.8MHz Input Current DIGITAL INPUTS (DIN, SCLK, SHDN) Input High Voltage Input Voltage Input Hysteresis Input Leakage Input Capacitance VINH VINL VHYST VDD2 VREF 2.500V, fSCLK power-down mode, fSCLK small adjustments, from 1.22V power down internal reference +2.05 2.05 VDD1 50mV VREF 0.75mA output load 0.01 1.22 ±100 VDD1 VREF +25°C 2.480 2.500 2.520 ppm/°C mV/mA Unipolar, VCOM VCH_ Bipolar, VCOM VCH_ VREF/2, referenced On/off leakage current, VCH_ VDD1 ±0.001 VREF ±VREF/2 fSCLK Normal operating mode tCONV tACQ Normal operating mode Normal operating mode SYMBOL CONDITIONS UNITS
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
ELECTRICAL CHARACTERISTICS-MAX1081 (continued)
(VDD1 VDD2 +2.7V +3.6V, GND, fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps), external +2.5V REF, REFADJ VDD1, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note VDD1, VDD2 Normal operating mode (Note Supply Current IVDD1+ IVDD2 VDD1 VDD2 3.6V Reduced-power mode (Note Fast power-down mode (Note Full power-down mode (Note Power-Supply Rejection VDD1 VDD2 2.7V 3.6V, midscale input ±0.5 ±2.0 SYMBOL COUT ISINK ISOURCE 0.5mA VDD2 0.5V CONDITIONS UNITS DIGITAL OUTPUTS (DOUT, SSTRB)
TIMING CHARACTERISTICS-MAX1080
(Figures VDD1 VDD2 +4.5V +5.5V, TMIN TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width SCLK Setup SCLK Hold Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall Ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise SSTRB Hold SCLK Rise DOUT Valid SCLK Rise SSTRB Valid Rise DOUT Disable Rise SSTRB Disable Fall DOUT Enable Fall SSTRB Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
TIMING CHARACTERISTICS-MAX1081
(Figures VDD1 VDD2 +2.7V +3.6V, TMIN TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width SCLK Setup SCLK Hold Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise SSTRB Hold SCLK Rise DOUT Valid SCLK Rise SSTRB Valid Rise DOUT Disable Rise SSTRB Disable Fall DOUT Enable Fall SSTRB Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
Note Tested VDD1 VDD2 VDD(MIN), GND, unipolar single-ended input mode. Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Offset nulled. Note Ground "on" channel; sine wave applied "off" channels. Note Conversion time defined number clock cycles multiplied clock period; clock duty cycle. Note common-mode range analog inputs (CH7-CH0 COM) from VDD1. Note External load should change during conversion specified accuracy. Guaranteed specification 2mV/mA result production test limitations. Note performance limited converter's noise floor, typically 300µVp-p. Note Electrical characteristics guaranteed from VDD1(MIN) VDD2(MIN) VDD1(MAX) VDD2(MIN). operations beyond this range, Typical Operating Characteristics. guaranteed specifications beyond limits, contact factory. Note AIN= midscale. Unipolar mode. MAX1080 tested with 20pF DOUT, 20pF SSTRB, fSCLK 6.4MHz, MAX1081 tested with same loads, fSCLK 4.8MHz, Note SCLK GND, VDD1.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
Typical Operating Characteristics
(MAX1080: VDD1 VDD2 5.0V, fSCLK 6.4MHz; MAX1081: VDD1 VDD2 3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, 0.01µF capacitor REFADJ, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1080/1-01
DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1080/1-02
SUPPLY CURRENT SUPPLY VOLTAGE (CONVERTING)
MAX1080/1-03
0.12
0.15 0.10 0.05 (LSB)
0.08
(LSB)
0.04
-0.05
SUPPLY CURRENT (mA) 1000 1200
-0.04
-0.10 -0.15 1000 1200 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE SUPPLY VOLTAGE
-0.08
SUPPLY CURRENT TEMPERATURE
MAX1080/1-04
SUPPLY CURRENT SUPPLY VOLTAGE (STATIC)
MAX1080/1-05
SUPPLY CURRENT TEMPERATURE (STATIC)
MAX1080/1-06
SUPPLY CURRENT (mA) MAX1081 MAX1080
NORMAL OPERATION (PD1
MAX1080 (PD1 MAX1081 (PD1 MAX1080 (PD1 MAX1081 (PD1
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
REDP (PD1
FASTPD (PD1
MAX1080 (PD1 MAX1081 (PD1
TEMPERATURE (°C) SUPPLY VOLTAGE
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE
MAX1080/1-07
SHUTDOWN SUPPLY CURRENT TEMPERATURE
(PD1 SUPPLY CURRENT (µA) MAX1080
MAX1080/1-08
REFERENCE VOLTAGE SUPPLY VOLTAGE
MAX1080/1-09
(PD1 SUPPLY CURRENT (µA)
2.5005
2.5003 REFERENCE VOLTAGE
MAX1081
2.5001
2.4999
2.4997
SUPPLY VOLTAGE
TEMPERATURE (°C)
2.4995 SUPPLY VOLTAGE
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1080: VDD1 VDD2 5.0V, fSCLK 6.4MHz; MAX1081: VDD1 VDD2 3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, 0.01µF capacitor REFADJ, +25°C, unless otherwise noted.)
MAX1080/MAX1081
REFERENCE VOLTAGE TEMPERATURE
MAX1080/1-10
OFFSET ERROR SUPPLY VOLTAGE
MAX1080/1-11
OFFSET ERROR TEMPERATURE
MAX1080/1-12
2.5002 2.5000 MAX1080 REFERENCE VOLTAGE 2.4998 2.4996 2.4994 2.4992 2.4990 2.4988 MAX1081
OFFSET ERROR (LSB)
OFFSET ERROR (LSB)
-0.25
-0.25
-0.50
-0.50
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR SUPPLY VOLTAGE
MAX1080/1-13
MAX1081 GAIN ERROR TEMPERATURE
MAX1080/1-14
0.25
GAIN ERROR (LSB)
GAIN ERROR (LSB)
-0.25
-0.25
-0.50
-0.75
-0.50 TEMPERATURE (°C)
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
Description
NAME CH0-CH7 SHDN Sampling Analog Inputs Ground Reference Analog Inputs. sets zero-code voltage single-ended mode. Must stable ±0.5LSB. Active-Low Shutdown Input. Pulling SHDN shuts down device, reducing supply current (typ). Reference-Buffer Output/ADC Reference Input. Reference voltage analog-to-digital conversion. internal reference mode, reference buffer provides 2.500V nominal output, externally adjustable REFADJ. external reference mode, disable internal buffer pulling REFADJ VDD1. Input Reference-Buffer Amplifier. disable reference-buffer amplifier, connect REFADJ VDD1. Analog Digital Ground Serial Data Output. Data clocked SCLK's rising edge. High impedance when high. Serial Strobe Output. SSTRB pulses high clock period before decision. High impedance when high. Serial Data Input. Data clocked SCLK's rising edge. Active-Low Chip Select. Data will clocked into unless low. When high, DOUT SSTRB high impedance. Serial Clock Input. Clocks data serial interface sets conversion speed. (Duty cycle must 60%.) Positive Supply Voltage Positive Supply Voltage FUNCTION
REFADJ DOUT SSTRB SCLK VDD2 VDD1
VDD2
VDD2 DOUT CLOAD 20pF High-Z DOUT CLOAD 20pF High-Z
DOUT CLOAD 20pF High-Z
DOUT
CLOAD 20pF High-Z
Figure Load Circuits Enable Time
Figure Load Circuits Disable Time
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
Detailed Description
MAX1080/MAX1081 ADCs successiveapproximation conversion technique input circuitry convert analog signal 10-bit digital output. flexible serial interface provides easy interface microprocessors (µPs). Figure shows functional diagram MAX1080/MAX1081. sinusoidal signal IN-, input voltage determined VIN- sin(2ft) maximum voltage variation determined dIN- 1LSB VREF VIN- CONV CONV
MAX1080/MAX1081
Pseudo-Differential Input
equivalent circuit Figure shows MAX1080/ MAX1081s' input architecture, which composed T/H, input multiplexer, input comparator, switchedcapacitor DAC, reference. single-ended mode, positive input (IN+) connected selected input channel negative input (IN-) COM. differential mode, selected from following pairs: CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7. Configure channels according Tables MAX1080/MAX1081 input configuration pseudodifferential because only signal sampled. return side (IN-) connected sampling capacitor while converting must remain stable within ±0.5LSB (±0.1LSB best results) with respect during conversion. varying signal applied selected IN-, amplitude frequency must limited maintain accuracy. following equations express relationship between maximum signal amplitude frequency maintain ±0.5LSB accuracy. Assuming
+1.22V REFERENCE REFADJ INPUT SHIFT REGISTER CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT CLOCK 2-BIT 2.05 DOUT SSTRB +2.500V VDD1 VDD2
2.6Vp-p, 60Hz signal will generate ±0.5LSB error when using +2.5V reference voltage 2.5µs conversion time SCLK When reference voltage used IN-, connect 0.1µF capacitor minimize noise input. During acquisition interval, channel selected positive input (IN+) charges capacitor CHOLD. acquisition interval spans three SCLK cycles ends falling SCLK edge after input control word's last been entered. acquisition interval, switch opens, retaining charge HOLD sample signal IN+. conversion interval begins with input multiplexer switching CHOLD from IN-. This unbalances node ZERO comparator's input. capacitive adjusts during remainder conversion cycle restore node ZERO VDD1/2 within limits 10-bit resolution. This action equivalent transferring 12pF [(VIN+ VIN-)] charge from CHOLD binaryweighted capacitive DAC, which turn forms digital representation analog input signal.
INPUT CAPACITIVE CHOLD 12pF ZERO CSWITCH* HOLD TRACK SAMPLING INSTANT, INPUT SWITCHES FROM SELECTED CHANNEL SELECTED CHANNEL. COMPARATOR
SCLK SHDN
MAX1080 MAX1081
VDD1/2 SINGLE-ENDED MODE: CH0-CH7, COM. PSEUDO-DIFFERENTIAL MODE: SELECTED FROM PAIRS CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7. *INCLUDES INPUT PARASITICS
Figure Functional Diagram
Figure Equivalent Input Circuit
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
Track/Hold
enters tracking mode falling clock edge after fifth 8-bit control word been shifted enters hold mode falling clock edge after eighth control word been shifted converter single-ended inputs, connected converter converts input. converter differential inputs, difference [(IN+) (IN-)] converted. conversion, positive input connects back CHOLD charges input signal. time required acquire input signal function quickly input capacitance charged. input signal's source impedance high, acquisition time lengthens, more time must allowed between conversions. acquisition time, tACQ, maximum time device takes acquire signal minimum time needed signal acquired. calculated following equation: tACQ RIN) 12pF where 800, source impedance input signal, never less than 468ns (MAX1080) 625ns (MAX1081). Note that source impedances below significantly affect ADC's performance.
Input Bandwidth
ADC's input tracking circuitry 6MHz (MAX1080) 3MHz (MAX1081) small-signal bandwidth, possible digitize high-speed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid high-frequency signals being aliased into frequency band interest, antialias filtering recommended.
Analog Input Protection
Internal protection diodes, which clamp analog input VDD1 GND, allow channel input pins swing from 0.3V 0.3V without damage. However, accurate conversions near full scale, inputs must exceed VDD1 more than 50mV lower than 50mV. analog input exceeds 50mV beyond supplies, allow input current exceed 2mA.
Table Channel Selection Single-Ended Mode (SGL/DIF
SEL2 SEL1 SEL0
Table Channel Selection Pseudo-Differential Mode (SGL/DIF
SEL2 SEL1 SEL0
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
OSCILLOSCOPE
+2.500V ANALOG INPUT 0.01µF
MAX1080 MAX1081
VDD1 VDD2
0.1µF 10µF
SCLK SSTRB
REFADJ 0.01µF 2.5V 4.7µF
SCLK DOUT VDD2 EXTERNAL CLOCK DOUT*
SSTRB SHDN VDD2
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT $3FF (HEX)
Figure Quick-Look Circuit
Quick Look
quickly evaluate MAX1080/MAX1081s' analog performance, circuit Figure devices require control byte written before each conversion. Connecting VDD2 feeds control bytes (HEX), which trigger single-ended unipolar conversions without powering down between conversions. SSTRB output pulses high clock period before conversion result shifted DOUT. Varying analog input will alter sequence bits from DOUT. total clock cycles required conversion. transitions SSTRB DOUT outputs typically occur 20ns after rising edge SCLK.
transfers perform conversion (one 8-bit transfer configure ADC, more 8-bit transfers clock conversion result). Figure MAX1080/ MAX1081 QSPI connections. Simple Software Interface Make sure CPU's serial interface runs master mode generates serial clock. Choose clock frequency from 500kHz 6.4MHz (MAX1080) 4.8MHz (MAX1081): control byte call TB1. should format: 1XXXXXXX binary, where denote particular channel, selected conversion mode, power mode. general-purpose line pull low. Transmit simultaneously receive byte call RB1. Ignore RB1. Transmit byte zeros ($00 hex) simultaneously receive byte RB2. Transmit byte zeros ($00 hex) simultaneously receive byte RB3. Pull high.
Starting Conversion
Start conversion clocking control byte into DIN. With low, each rising edge SCLK clocks from into MAX1080/MAX1081s' internal shift register. After falls, first arriving logic defines control byte's MSB. Until this first "start" arrives, number logic bits clocked into with effect. Table shows control-byte format. MAX1080/MAX1081 compatible with SPI/ QSPI MICROWIRE devices. SPI, select correct clock polarity sampling edge control registers: CPOL CPHA MICROWIRE, SPI, QSPI transmit byte receive byte same time. Using Typical Operating Circuit, simplest software interface requires only three 8-bit
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
Table Control-Byte Format
(MSB) START 7(MSB) SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP SEL1 DESCRIPTION first logic after goes defines beginning control byte. These three bits select which eight channels used conversion (Tables SEL0 UNI/BIP SGL/DIF (LSB)
unipolar, bipolar. Selects unipolar bipolar conversion mode. unipolar mode, analog input signal from VREF converted; bipolar mode, differential signal range from -VREF/2 +VREF/2. single ended, pseudo-differential. Selects single-ended pseudo-differential conversions. single-ended mode, input signal voltages referred COM. pseudo-differential mode, voltage difference between channels measured (Tables Select operating mode. Mode Full power-down Fast power-down Reduced power Normal operation
SGL/DIF
0(LSB)
Figure shows timing this sequence. Bytes contain result conversion, padded with three leading zeros, sub-LSB bits, trailing zero. total conversion time function serial-clock frequency amount idle time between 8-bit transfers. avoid excessive droop, make sure total conversion time does exceed 120µs. Digital Output unipolar input mode, output straight binary (Figure 14). bipolar input mode, output two's complement (Figure 15). Data clocked rising edge SCLK MSB-first format.
conversion must complete 120µs less, droop sample-and-hold capacitors degrade conversion results.
Data Framing
falling edge does start conversion. first logic high clocked into interpreted start defines first control byte. conversion starts SCLK's falling edge, after eighth control byte (the bit) clocked into DIN. start defined follows: first high clocked into with time converter idle, e.g., after VDD1 VDD2 applied. first high clocked into after conversion progress clocked onto DOUT pin. Once start been recognized, current conversion only terminated pulling SHDN low. fastest MAX1080/MAX1081 with held between conversions clocks conversion. Figure shows serial-interface timing necessary perform conversion every SCLK cycles. tied SCLK continuous, guarantee start first clocking zeros.
Serial Clock
external clock only shifts data also drives analog-to-digital conversion steps. SSTRB pulses high clock period after last control byte. Successive-approximation decisions made appear DOUT each next SCLK rising edges (Figure SSTRB DOUT into high-impedance state when goes high; after next falling edge, SSTRB outputs logic low. Figure shows detailed serial-interface timings.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
tACQ SCLK
UNI/ SGL/ START
HIGH-Z SSTRB HIGH-Z DOUT IDLE ACQUISITION CONVERSION IDLE
HIGH-Z
HIGH-Z
Figure Single-Conversion Timing
_Applications Information
Power-On Reset
When power first applied, SHDN pulled low, internal power-on reset circuitry activates MAX1080/MAX1081 normal operating mode, ready convert with SSTRB low. MAX1080/MAX1081 require 10µs reset after power supplies stabilize; conversions should initiated during this time. low, first logical interpreted start bit. Until conversion takes place, DOUT shifts zeros. Additionally, wait reference stabilize when using internal reference.
power-up delay dependent power-down state. Software low-power modes will able start conversion immediately when running decreased clock rates (see Power-Down Sequencing). During power-on reset, when exiting software full power-down mode, when exiting hardware shutdown, device goes immediately into full-power mode ready convert after when using external reference. When using internal reference, wait typical power-up delay from full power-down (software hardware) shown Figure Software Power-Down Software power-down activated using bits control byte. When software power-down asserted, completes conversion progress powers down into specified low-quiescent-current state (2µA, 0.9mA, 1.3mA). first logic interpreted start puts MAX1080/MAX1081 into full-power mode. Following start bit, data input word control byte also determines next power-down state. example, word contains 0.9mA power-down resumes after conversion. Table details four power modes with corresponding supply current operating sections. data rates achievable software power-down modes, Power-Down Sequencing.
Power Modes
save power placing converter low-current operating modes full power-down between conversions. Select power mode through control byte (Tables force converter into hardware shutdown driving SHDN GND. software power-down modes take effect after conversion completed; SHDN overrides software power mode immediately stops conversion progress. software power-down mode, serial interface remains active while waiting control byte start conversion switch full-power mode. Once conversion completed, device goes into programmed power mode until control byte written.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
tCSW tCSS tCSO SCLK tDOH tDOV tDOE DOUT tSTH tSTV tDOD tCSH tCS1
tSTE SSTRB
tSTD
Figure Detailed Serial-Interface Timing
Table Software-Controlled Power Modes
TOTAL SUPPLY CURRENT PD1/PD0 MODE CONVERTING (mA) AFTER CONVERSION 0.9mA 1.3mA 2.0mA CIRCUIT SECTIONS* INPUT COMPARATOR Reduced Power Reduced Power Full Power REFERENCE
Full Power-Down (FULLPD) Fast Power-Down (FASTPD) Reduced-Power Mode (REDP) Normal Operating
*Circuit operation between conversions; during conversion circuits fully powered
Hardware Power-Down Pulling SHDN places converter hardware power-down. Unlike software power-down mode, conversion terminated immediately. When returning normal operation from SHDN with external reference, MAX1080/MAX1081 considered fully powered within actively pulling SHDN high. When using internal reference, conversion should initiated only after reference settled; recovery time dependent external bypass capacitors shutdown duration.
average supply current function sampling rate. Using Full Power-Down Mode Full power-down mode (FULLPD) achieves lowest power consumption, 1000 conversions channel second. Figure shows MAX1081's power consumption one- eight-channel conversions utilizing full power-down mode (PD1 with internal reference maximum clock speed. 0.01µF bypass capacitor REFADJ forms filter with internal reference resistor, with 200µs time constant. achieve full 10-bit accuracy, seven time constants 1.4ms required after power-up bypass capacitor fully discharged between conversions. Waiting this 1.4ms duration
Power-Down Sequencing
MAX1080/MAX1081 automatic power-down modes save considerable power when operating less than maximum sample rates. Figures show
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
CONTROL BYTE
CONTROL BYTE
CONTROL BYTE
ETC.
SCLK
HIGH-Z DOUT
CONVERSION RESULT
CONVERSION RESULT
HIGH-Z SSTRB
Figure Continuous 16-Clock/Conversion Timing
1.50 REFERENCE POWER-UP DELAY (ms) 1.25 1.00 0.75 0.50 0.25 0.0001 0.001 0.01 100k TIME SHUTDOWN SAMPLING RATE (sps) SUPPLY CURRENT (µA) 1000 CHANNELS CHANNEL 10,000 MAX1081, VDD1 VDD2 3.0V CLOAD 20pF CODE 1010100000
Figure Reference Power-Up Delay Time Shutdown
Figure 10b. Average Supply Current Sampling Rate (sps) Using FULLPD External Reference
1000 MAX1081, VDD1 VDD2 3.0V CLOAD 20pF CODE 1010100000 SUPPLY CURRENT (mA) SUPPLY CURRENT (µA)
NORMAL OPERATION REDP FASTPD
CHANNELS CHANNEL
MAX1081, VDD1= VDD2 3.0V CLOAD 20pF CODE 1010100000
SAMPLING RATE (sps)
SAMPLING RATE (sps)
Figure 10a. Average Supply Current Sampling Rate (sps) Using FULLPD Internal Reference
Figure Average Supply Current Sampling Rate (sps) Using FASTPD, REDP, Normal Operation, Internal Reference
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
fast power-down (FASTPD) reduced-power (REDP) mode instead full power-up further reduce power consumption. This achieved using sequence shown Figure 12a. Figure shows MAX1081's power consumption one- eight-channel conversions utilizing FULLPD mode (PD1 external reference, maximum clock speed. dummy conversion power device needed, wait time necessary start second conversion, thereby achieving lower power consumption half full sampling rate. Using Fast Power-Down Reduced Power Modes FASTPD REDP modes achieve lowest power consumption speeds close maximum sampling rate. Figure shows MAX1081's power consumption FASTPD mode (PD1 REDP mode (PD1 comparison, normal operating mode (PD1 figure shows power consumption using specified power-down mode, with internal reference conversion controlled maximum clock speed. clock speed FASTPD REDP should limited 4.8MHz MAX1080/MAX1081. FULLPD mode provide increased power savings applications where MAX1080/MAX1081 inactive long periods time, intermittent bursts high-speed conversions required. Figure shows FASTPD REDP timing.
Internal External References
MAX1080/MAX1081 used with internal external reference. external reference connected directly REFADJ pin. internal buffer designed provide 2.5V MAX1080/MAX1081. internally trimmed 1.22V reference buffered with 2.05V/V gain. Internal Reference MAX1080/MAX1081s' full-scale range with internal reference 2.5V with unipolar inputs ±1.25V with bipolar inputs. internal reference voltage adjustable ±100mV with circuit Figure
WAIT 1.4ms
FULLPD
REDP
FULLPD 1.22V
1.22V REFADJ 2.5V IVDD1 IVDD2 2.5mA
DUMMY CONVERSION
0.01µF
2.5V
2.5mA 1.3mA 0.9mA
2.5mA
Figure 12a. Full Power-Down Timing
REDP
REDP
FASTPD
2.5V (ALWAYS 2.5mA 2.5mA 0.9mA 0.9mA 2.5mA 1.3mA
IVDD1 IVDD2
Figure 12b. FASTPD REDP Timing
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
+3.3V MAX1081 510k 100k 0.01µF REFADJ
OUTPUT CODE VREF VCOM VCOM -VREF VCOM VREF 1LSB 1024
Figure MAX1081 Reference-Adjust Circuit
OUTPUT CODE FULL-SCALE TRANSITION
COM* INPUT VOLTAGE (LSB) *VCOM VREF VREF VCOM VCOM 1LSB 1024 1LSB
Figure Bipolar Transfer Function, Full Scale (FS) VREF VCOM, Zero Scale (ZS) VCOM
Transfer Function
Table shows full-scale voltage ranges unipolar bipolar modes. Figure depicts nominal, unipolar input/output (I/O) transfer function, Figure shows bipolar transfer function. Code transitions occur halfway between successive-integer values. Output coding binary, with 1LSB 2.44mV unipolar bipolar operation.
(COM) INPUT VOLTAGE (LSB)
3/2LSB
Layout, Grounding, Bypassing
Figure Unipolar Transfer Function, Full Scale (FS) VREF VCOM, Zero Scale (ZS) VCOM
External Reference external reference placed input (REFADJ) output (REF) internal referencebuffer amplifier. REFADJ input impedance typically 17k. REF, input resistance minimum 18k. During conversion, external reference must deliver 350µA load current have less output impedance. reference higher output impedance noisy, bypass close with 4.7µF capacitor. Using REFADJ input makes buffering external reference unnecessary. direct input, disable internal buffer connecting REFADJ VDD1.
best performance, boards; wire-wrap boards recommended. Board layout should ensure that digital analog signal lines separated from each other. analog digital (especially clock) lines parallel another, digital lines underneath package. Figure shows recommended system ground connections. Establish single-point analog ground (star ground point) GND. Connect other analog grounds star ground. Connect digital system ground this ground only this point. lowestnoise operation, ground return star ground's power supply should impedance short possible. High-frequency noise power supply affect high-speed comparator ADC. Bypass supply star ground with 0.1µF 10µF capacitors close MAX1080/MAX1081.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
Table Full Scale Zero Scale
UNIPOLAR MODE Full Scale VREF VCOM Zero Scale VCOM Positive Full Scale VREF VCOM BIPOLAR MODE Zero Scale VCOM Negative Full Scale -VREF VCOM
SUPPLIES VDD1 VDD2
clock) active-high output clock CLKR (TMS320 receive clock) active-high input clock. CLKX CLKR TMS320 connected MAX1080/MAX1081's SCLK input. MAX1080/MAX1081's driven TMS320's port enable data clocked into MAX1080/MAX1081s' pin. 8-bit word (1XXXXX11) should written MAX1080/MAX1081 initiate conversion place device into normal operating mode. Table select proper XXXXX values your specific application. MAX1080/MAX1081s' SSTRB output monitored through TMS320's input. falling edge SSTRB output indicates that conversion progress data ready received from device. TMS320 reads data each next rising edges SCLK. These data bits represent 2-bit conversion result followed trailing bits, which should ignored. Pull high disable MAX1080/MAX1081 until next conversion initiated.
VDD1
VDD2
DGND
MAX1080 MAX1081
*OPTIONAL
DIGITAL CIRCUITRY
Figure Power-Supply Grounding Connection
Minimize capacitor lead lengths best supply-noise rejection. power supply very noisy, resistor connected lowpass filter (Figure 16).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) deviation values from straight line actual transfer function. This straight line best-straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1080/MAX1081 measured using best-straight-line method.
High-Speed Digital Interfacing with QSPI
MAX1080/MAX1081 interface with QSPI using circuit Figure SCLK 4.0MHz, CPOL CPHA This QSPI circuit programmed conversion each eight channels. result stored memory without taxing CPU, since QSPI incorporates microsequencer.
TMS320LC3x Interface
Figure shows application circuit interface MAX1080/MAX1081 TMS320 external clock mode. Figure shows timing diagram this interface circuit. following steps initiate conversion MAX1080/MAX1081 read results: TMS320 should configured with CLKX (trans20
Differential Nonlinearity
Differential nonlinearity (DNL) difference between actual step width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
MAX1080
VDD1 VDD2 SCLK SSTRB DOUT REFADJ
0.1µF
10µF (POWER SUPPLIES) PCS0 MOSI
ANALOG INPUTS
VDD1
MAX1081
MC683XX
MISO
SHDN
4.7µF
0.01µF
(GND)
Figure QSPI Connections
Aperture Jitter
Aperture jitter (tAJ) sample-to-sample variation time between samples.
Aperture Delay
CLKX
SCLK
Aperture delay time defined between rising edge sampling clock instant when actual sample taken.
MAX1080 MAX1081
TMS320LC3x
CLKR
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused only quantization error results directly from ADC's resolution bits): (6.02
DOUT SSTRB
1.76)dB
Figure MAX1080/MAX1081-to-TMS320 Serial Interface
Aperture Width
Aperture width (tAW) time circuit requires disconnect hold capacitor from input circuit (for instance, turn sampling bridge unit hold mode).
reality, there other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, calculated taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
SCLK START SEL2 SEL1 SEL0 UNI/BIP SGI/DIF HIGH IMPEDANCE HIGH IMPEDANCE
SSTRB DOUT
Figure MAX1080/MAX1081-to-TMS320 Serial Interface
Signal-to-Noise Plus Distortion (SINAD)
SINAD ratio fundamental input frequency's amplitude equivalent other output signals: SINAD (dB) (SignalRMS NoiseRMS)
Ordering Information (continued)
PART MAX1080BEUP MAX1081ACUP MAX1081BCUP MAX1081AEUP MAX1081BEUP TEMP. RANGE -40°C +85°C +70°C +70°C -40°C +85°C -40°C +85°C PINPACKAGE TSSOP TSSOP TSSOP TSSOP TSSOP (LSB) ±1/2 ±1/2
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists only quantization noise. With input range equal ADC's full-scale range, calculate ENOB follows: ENOB (SINAD 1.76) 6.02
Typical Operating Circuit
+2.5V ANALOG INPUTS VDD1 VDD2 0.1µF
Total Harmonic Distortion (THD)
ratio input signal's first five harmonics fundamental itself. This expressed where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
MAX1080 MAX1081
SCLK REFADJ DOUT SSTRB SHDN VDD2
4.7µF
(SK) MOSI (SO) MISO (SI)
0.01µF
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next-largest distortion component.
Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
_Package Information
TSSOP.EPS
MAX1080/MAX1081
Note: MAX1080/MAX1081 have exposed pad.
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference MAX1080/MAX1081
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2000 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit AD

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