Preliminary Information (See Last Page) Dual Feed Active-ORing Pr

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Preliminary Information (See Last Page) Dual Feed Active-ORing Pr

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SMH4814
Preliminary Information (See Last Page)
Dual Feed Active-ORing Programmable Swap Controller
FEATURES APPLICATIONS
Eliminates Passive ORing Diodes Reduced Power Consumption High Noise Immunity Logic Inputs Soft Starts Main Power Supply Card Insertion System Power with Slew Rate Control Programmable Differential Current Sense Programmable Inrush Current Limiting Master Enable Allow System Control Power-Up -Down Programmable Independent Enabling DC/DC Converters Programmable Circuit Breaker Level Mode Programmable Quick-TripValue, Current Limiting, Duty Cycle Times, Over-Current Filter Programmable Host Voltage Fault Monitoring Programmable UV/OV Filter Hysteresis Programmable Fault Mode: Latched Duty Cycle Internal Shunt Regulator Allows Wide Supply Range
INTRODUCTION
SMH4814 integrated power controller designed control hot-swapping plug-in cards distributed power environment. SMH4814 drives external power MOSFET switches that connect supply load while reducing in-rush current providing over-current protection. When source drain voltages external MOSFETs within specification SMH4814 asserts four logic outputs programmable cascade sequence enable DC/DC converters. SMH4814 also monitors independent -48V feeds. redundant power supplies allow high availability reliability. traditional method supplying power from these feeds ORing power diodes, which consume significant amount power. SMH4814 allows low-RDSON FETs used place ORing diodes reduce power consumption. SMH4814 determines when least -48V feeds within acceptable voltage range switches appropriate path while providing slew rate control. SMH4814 continuously monitors incoming feeds switches most negative feed necessary. SMH4814 programmed controlled using required ATCAapplications.
Applications
Telecom Hot-Swap Card AdvancedTCANetwork Processors Power-on Ethernet, IEEE 802.3af
SIMPLIFIED APPLICATIONS DRAWING
-48V Ret.
VIN+ Detect PUPA PUPB PUPC DRAIN SENSE PUPD VOUT+ DC-to-DC Converter ON/OFF VINVOUT-
SMH4814
CBSENSE FEEDA FEEDB VGATEA VGATEB VGATE_HS
Detect
Primary Secondary
-48V -48V
Figure SMH4814 Controller hot-swaps cascade sequences DC/DC Converters actively controls -48V feeds eliminating need ORing diodes associated voltage drop.
Note: This applications example only. Some pins, components values shown. SUMMIT Microelectronics, Inc. 2005 1717 Drive Jose 95131 Phone 436-9890 436-9897 Summit Site accessed "right" "left" mouse clicking link: http://www.summitmicro.com/ 2080 07/21/05
SMH4814
Preliminary Information
GENERAL DESCRIPTION
SMH4814 integrated power controller operates within wide supply range, typically volts, generates signals necessary drive isolatedoutput DC/DC converters. device accepts independent -48V feeds input pins FEEDA FEEDB. VGATEA controls flow power from FEEDA load. VGATEB controls flow power from FEEDB load. SMH4814 continuously monitors voltage FEEDA FEEDB. supply arbitration block Figure selects which drives power device based voltage level each acceptable voltage range. Once FEEDA FEEDB selected SMH4814 asserts corresponding VGATE pin. assertion this turns external low-RDSON FETs supply power load. Start-up Procedure general start-up procedure follows: physical connection must made with chassis discharge electrostatic voltage potentials when typical add-in board inserted into powered backplane. board then contacts long pins backplane that provide power ground. soon power applied device starts does immediately apply power output load. Under-voltage over-voltage circuits inside controller verify that input voltage within user-specified range. SMH4814 senses detection signals indicate card seated properly. These requirements must Detect Delay period tPDD. Once this time elapsed hot-swap controller enables VGATE_HS turn external power MOSFET switch. VGATE_HS output current limited IVGATE, allowing slew rate easily modified using external passive components. During controlled turn-on period MOSFET monitored DRAIN SENSE input. When DRAIN SENSE drops below 2.5V, VGATE_HS rises above VGT, SMH4814 asserts PUPA through PUPD power good outputs enable DC/DC controllers. Steady-state operation maintained long conditions normal. following events cause device disable DC/DC controllers shutting down power MOSFETs: under-voltage over-voltage condition host power supply. failure power MOSFET sensed DRAIN SENSE pin. PD1/PD0 detect signals becoming invalid. master enable (EN/TS) falls below 2.5V. inputs driven events secondary side DC/DC controllers. occurrence overcurrent. SMH4814 configured that after these events occurs VGATE output shuts off, either latches into state recycles power after cooling down period, tCYC. Powering SMH4814 contains internal shunt regulator that prevents voltage from exceeding 12V. necessary dropping resistor (RD) between host power supply order limit current into device prevent possible damage. dropping resistor allows device operate across wide range system supply voltages, typically -72V, also helps protect device against common-mode power surges. Refer Applications Section help calculating resistance value.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
INTERNAL FUNCTIONAL BLOCK DIAGRAM
Voltage Regulator Reference Generator
PUPA Polarity
PUPA
5V_CAP
CBSENSE DRAIN_SENSE SLEW VGATE_HS
Sense Gate Control
PUPB Polarity
PUPB
Memory Configuration, Status, Command Registers
Time Slot Control
PUPC Polarity
PUPC
Interface Virtual Address
PUPD Polarity
PUPD
Programmable Fault Conditions
FEEDA Supply Arbitration
2.5V
FEEDB GATEA GATEB
ENTS
Filter
Prog Prog Hyst
Glitch Filter
Prog Prog Hyst
UV/OV Filter
FAULT#
Fault Latch
RESET#
Glitch Filter
Duty Cycle Timer
Figure Block Diagram
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
DESCRIPTION
Type Name PD0, Description pins active high, logic level inputs. Protection diodes allow them overdriven when used conjunction with series limiting resistor. pins have internal pull-down current sink 10uA typical. RESET# used clear latched fault conditions. When this asserted, VGATEX PUPX outputs immediately disabled. Refer section Circuit Breaker Operation more information. RESET# internal pull-up current source 5V_CAP 10uA typical. serial clock input. bidirectional serial data port. PUPX outputs programmable active high/low open drain converter enable pins. They used programmable sequence positions switch load enable DC/DC converter after programmable delay, tPGDn. voltage these pins cannot exceed relative VSS. FAULT# open-drain, active-low output that indicates fault status device. device's Status Register polled determine more detailed information about fault condition. This connected negative side supply. circuit breaker sense input used detect over-current conditions across external, value sense resistor (RS) tied series with Power MOSFET. voltage drop greater than (programmable level) across resistor longer than tCBD trips circuit breaker. programmable Quick-Tripsense point also available. used under-voltage supply monitor, typically conjunction with external resistor ladder. VGATE_HS enabled when input disabled when Vuv-Vuvhys. optional programmable filter delay also available input. used over-voltage supply monitor, typically conjunction with external resistor ladder. VGATE_HS disabled when enabled when Vov-Vovhys. filter delay also available input. Enable/Temperature Sense input master enable input. EN/TS less than 2.5V, VGATE outputs disabled. capacitor connected this controls VGATE_HS Slew Rate. Connect -48V feed using series 100k resistor. voltage this compared with voltage FEEDA internally supply arbitration logic determine which voltage will used.
RESET#
PUPA, PUPB, PUPC, PUPD FAULT#
CBSENSE
EN/TS SLEW_CNTL FEEDB
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
DESCRIPTION (CONTINUED)
Type Name FEEDA Description Connect -48V feed using series 100k resistor. voltage this compared with voltage FEEDB internally supply arbitration logic determine which voltage will used. DRAIN SENSE input monitors voltage drain external power MOSFET switch with respect VSS. internal 10µA source pulls DRAIN SENSE signal towards 5V_CAP level. DRAIN SENSE must held below 2.5V enable PUPX outputs. External capacitor input used filter device's internal operating supply. Also hold Capacitor sequence down filter power glitches. VGATE_HS output activates external power MOSFET switch. This signal controls inrush current modulating gate Swap MOSFET device. supplies programmable current output which allows easy adjustment MOSFET turn-on slew rate. This controls gate active FEEDB. This controls gate active FEEDA This positive supply input. internal shunt regulator limits voltage this approximately with respect VSS. resistor must placed series with limit regulator current application schematics). Active-high, logic level input that used indicate when converter controlled PUPD fully powered. hold-off timer allows secondary side (which powered initially) control shut down optoisolator. Figures Active-high, logic level input that used indicate when converter controlled PUPC fully powered. hold-off timer allows secondary side (which powered initially) control shut down optoisolator. Figures Active-high, logic level input that used indicate when converter controlled PUPB fully powered. hold-off timer allows secondary side (which powered initially) control shut down optoisolator. Figures Active-high, logic level input that used indicate when converter controlled PUPA fully powered. hold-off timer allows secondary side (which powered initially) control shut down optoisolator. Figures
DRAIN SENSE 5V_CAP VGATE_HS
VGATEB VGATEA
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
PACKAGE CONFIGURATION
VGATEA VGATEB
RESET# PUPA PUPB
VGATE_HS 5V_CAP DRAIN SENSE FEEDA FEEDB SLEW_CNTL EN/TS
PUPC
PUPD
FAULT#
Figure
RESET# PUPA PUPB PUPC PUPD FAULT# VGATEA VGATEB VGATE_HS 5V_CAP DRAIN SENSE FEEDA FEEDB SLEW_CNTL EN/TS CBSENSE
Figure SOIC
Summit Microelectronics,
2080 07/21/05
CBSENSE
SMH4814
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias -55°C 125°C Power Supply Current (IDD) Storage Temperature -65°C 150°C Lead Solder Temperature seconds) 300°C Terminal Voltage with Respect VSS: 5V_CAP. -0.3 V12, SDA, SCL, CBSENSE, EN/TS, FAULT#, -0.3 +15V VGATE_HS, VGATEA, VGATEB PUPA, PUPB, PUPC, PUPD -0.3 V12+0.7V PD1, PD0, FBA, FBB, FBC, FBD, FEEDA, FEEDB, RESET#, DRAIN SENSE, SLEW_CNTL -0.3 5V_CAP+0.7V Open Drain Output Short Circuit Current 100mA Junction Temperature 150°C Rating JEDEC 2000V Latch-Up testing JEDEC ±100mA
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial) -40°C 85°C (Commercial) -5°C 70°C Supply Voltage (V12) (IDD .11V Thermal Resistance (JA) 28-pin 79°C/W Thermal Resistance (JA) 28-pin SOIC 80°C/W
Moisture Classification Level (MSL J-STD-020
Reliability Characteristics: Data Retention Years Endurance .100,000 Cycles
Stresses listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted. voltages relative VSS. Symbol VGATEHI VGATELO VSENSE ISENSE VENTS VENTSHYST (PD) (RESET#)
Notes:
Parameter Supply Voltage Supply Current VGATEA, VGATEB, VGATE_HS High Voltage VGATEA, VGATEB, VGATE_HS Voltage Drain Sense Threshold Drain Sense Current EN/TS Threshold EN/TS Hysteresis RESET#, PD1, PD0, SCL, SDA, FBA, FBB, FBC, FAULT#, PUPA, PUPB, PUPC, PUPD
Conditions
Min.
Typ.
Max.
Units
IGATE VSENSE 2.45 2.45 -0.1 2.50 2.50
2.55 2.55
SCL, SDA, CBSENSE, EN/TS, FBA, FBB, FBC, PD1, RESET# VGATE_HS Threshold
This value resistor (see page Dropper Resistor Selection).
5V_CAP
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
OPERATING CHARACTERISTICS (Continued)
Over recommended operating conditions, unless otherwise noted. voltages relative VSS.
Programmable Functions (Note
Symbol VUVHYS VOVHYS VCBMAX VQCB IVGHS_MAX Parameter Under-Voltage Threshold Under-Voltage Hysteresis Over-Voltage Threshold Over-Voltage Hysteresis Circuit Breaker Threshold Circuit Breaker Threshold Current Regulation Level Programmable Quick Trip Circuit Breaker Threshold Voltage VGATE_HS Maximum Current Conditions Default 2.864V Default 160mV Default 3.072V Default 160mV Default 50mV Default 256mV Default VCB+25% Default 100mV Default 72µA VGATE Min. Typ. VUVHYS VOVHYS VCBMAX VQCB IVGHS_MAX Max. Units
IVGATEA/B
Programmable IVGATEA, IVGATEB
Default 50µA
IVGATEA/B
IFEED_SEL
Programmable FEED current selected feed
Default 18µA
IFEED_SEL
IFEED_UNSEL
Programmable FEED current unselected feed
Default 26µA
IFEED_UNSEL
Notes:
Default values listed; refer Configuration Registers description range values allowed.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted. voltages relative VSS. Symbol tQTSD Parameter Quick Trip Shutdown Conditions overdrive start VGATE_HS turn-off Min. Typ. Max. Units
Programmable Functions (Note
Symbol tCBD tPGD tCYC tPUOVF tPDD tSTT tGLITCH tPCR
Notes:
Parameter
Conditions
Min.
Typ. tCBD tPGD tCYC tPUOVF tPDD tSTT tGLITCH tPCR
Max.
Units
Programmable Over-Current Glitch Filter Default 40µs Programmable Power Good Delay Default 64ms Circuit Breaker Cycle Mode Cycle Time Default 5.4s
Programmable Under/Over-Voltage Filter Default 64ms Programmable Detect Delay Programmable Sequence Termination Timer Glitch Filter Programmable Current Regulation Default 64ms Default 64ms Default 40µs Default 64ms
Default values listed; refer Configuration Registers description range values allowed.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
2-WIRE SERIAL INTERFACE OPERATING CHARACTERISTICS 100/400kHz
Over recommended operating conditions, unless otherwise noted. voltages relative VSS. Figure Timing Diagram. 100kHz 400kHz Symbol Description Conditions Units fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT Clock Frequency Clock Period Clock High Period Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge Data Valid Data Output Hold Time Rise Time Fall Time Data Setup Time Data Hold Time Noise Filter Write Cycle Time Noise suppression Memory Array valid (cycle (cycle n+1) change
Note Note Before Transmission Note
1000
1000
Note: Guaranteed Design.
TIMING DIAGRAMS
SU:SDA
(IN)
tHD:SDA
tHIGH
(For rite Operation nly) tLOW tSU:DAT tSU:STO tBUF
HD:DAT
(OUT)
Figure Basic serial interface timing diagram Interface Memory timing. table above lists timing parameters. data transferred during each clock pulse. Note that data must remain stable when clock high.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
TIMING DIAGRAMS (CONTINUED)
PUPA <tSTT PUPB PUPC <tSTT PUPD tPGD2 <tSTT tPGD3 tPGD0 tPGD1 tPGD2
Figure SMH4814 cascade sequencing supplies then monitoring fault conditions.
PUPA <tSTT PUPB PUPC <tSTT PUPD tPGD2 tPGD3 <tSTT tPGD1 tPGD0 tPGD2
Figure SMH4814 cascade sequencing supplies off.
Summit Microelectronics, 2080 07/21/05
SMH4814
Preliminary Information
TIMING DIAGRAMS (CONTINUED)
Power-on Timing Figure illustrates some power sequences, including differentials their reference, Power Good cascading. Refer table page more information tPDD tCBD timings.
11VV1213V <tPUOVF
<VOV
>VUV
tPDD
V12-VGT VGATE_HS
DRAIN SENSE
2.5VREF
Programmable level CBSENSE <tCBD tPGD0 PUPX tPGD1 PUPX tPGD2 PUPX tPGD3 PUPX
Figure SMH4814 Power-On Sequences
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION
General Purpose EEPROM SMH4814 bytes general-purpose EEPROM memory available user. These 2kbits EEPROM accessible interface slave address 1010 1011, beginning word address (0x000) ending word address (0x0FF). Refer 2-Wire Serial Interface section more information. Configuration Registers There also user-programmable, non-volatile configuration registers SMH4814. configuration registers accessible interface same slave address general purpose EEPROM, beginning word address (0x100) ending address (0x113). These locations will referred throughout this document registers through R13. Individual bits ranges bits will further denoted with square brackets. example, R00[3:0] refers Register 0x100, bits through R0D[6,2] refers Register 0x10D, bits configuration registers responsible setting programmable parameters described within this document. Refer Configuration Register Tables more detailed information about register settings. Detection There several enabling inputs that allow host control SMH4814. Detect signals (PD1 PD0) active high enables that generally used indicate that add-in circuit card properly seated. These inputs must held high pin-detect delay period tPDD before power-up sequence initiated. This typically done clamping inputs through implementation ejector switch, alternatively through staggered pins card-cage interface.
-48V CHASSIS CARD
100k -48V
SMH4814
-48V 100k Short Pins
Figure Inputs, Physical Offset
shorter pins, arranged opposite ends connector, force card fully seated before both detects enabled. important limiting resistors (typically 100k series with inputs avoid damaging them. internal shunt prevents voltage those pins from reaching unsafe levels. inputs disabled using R0F[2]; however, even Detect inputs disabled tied directly device must still wait detect delay period before starting detect delay (tPDD) timing parameter controlled bits R00[3:0]. Refer Register detailed programming information. EN/TS Input EN/TS input provides active high comparator input that used master enable temperature sense input. This input signal must exceed 2.5V enable turn-on sequence. EN/TS drops below 2.5V sense level, device configured FAULT# output not, initiates either Forced Shutdown Power Down sequence. These options using R0D[6,2].
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Under-/Over-Voltage Sensing Under-Voltage (UV) Over-Voltage (OV) inputs provide comparators that conjunction with external resistive divider ladder sense whether host supply voltage within user-defined limits. power-up sequence initiated when input rises above input remains below period least tPDD (Pin Detect Delay time). tPDD filter helps prevent spurious start-up sequences while card being inserted. default values 2.86V 3.07V, respectively. This ratio allows input tied together accommodates standard telecom over under voltage input ranges. Alternatively, programmed independently four values, determined R09[3:0]. Under-/Over-Voltage Filtering falls below Vuv-Vuvhys rises above period time determined UV/OV glitch filter (R06[7:6]), PUPX VGATEX outputs disabled immediately. Alternatively, SMH4814 configured that out-of- tolerance condition does shut output immediately. Instead, filter delay inserted that only sustained under-voltage over-voltage conditions longer than filter delay time (tPUOVF Figure shut output. filters enabled with bits respectively, register R0F. Refer R04[3:0] more information filter delay options. Figure shows sample waveform when under-voltage filter enabled.
Vuv-Vuvhys
tPUOVF
VGATE_HS
Figure Example Under-Voltage Filter Timing Under-/Over-Voltage Latching default, out-of-tolerance condition will shut outputs until offending condition goes away. that point, entire turn sequence start over. However, over under voltage condition also programmed cause FAULT condition, using R0D[1:0]. this case FAULT# output asserted, user required reset Fault condition before device will through another power-up sequence. Under-/Over-Voltage Hysteresis Under Over Voltage comparator inputs configured with programmable level hysteresis using Register R08. falling voltage compare level from 32mV 512mV below nominal value, steps 32mV. rising voltage compare level fixed either Vov, depending input. default under over voltage hysteresis level 160mV. Soft Start Slew Rate Control Once preconditions powering DC/DC controllers have been explained previous sections, SMH4814 provides means soft start external power MOSFET. important limit in-rush current prevent damage add-in card disruptions host power supply.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
SMH4814 provides three methods controlling inrush current. first method entails limiting current being sourced from VGATE_HS pin. maximum current this (IVGHS_MAX) programmable value from 128µa (nominal), based register R0E[3:0]. importance having current-limited gate drive that slew rate load voltage roughly equivalent slew rate gate drain capacitance, once gate source potential reached FET's threshold voltage. This slew rate (computed dividing gate current gate-drain capacitance) easily modified adjusting gate-drain capacitance, which discrete component capacitance built into structure, adjusting gate current. second tool limiting inrush current based further controlling current being sourced from VGATE_HS. SLEW_CNTL used cause gate current linearly ramp from maximum amount (described above) following manner. power-up, SLEW_CNTL clamped VSS; when VGATE_HS enabled, SLEW_CNTL outputs drawn from internal supply. register high, then current VGATE_HS reduced ratio voltage SLEW_CNTL divided 2.5V. Once SLEW_CNTL exceeds 2.5V, then current limited IVGHS_MAX. advantage ramping gate current from zero maximum amount that corresponding inrush current will follow similar pattern, which lead less disruption overall system. rate which gate current increases determined size external capacitor connected SLEW_CNTL pin. third method controlling inrush current based SMH4814's Current Regulation feature. Described more detail later section, this feature regulates current through FET, therefore voltage across external sense resistor measured CBSENSE input, controlling VGATE_HS. Normally, this operation attempts keep CBSENSE from exceeding programmable threshold voltage, VCR; however, when load being initially powered, regulation point which CBSENSE held gradually ramped from zero VCR. This feature enabled setting register high, selecting ratio using R0E[7:6]. this case, CBENSE regulated voltage SLEW_CNTL times ratio determined R0E, value VCR. methods described here controlling inrush current used separately together. Once voltage SLEW_CNTL within p-ch threshold voltage 5V_CAP, must remain above this voltage. Load Control Sequencing Secondary Supplies PUPA through PUPD output pins used enable external DC/DC controllers. Once load been fully powered, sequencing begin. SMH4814 checks that conditions have been indicate that load fully powered: DRAIN SENSE input voltage must 2.5V VGATE_HS voltage must VGT. DRAIN SENSE input helps ensure that power MOSFET absorbing excessive steady state power from operating high VDS. This sensor remains active times (except when current regulation enabled). VGATE sensor makes sure that power MOSFET operating well into saturation region before allowing loads switched Once VGATE reaches this sensor latched. Outputs SMH4814 four programmable-polarity, opendrain (Power-Up Permitted) outputs that used control sequencing order DC-DC converters. After soft start process been completed load capacitance been fully charged, there four sequential time slots into which each outputs assigned (Figure given time slot have more than output assigned likewise, time slot have outputs assigned Time Slot begins after gate main soft-start fully enhanced load fully charged.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
duration each time slot programmable values ranging from 250µs 768ms. When Time Slot times out, then outputs assigned that time slot enabled. Time Slot begins when affiliated feedback pins pulled high. example, PUPA PUPC assigned Time Slot then Time Slot begins only after PUPA PUPC enabled, pulled high. there outputs assigned given time slot, then next time slot commences soon current time slot times out. This process continues until four time slots have timed feedback pins have been pulled high. this point, brick sequencing complete. device also sequences down same manner (Figure PUPx outputs have withstand capability, high voltages must connected these pins. Bipolar transistors opto-isolators used boost withstand voltage that host supply Inputs pins designed receive feedback from secondary side bricks used indicate that enabled brick powered properly. previous section described PUPX output enabling sequence when SMH4814 receives expected feedback from secondary side. This section describes what happens when stays goes unexpectedly. described above, when given time slot times out, appropriate output enabled. next time slot will commence until associated pulled high. sequence termination timer (STT) used protect against stalled Power-on sequence. This timer commences when PUPx outputs within given time slot enabled, continues running until either associated inputs high sequence termination timer times (tSTT). times before appropriate inputs high device will power down VGATE outputs. This control mechanism allows supplies that have dependencies based other voltages system cascaded properly. status registers contain bits that indicate sequence been terminated which sequence position timer timed out. Active Gate Control Throughout power-up process, Active-ORing FET's kept off. Current flows means body diodes those MOSFET devices. Once outputs SMH4814 have been enabled, Active-ORing FET's enabled. Initially, feed with lowest negative potential selected power load. determine lowest supply, on-board comparator determines which input (FEEDA FEEDB) lower. Since actual feeds both below drop across body diodes, FEEDA FEEDB inputs level shifted delivering current across dropper resistor (typically 100k). FEED output current programmable from 10µA-25µA, using R07[7:4]. VGATE output corresponding lowest FEED input driven V12. FEEDA FEEDB inputs continually monitored lowest input level that corresponding power feed will used energize load. However, once Active gates been driven high, level shifting currents being delivered FEEDA FEEDB skewed offer some degree hysteresis. current driven non-selected feed increased anywhere from 15µA, determined R07[3:0]. effect increased current make non-selected feed appear have even higher potential, thereby offering level hysteresis. hysteresis will help reduce amount unnecessary switching between feeds cases where potentials very close together where there excessive noise feeds. When determined that selected feed longer most appropriate power load, corresponding VGATE output immediately switched powerful pull-down device. complementary output then enabled using current limited pull-up. amount current selectable from 10µA -200µA using R05[5:4].
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Circuit Breaker Operation SMH4814 provides highly configurable method detecting controlling over-current events. sustained over-current condition cause physical damage card edge connector, load circuitry, even disrupt operation other cards system. detect such over-current conditions, series sense resistor (RS) connected between MOSFET source (which tied CBSENSE) VSS. board's load current passes through sense resistor, CBSENSE input monitored excessive voltage drop across SMH4814 compares CBSENSE input against three important voltage levels (VCB, VQCB, VCR) takes appropriate action each successive level reached. first voltage, VCB, circuit breaker trip point, which determined R0A[7:0]. levels maximum voltage VCBMAX, which configurable voltage 128mV, 256mV, 512mV 1024mV, determined R09[5:4]. example, VCBMAX 256mV, then programmed value between 255mV, increments. (Refer Register Description more information.) CBSENSE exceeds period time longer than glitch filter delay associated with that input, tCBD (set using R06[1:0]), then device considered over-current state. Once over-current state, SMH4814 will either shut down immediately, Current Regulation option selected (R05[3]), device will begin another timer. Refer description Current Regulation more information these actions. Quick-TripCircuit Breaker second voltage level that CBSENSE input compared against Quick-TripCircuit Breaker level, VQCB. VQCB determined contents R0B[7:0], manner similar VCB. (Note that value stored complement number; refer Register Description more information.) Unlike comparator, output VQCB comparator high-speed, non-filtered signal designed shutdown MOSFET gate very quickly. Current Regulation option selected, then exceeding Quick-Trip level causes immediate shutdown outputs MOSFET gate; however, Current Regulation selected, outputs will immediately shut off. Refer description Current Regulation more information. Figure shows circuit breaker `Quick Trip' response. this figure, voltage rises above VQCB, causing VGATE deasserted.
<tCBD CBSENSE VQCB
tQTSD VGATE_HS
Figure Circuit Breaker Quick Trip Response without current regulation. Current Regulation Current Regulation mode optional feature that provides means regulate current through MOSFET programmable period time. This mode allows system "ride out" temporary disruptions that might otherwise cause traditional circuit breakers trip. Current Regulation trip point, VCR, third voltage level against which CBSENSE input compared. determined register R09[7:6] expressed percentage above level. There four choices: 12.5%, 25%, 100%. Note that Quick-Trip level VQCB should chosen fall above order Current Regulation effective. Current Regulation works modulating VGATE_HS that CBSENSE always less than equal VCR. order avoid overheating MOSFET operating linear region long, timer started whenever CBSENSE goes above VGATE_HS falls least below V12. either these conditions exist duration current regulation timer, tCR, then VGATE outputs shut down. There actually different Current Regulation timers; R00[7:4] controls timing initial VGATE_HS turn R04[7:4] controls timing subsequent current regulation events.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
case when Current Regulation enabled CBSENSE exceeds VQCB before circuitry time modulate VGATE_HS, Quick-Trip circuit assists modulation pulling down gate immediately. Rather than pull VSS, Quick-Trip circuitry also configured only pull down within one, three diode (R05[7:6]). Once CBSENSE falls back below VQCB, pull-down circuitry will shut off. this point, Current Regulation circuit will have time activate, VGATE_HS will modulated keep CBSENSE level VCR. Figure Figure illustrate current regulation function.
<tPCR VQCB CBSENSE tCBD VGATE_HS
Resetting FAULT# When circuit breaker trips and, case which current regulation enabled, tPCR times out, VGATE_HS outputs turned FAULT# driven low. Other events also configured cause Fault, determined R0D[3:0] R10[7:4]. Once Fault occurred, SMH4814 configured (using R05[2]) either restart after programmable cooling period tCYC (Figure 13), configured stay latched until Fault manually reset (Figure 14). duty cycle timeout period tCYC using R03[7:4] range from 21.5s. Fault condition manually reset driving RESET# low, through Command Register.
tCBD CBSENSE tCBD
tCYC VGATE_HS
Figure Current Regulation With Recovery
tPCR VQCB CBSENSE VGATE_HS
Figure Circuit Breaker Duty Cycle Operation with RESET# High
tCBD
CBSENSE
tPDD VGATE_HS
tCBRST RESET#
Figure Current Regulation Without Recovery
Figure Circuit Breaker Reset with RESET#
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Command Register: command register (Table provides useful software functionality SMH4814. accessed using 1001 slave address, word address 0x000. invoke functions command register, simply write appropriate position. other bits should receive "0". Note that invoking contradictory commands, such Power Down Power simultaneously will cause indeterminate results. following table describes command byte: Description Clear Fault Check Fuse Clear Check Short Forced Shut Down Power Down Power Serial Interface SMH4814 uses industry standard I2C, 2-wire serial data interface. This interface provides access general purpose EEPROM, command status registers, configuration registers. interface address inputs (determined R0F[7:6]), allowing four devices same bus. This allows multiple devices same board multiple boards system controlled with signals; SCL. Device configuration utilizing Windows based SMH4814 graphical user interface (GUI) highly recommended. software available from Summit website (www.summitmicro.com/). Using conjunction with this datasheet, simplifies process device prototyping interaction various functional blocks. programming Dongle (SMX3200) available from Summit communicate with SMH4814. Dongle connects directly parallel port programs device through cable using protocol. Status/Fault Registers: There three Status/Fault Registers, accessed slave address 1001 with address low, word address 0x02-0x04. These registers generally status registers, giving user current state device. However, when fault occurs, state device becomes latched, allowing user access state part time fault. Once latched into Fault state, only these registers back Status registers command register clear fault. Refer Status/Fault Register Tables (page more detailed information about meaning each bit.
Table Command Register
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
100k
-48V Ret.
0.1µF
6.8k 1/2W
VIN-
5V_CAP
ON/OFF
Detect
RPD1
100K
ON/OFF
VIN+
VOUT+ DC-to-DC Converter VOUT-
VIN+ PUPA PUPB DRAIN SENSE PUPC VIN-
VOUT+ DC-to-DC Converter VOUT-
SLEW_CNTL
SMH4814
CBSENSE FEEDA FEEDB VGATEA VGATEB VGATE_HS
-48V -48V
RSHS
VINPrimary
ON/OFF
RGHS
100k
VIN-
ON/OFF
Detect
RPD0
PUPD
VIN+
VOUT+ DC-to-DC Converter VOUT-
Figure Full Application Schematic with isolation components shown. value chosen single 1/2W resistor shown parallel combination smaller 1/10W resistors shown Figure 15B.
0.01µF
VIN+
VOUT+ DC-to-DC Converter VOUTSecondary
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Operating High Voltages breakdown voltage external active passive components limits maximum operating voltage SMH4814 hot-swap controller. Components that must able withstand full supply voltage are: input output decoupling capacitors, protection diode series with DRAIN SENSE pin, power MOSFET switch capacitor connected between drain gate, high-voltage transistors connected power good outputs, dropper resistor connected controller's pin. Over-Voltage Under-Voltage Resistors Figure 15A, three resistors (R1, connected inputs must capable withstanding maximum supply voltage several hundred volts. resistor values should chosen that input reaches corresponding trip point (Vuv Vov) when incoming power feed reaches high operational limit. input impedance very high, large value resistors used resistive divider. divider resistors should high stability, metal-film resistors keep under-voltage over-voltage trip points accurate. Telecom Design Example hot-swap telecom application power supply with -25% +50% tolerance (i.e., supply vary from 72V). formula calculating follows. First, peak current, IDMAX, must specified resistive network. value current arbitrary, cannot high (self-heating becomes problem), (the value becomes very large, leakage currents reduce accuracy trip points). value IDMAX should 200µA best accuracy trip points. value 250µA IDMAX used illustrate following calculations. With (2.864V) being over-voltage trip point, calculated formula: Substituting: 2.864V 11.46 250µA closest standard resistor value 11.8k Next minimum current that flows through resistive divider, IDMIN, calculated from ratio minimum maximum supply voltage levels:
VSMA
Substituting:
250µ
value calculated from IDMIN:
under-voltage trip point, also 2.864V. Substituting:
2.864V
closest standard resistor value 825k Then calculated:
Substituting:
2.864V 11.8 125µ
Excel spread sheet available (http://www.summitmicro.com/) contact Summit simplify resistor value calculations tolerance analysis
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Dropper Resistor Selection SMH4814 powered from high-voltage supply dropper resistor, dropper resistor must provide SMH4814 (and loads) with sufficient operating current under minimum supply voltage conditions, must allow maximum supply current exceeded under maximum supply voltage conditions. dropper resistor value calculated from: circumstances where input voltage swing over wide range (e.g., from 100V) maximum current exceeded. these circumstances necessary Zener diode between handle wide current range. Zener voltage should below nominal regulation voltage SMH4814 that becomes primary regulator. MOSFET VDS(ON) Threshold drain sense input SMH4814 monitors voltage drain external power MOSFET switch with respect VSS. When MOSFET's below user-defined threshold MOSFET switch considered VDS(ON)THRESHOLD adjusted using resistor, VDS(ON)THRESHOLD calculated from:
(ON)T HRESHO SENSE (ISE
where VSMIN lowest operating supply voltage, VDDMAX upper limit SMH4814 supply voltage, minimum current required SMH4814 operate, ILOAD additional load current from 2.5V outputs between VSS. Calculate minimum wattage required from:
VDDM
where VDDMIN lower limit SMH4814 supply voltage, VSMAX highest operating supply voltage. dropper resistor value should chosen such that minimum maximum specifications SMH4814 maintained across host supply's valid operating voltage range. First, subtract minimum SMH4814 from voltage, divide minimum value. Using this value resistance find operating current that would result from running high supply voltage verify that resulting current less than maximum current allowed. some range supply voltage chosen that would cause maximum specification violated, then external zener diode with breakdown voltage ~12V should used across VDD. example choosing proper value, assume host supply voltage ranges from 72V. largest dropper resistor that used (36V-11V)/3mA 8.3k. Next, confirm that this value also works high end: (72V-13V)/8.3k 7.08mA, which less than 8mA.
VDS(ON)THRESHOLD varies over temperature temperature dependence ISENSE. calculation below gives VDS(ON)THRESHOLD under worst case condition 85°C ambient. Using 100k resistor gives:
VDS(ON)TH RESHOLD 2.5V (15µA 100k)
voltage drop across MOSFET switch sense resistor, VDSS, calculated from:
VDSS SON)
where MOSFET drain current, circuit breaker sense resistor RDSON MOSFET resistance.
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2080 07/21/05
SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Figure ATCAapplication Schematic
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2080 07/21/05
SMH4814
Preliminary Information
2-WIRE SERIAL INTERFACE
Programming Information Interface interface standard two-wire serial protocol that allows communication between integrated circuits. data line (SDA) bidirectional I/O; clock line (SCL) runs speeds 400kHz. line must connected positive logic supply through pull-up resistor located bus. Start Stop Conditions Both pins remain high when busy. Data transfers between devices initiated with Start condition. high-to-low transition input while high defined Start condition. low-to-high transition while high defined Stop condition. Figure shows timing diagram start stop conditions. Acknowledge Data always transferred bytes. Acknowledge (ACK) used indicate successful data transfer. transmitting device releases after transmitting eight bits. During ninth clock cycle Receiver pulls line acknowledge that received eight bits data. This shown callout Figure When last byte been transferred Master during read SMH4814, Master leaves high Acknowledge (NACK) cycle. This causes SMH4814 part stop sending data, Master issues Stop clock pulse following NACK. Figure shows Acknowledge timing.
Figure Acknowledge Timing Read Write Figure Start Stop Conditions Master/Slave Protocol master/slave protocol defines device that sends data onto transmitter, device that receives data receiver. device controlling data transmission called Master, controlled device called Slave. cases SMH4814 referred Slave device since never initiates data transfers. data transferred during each clock pulse. data line must remain stable during clock high time, because change data line while high interpreted either Start Stop condition. first byte from Master always made 7bit Slave address Read/Write (R/W) bit. tells Slave whether Master reading data from writing data Read, Write). first four seven address bits called Device Type Identifier (DTI). case SMH4814, next bits Address values used distinguish multiple devices common bus. seventh slave address represents ninth word address. SMH4814 issues Acknowledge after recognizing Start condition DTI. Figure shows example typical master address byte transmission.
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Preliminary Information
2-WIRE SERIAL INTERFACE (CONTINUED)
Random Access Read Random address read operations allow Master access memory location random fashion. This operation involves two-step process. First, Master issues Write command which includes Start condition Slave address field (with Write) followed address word read. This procedure sets internal address counter SMH4814 desired address. After word address Acknowledge received Master, immediately reissues Start condition followed another Slave address field with Read. SMH4814 responds with Acknowledge then transmits data bits stored addressed location. this point, Master sets line NACK generates Stop condition. SMH4814 discontinues data transmission reverts standby power mode. Sequential Reads Sequential reads initiated either current address read random access read. first word transmitted with other byte Read modes (current address byte Read random address byte Read). However, Master responds with Acknowledge, indicating that requires additional data from SMH4814. SMH4814 continues output data each Acknowledge received. Master sets line NACK generates Stop condition. During sequential Read operation internal address counter automatically incremented with each Acknowledge signal. Read operations address bits incremented, allowing entire array read using single Read command. After count last memory address address counter rolls over memory continues output data.
Figure Transmission
Typical
Master
Address
Byte
During read Master device, SMH4814 transmits eight bits data, then releases line, monitors line Acknowledge signal. Acknowledge detected, Stop condition generated Master, SMH4814 continues transmit data. Acknowledge detected (NACK), SMH4814 terminates subsequent data transmission. read transfer protocol shown Figure
Figure Read Protocol During Master write, SMH4814 receives eight bits data, then generates Acknowledge signal. device continues generate condition until Stop condition generated Master. write transfer protocol shown Figure
Figure Write Protocol
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
2-WIRE SERIAL INTERFACE (CONTINUED)
Figure Typical Memory Write Random Read Operations Register Access SMH4814 contains 2-wire interface register access explained previous section. This highly configurable, while maintaining industry standard protocol. SMH4814 responds selectable Device Type Addresses: 1010BIN, generally assigned NV-memories default address SMH4814, 1011BIN. Device Type Address assigned programming Register 0x0F. configuration registers locked setting register 0x0F high. This one-time, non-reversible operation. SMH4814 virtual address pins, A[2:1] (set with R0F[7:6]), associated with 2-wire bus. SMH4814 configured respond only proper serial data string Device Type Address specific addresses (Register 0x0F, cleared). Device Type Address address (Register 0x0F, set).
Slave Address
Address
Register Type
1001BIN
Command Status Registers,
1010BIN 1011BIN
Bits General-Purpose Memory Configuration Registers
Table Address bytes used SMH4814.
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Preliminary Information
PROGRAMMING INFORMATION (CONTINUED)
Master
Address
Configuration Register Address
Data
Slave
Figure Configuration Register Byte Write
Master
Address
Configuration Register Address
Address
Slave
Master Slave
Data
Data
Figure Configuration Register Read
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
PROGRAMMING INFORMATION (CONTINUED)
Slave
Master
Address
Configuration Register Address
Data
Figure General Purpose Memory Byte Write
Slave
Master
Address
Configuration Register Address
Address
Master Slave
Data
Data
Figure General Purpose Memory Read
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
PROGRAMMING INFORMATION (CONTINUED)
Slave
Master
Address
Command Register Address
Data
Figure Command Register Write
Slave Status Register Address
Master
Address
Address
Master Slave
Data
Data
Figure Status Register Read
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
DEVELOPMENT HARDWARE SOFTWARE
user obtain Summit SMX3200 programming system device prototype development. SMX3200 system consists programming Dongle, cable WindowsGUI software. ordered website from local representative. latest revisions software application brief describing SMX3200 available from website (www.summitmicro.com). SMX3200 programming Dongle/cable directly between PC's parallel port application. device then configured intuitive graphical user interface drop-down menus. interfaces target on-screen employing Windows software will generate data send serial format that directly downloaded SMH4814 programming Dongle cable. example connection interface shown Figure When design prototyping complete, software generate data file that should transmitted Summit approval. Summit will then assign unique customer code program production devices before final electrical test operations. This will ensure proper device operation application.
-48V (0V) 1N4148
view straight 0.1" closed-side connector. SMX3200 interface cable connector Reserved Reserved Reserved
SMH4814
0.1µF
-48V
Figure SMX3200 Programmer serial connections program SMH4814. Caution: Damage occur when connecting dongle system utilizing earth-connected positive terminal.
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
CONFIGURATION REGISTERS Configuration Registers:
There user programmable configuration registers SMH4814. following tables describe configuration register bits detail. cases where timer used, refer Timers Table description codes required each timeout selection.
Table Timers timers configured following sixteen choices: Code 0000 0001 0010 0011 Timer (ms) 0.25 Code 0100 0101 0110 0111 Timer (ms) Code 1000 1001 1010 1011 Timer (ms) Code 1100 1101 1110 1111 Timer (ms)
Register Initial Current Regulation power-on delay.
Bits D[7:4] control Initial Current Regulation Timer (defines amount time current regulation allowed during initial power-on). Bits D[3:0] control Detect delay (defines time from when PD's enabled valid until VGATE_HS allowed turn Register Action Initial Current Regulation Timer 64ms, Table Detect Delay 64ms, Table
Register -Sequence position.
Bits D[7:4] control Time Slot (time from high second allowed active). Bits D[3:0] control Time Slot which time from when fully when first goes active. Register Action Time Slot Time from high second PUPX allowed active- 64ms, Table Time Slot Time from high first PUPX allowed active 64ms, Table
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register -Time Slots.
Bits D[7:4] control Time Slot (time from high second allowed active). Bits D[3:0] control Time Slot (time from fully first allowed active). timer table codes. Register Action Time Slot Time from high fourth PUPX allowed active 64ms, Table Time Slot Time from high third PUPX allowed active 64ms, Table
Register -Duty Cycle Sequence Termination Timers.
Bits D[7:4] control Duty Cycle Timer (restart time after fault; short circuit detect cycle time; multiply standard times 28X). Bits D[3:0] control Sequence Termination Timer (defines time from active until must high). Register Action Duty Cycle Timer defines time between when Fault occurs device attempts restart power sequence. Note that these times actually that listed table. Sequence Termination Timer time from when enabled until corresponding input must high 64ms, Table
Register -Current Regulation UV/OV Filter Timers.
Bits D[7:4] control Subsequent Current Regulation Timer (except initial power on). Bits D[3:0] control UV/OV Filter Timer (when enabled). Register Action Current Regulation Timer defines amount time that held linear region regulate current load 64ms, Table UV/OV Filter Time defines length time that under over voltage condition must sustained trip sensor 64ms, Table
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Pull-downs, Pull-ups, current regulation fault latch.
Bits D[7:6] control fast pull down level number diodes connected series with gate pull-down transistor Quick Trip sensor. Bits D[5:4] control GATEA/GATEB Pull-up Current. D[3] controls Current Regulation. D[2] controls Fault Latches versus Duty Cycle. Bits D[1:0] control Drain Sense Glitch Filter. Register Action Fast pull down level diodes connected series with gate pull-down transistor Quick Trip sensor. Fast pull down level diode connected series with gate pull-down transistor Quick Trip sensor. Fast pull down level diodes connected series with gate pull-down transistor Quick Trip sensor. Fast pull down level diodes connected series with gate pull-down transistor Quick Trip sensor. VGATEA/VGATEB Pull-up Current 10µa VGATEA/VGATEB Pull-up Current 50µa VGATEA/VGATEB Pull-up Current 100µa VGATEA/VGATEB Pull-up Current 200µa) Enable Current regulation. Disable Current regulation. Fault condition must manually cleared Fault cleared after Duty cycle timeout Drain Sense Glitch Filter 1µs. Drain Sense Glitch Filter 14µs. Drain Sense Glitch Filter 40µs. Drain Sense Glitch Filter 119µs.
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Glitch Filters.
Bits D[7:6] control UV/OV Glitch Filter. Bits D[5:4] control RESET# Glitch Filter. Bits D[3:2] control Glitch Filter. Bits D[1:0] control CBSENSE Glitch Filter. Register Action UV/OV Glitch Filter 1µs. UV/OV Glitch Filter 14µs. UV/OV Glitch Filter 40µs. UV/OV Glitch Filter 119µs. RESET# Glitch Filter 1µs. RESET# Glitch Filter 14µs. RESET# Glitch Filter 40µs. RESET# Glitch Filter 119µs. Glitch Filter 1µs. Glitch Filter 14µs. Glitch Filter 40µs. Glitch Filter 119µs. CBSENSE Glitch Filter 1µs. CBSENSE Glitch Filter 14µs. CBSENSE Glitch Filter 40µs. CBSENSE Glitch Filter 119µs.
Register FEEDA/B Current.
Bits D[7:4] control FEED Offset Current. Bits D[3:0] control FEED Hysteresis Current Register Action FEED Offset Current defined value this register, plus range offset current 10-25uA. default value shown here represents 18uA (8b+10). FEED Hysteresis current ranges from 0-15ua. default shown here
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register OV/UV Hysteresis.
Bits D[7:4] control Hysteresis Voltage level. Bits D[4:0] control Hysteresis Voltage level. Register Action Hysteresis ((n+1)*32), where value stored bits 7:4. Hystersis ranges from 32mV 512mV, with default value (shown here) 160mV Hysteresis ((n+1)*32), where value stored bits 7:4. Hystersis ranges from 32mV 512mV, with default value (shown here) 160mV
Register Current regulation Offsets, Current OV/UV reference voltage
Bits D[7:6] control Current Regulation Offset. Bits D[5:4] control Current Voltage. Bits D[3:2] control reference voltage range. Bits D[1:0] control reference voltage range. Register
Action Current Regulation Offset 12.5% (This percentage above Over Current trip point which current regulated) Current Regulation Offset Current Regulation Offset Current Regulation Offset 100% Current Voltage 128mV Current Voltage 256mV (default) Current Voltage 512mV Current Voltage 1.024V Reference 2.048V Reference 2.864V Reference 3.072V Reference 4.096V Reference 2.048V Reference 2.864V Reference 3.072V Reference 4.096V
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Over Current Level
Bits D[7:0] control Over Current Level. Register
Action Over Current Level Current Voltage (R09[5:4]) n/256, where value this register. default value (shown here) 50mV
Register Quick-TripOver Current Level.
Bits D[7:0] control Fast Response Over Current Level Register
Action Fast Response Over Current Level (2's complement) Current Voltage (256-n)/256. default value (shown here) 100mV.
Bits D[7:6] control PUPD Time Slot. Bits D[5:4] control PUPC Time Slot. Bits D[3:2] control PUPB Time Slot. Bits D[1:0] control PUPA Time Slot. Register Action PUPD Time Slot PUPD Time Slot PUPD Time Slot PUPD Time Slot PUPC Time Slot PUPC Time Slot PUPC Time Slot PUPC Time Slot PUPB Time Slot PUPB Time Slot PUPB Time Slot PUPB Time Slot PUPA Time Slot PUPA Time Slot PUPA Time Slot PUPA Time Slot
Register PUPX Sequence Time Slot
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Power Down Forced Shutdown, Fault Fault
These bits control given inputs affect power off. Register
Action Power Down Forced Shutdown ENTS Power Down ENTS Forced Shutdown condition: Power Down condition: Forced Shutdown condition: Power Down condition: Forced Shutdown don't FAULT FAULT ENTS don't FAULT ENTS FAULT condition: don't FAULT condition: FAULT condition: don't FAULT condition: FAULT
Register Slew Rate Control
Bits D[7:6] control PUPD Time Slot. Bits D[5:4] control PUPC Time Slot. Bits D[3:2] control PUPB Time Slot. Bits D[1:0] control PUPA Time Slot. Register
Action Scale Factor SLEW_CNTL Curr. Reg. 1/100 Scale Factor SLEW_CNTL Curr. Reg. 1/50 Scale Factor SLEW_CNTL Curr. Reg. 1/20 Scale Factor SLEW_CNTL Curr. Reg. 1/10 SLEW_CNTL Current Regulation Voltage Curr. Reg. Voltage fixed registers SLEW_CNTL Current Regulation Voltage Curr. Reg. Voltage SLEW CNTL*scale factor D[7:6] SLEW_CNTL GATE Current Ramp GATE current fixed Current SLEW_CNTL GATE Current Ramp GATE current (Max Current)*(SLEW CNTL)/2.5 GATE Current (8+(n 8))µA Largest GATE Current (8+(15 136µA Lowest GATE Current (8+(0 GATE Current (8+(11 96µA
Summit Microelectronics,
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Interface Control
Register
Action Virtual Address Virtual Address Virtual Address Virtual Address Configuration lockout unlocked Configuration lockout locked Respond only respond virtual address match Respond addresses Slave Address 1010 Slave Address 1011 Enable PD's Disabled Enable PD's Enabled Enable filter delay Disabled Enable filter delay Enabled Enable filter delay Disabled Enable filter delay =-Enabled
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Power Down Forced Shutdown, Fault Fault
Register Action Shorted Detection disabled Shorted sets fault Shorted causes power down Shorted causes forced shutdown Blown Fuse Detection disabled Blown sets fault Blown causes power down Blown causes forced shutdown Enable Fuse Check High (works conjunction with D[5:4]) Disable Fuse Check High (works conjunction with D[5:4]) Disable Periodic Fuse Checking Enable Periodic Fuse Checking Short Circuit Level 256V (defines amount Drain Sense move during Short Detect) Short Circuit Level 512V (defines amount Drain Sense move during Short Detect) Short Circuit Level 1.024V (defines amount Drain Sense move during Short Detect) Short Circuit Level 2.048V (defines amount Drain Sense move during Short Detect)
Register polarity, Power-up command.
Register Action Command Required Power-Up Command Required Power-Up Power Up/Down Configuration PUPD polarity active PUPD polarity active high PUPC polarity active PUPC polarity active high PUPB polarity active PUPB polarity active high PUPA polarity active PUPA polarity active high
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SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register Write protect Write lockout, feedback control settings. Register
Action Used Power-up (0-don't 1-set Power-up (0-don't 1-set Write Lockout allows writes config memory) Write Lockout prevents writes config memory enable disable input enable enable input enable disable input enable enable input enable disable input enable enable input enable disable input enable enable input
Fault/Status Registers
following tables describe bits within Fault/Status Registers. When Register 0x04 (Slave address 1001) low, then data within these registers represents real-time state part. When high, then these registers represent data that latched time that Fault occurred. There three Status/Fault Registers, accessed slave address 1001 with address low, word address 0x02-0x04. Register 0x02 Description PUPD PUPC PUPB PUPA Regsiter 0x03 Description GATEB GATEA Over-Current Fault ENTS Fault Fault Fault Fault Regsiter 0x04 Description Fault Register Latched Write Protect Status reserved reserved Fault reserved reserved reserved
Summit Microelectronics,
2080 07/21/05
SMH4814
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS SMH4814NC-184
Register
Contents
Register
Contents
default device ordering number SMH4814NC-184, programmed described above tested over commercial temperature range.
Summit Microelectronics,
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SMH4814
Preliminary Information
PACKAGING
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Preliminary Information
PACKAGING SOIC
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SMH4814
Preliminary Information
PART MARKING
SUMMIT SMH4814N Annn
Summit Part Number
Status Tracking Code (Blank, 02,.) (Summit Use)
AYYWW
Date Code (YYWW) tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements)
Drawing scale
Product Tracking Code (Summit use)
ORDERING INFORMATION SMH4814
Customer specific requirements contained suffix such code, code revision, etc.
Summit Part Number Package Lead SOIC
Part Number Suffix (see page
Temp Range C=Commercial Blank=Industrial
NOTICE
NOTE NOTE This Preliminary Information data sheet that describes Summit product currently pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves right make changes products proposed this publication. SUMMIT Microelectronics, Inc. assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein reflect representative operating parameters, vary depending upon user's specific application. While information this publication been carefully checked, SUMMIT Microelectronics, Inc. shall liable damages arising result error omission. SUMMIT Microelectronics, Inc. does recommend products life support aviation applications where failure malfunction product reasonably expected cause failure either system significantly affect their safety effectiveness. Products authorized such applications unless SUMMIT Microelectronics, Inc. receives written assurances, satisfaction, that: risk injury damage been minimized; user assumes such risks; potential liability SUMMIT Microelectronics, Inc. adequately protected under circumstances. Revision This document supersedes previous versions. Please check Summit Microelectronics, Inc. site data sheet updates. Copyright 2005 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER DIGITAL WORLDI2C trademark Philips Corporation. PICMG, AdvancedTCA, CPCI ATCA trademarks Industrial Computers Manufacturers Group (PICMG).
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Preliminary Information (See Last Page) Dual Feed Active-ORing Pr

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