SPNS106 SEPTEMBER 2005 High-Performance Static CMOS Technology TM
|
|
|
Top Searches for this datasheet
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMITM) 24-MHz System Clock (48-MHz Pipeline) Independent 16/32-Bit Instruction Open Architecture With Third-Party Support Built-In Debug Module Integrated Memory 288K-Byte Program Flash Banks With Contiguous Sectors 16K-Byte Static (SRAM) Memory Security Module (MSM) JTAG Security Module Operating Features Low-Power Modes: STANDBY HALT Industrial Temperature Range 470+ System Module 32-Bit Address Space Decoding Supervision Memory/Peripherals Digital Watchdog (DWD) Timer Analog Watchdog (AWD) Timer Enhanced Real-Time Interrupt (RTI) Interrupt Expansion Module (IEM) System Integrity Failure Detection Breaker Direct Memory Access (DMA) Controller Control Packets Channels Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler Multiply-by-8 Internal ZPLL Option ZPLL Bypass Mode Communication Interfaces: Serial Peripheral Interfaces (SPIs) Programmable Baud Rates Serial Communication Interfaces (SCIs) Selectable Baud Rates Asynchronous/Isosynchronous Modes Class Serial Interface (C2SIb) Normal 10.4 Kbps Mode 41.6 Kbps Standard Controllers (SCC)
16-Mailbox Capacity Fully Compliant With Protocol, Version 2.0B Three Inter-Integrated Circuit (I2C) Modules Multi-Master Slave Interfaces Kbps (Fast Mode) 10-Bit Address Capability High-End Timer Lite (HET) Programmable Channels: High-Resolution Pins High-Resolution Share Feature (XOR) High-End Timer 64-Instruction Capacity External Clock Prescale (ECP) Module Programmable Low-Frequency External Clock (CLK) 12-Channel 10-Bit Multi-Buffered (MibADC) 64-Word FIFO Buffer Single- Continuous-Conversion Modes 1.55 Minimum Sample/Conversion Time Calibration Mode Self-Test Features Flexible Interrupt Handling Expansion Module (EBM) (PGE only) Supports 16-Bit Expansion Memory Interface Mappings Expansion Pins Dedicated General-Purpose (GIO) Pins Additional Peripheral I/Os (PGE) Dedicated General-Purpose (GIO) Pins Additional Peripheral I/Os (PZ) External Interrupts On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) 100-Pin Plastic Low-Profile Quad Flatpack Suffix)
test-access port compatible with IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port Boundary Scan Architecture specification. Boundary scan supported this device.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. ARM7TDMI trademark Advanced RISC Machines Limited (ARM). trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
TMS470R1A288 144-Pin Package (Top View) (without Expansion Bus)
ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADEVT GIOF[7] GIOF[6] GIOA[5]/INT[5] PLLDIS GIOF[5] I2C2SCL I2C2SDA GIOF[4] GIOF[3] GIOF[2] I2C1SCL I2C1SDA VCCIO VSSIO CAN1STX CAN1SRX GIOF[1] CLKOUT GIOF[0] GIOA[7]/INT[7] GIOA[6]/INT[6] GIOE[7] HET[0] ADREFHI ADREFLO VCCAD VSSAD ADIN[4] ADIN[3] ADIN[2] ADIN[1] ADIN[0] PORRST GIOC[4] GIOC[3] TEST GIOH[5]/INT[13] GIOC[2] GIOA[4]/INT[4] GIOC[1] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] GIOC[0] GIOA[1]/INT[1]/ECLK VCCIO VSSIO GIOH[0]/INT[8] GIOG[7] GIOA[0]/INT[0] GIOG[6] GIOG[5] TRST
HET[1] HET[2] GIOE[6] VCCIO VSSIO GIOE[5] HET[3] HET[4] GIOE[4] HET[5] SPI2SCS GIOE[3] SPI2ENA SPI2SIMO GIOE[2] SPI2SOMI SPI2CLK CAN2STX CAN2SRX SCI2CLK SCI2RX SCI2TX SCI1CLK GIOE[1] SCI1RX SCI1TX GIOE[0] GIOB[0] GIOD[0] GIOH[1]/INT[9] GIOH[2]/INT10] GIOD[1] GIOH[3]/INT[11] GIOH[4]/INT[12]
SPI1SCS SPI1ENA GIOG[4] SPI1CLK SPI1SIMO GIOG[3] SPI1SOMI GIOG[2] HET[6] GIOG[1] HET[7] HET[8] HET[18] TMS2 HET[20] HET[22] GIOG[0] C2SILPN C2SIRX GIOD[5] C2SITX VCCIO VSSIO GIOD[4] I2C3SCL I2C3SDA GIOD[3] OSCOUT OSCIN GIOD[2]
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
TMS470R1A288 144-Pin Package (Top View) (with Expansion Bus)
ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADEVT EBADDR[13]EBDATA[15] EBADDR[12]EBDATA[14] GIOA[5]/INT[5] PLLDIS EBADDR[11]EBDATA[13] I2C2SCL I2C2SDA EBADDR[10]EBDATA[12] EBADDR[9]EBDATA[11] EBADDR[8]EBDATA[10] I2C1SCL I2C1SDA VCCIO VSSIO CAN1STX CAN1SRX EBADDR[7]EBDATA[9] CLKOUT EBADDR[6]EBDATA[8] GIOA[7]/INT[7] GIOA[6]/INT[6] EBDATA[7] HET[0]
ADREFHI ADREFLO VCCAD VSSAD ADIN[4] ADIN[3] ADIN[2] ADIN[1] ADIN[0] PORRST EBCS[6] EBCS[5] TEST EBHOLD EBWR[1] GIOA[4]/INT[4] EBWR[0] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] GIOA[1]/INT[1]/ECLK VCCIO VSSIO EBADDR[22]/EBADDR[14] EBADDR[21]/EBADDR[13] GIOA[0]/INT[0] EBADDR[20]/EBADDR[12] EBADDR[19]/EBADDR[11] TRST
HET[1] HET[2] EBDATA[6] VCCIO VSSIO EBDATA[5] HET[3] HET[4] EBDATA[4] HET[5] SPI2SCS EBDATA[3] SPI2ENA SPI2SIMO EBDATA[2] SPI2SOMI SPI2CLK CAN2HTX CAN2HRX SCI2CLK SCI2RX SCI2TX SCI1CLK EBDATA[1] SCI1RX SCI1TX EBDATA[0] EBDMAREQ[0] EBADDR[0] EBADDR[23]/EBADDR[15] EBADDR[24]/EBADDR[16] GIOD[1] EBADDR[26]/EBADDR[18] EBADDR[25]/EBADDR[17]
SPI1SCS SPI1ENA EBADDR[18]/EBADDR[10] SPI1CLK SPI1SIMO EBADDR[17]/EBADDR[9] SPI1SOMI EBADDR[16]/EBADDR[8] HET[6] EBADDR[15]/EBADDR[7] HET[7] HET[8] HET[18] TMS2 HET[20] HET[22] EBADDR[14]/EBADDR[6] C2SILPN C2SIRX EBADDR[5] C2SITX VCCIO VSSIO EBADDR[4] I2C3SCL I2C3SDA EBADDR[3] OSCOUT OSCIN EBADDR[2]
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
TMS470R1A288 100-Pin Package (Top View)
ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADEVT GIOA[5]/INT[5] PLLDIS I2C2SCL I2C2SDA I2C1SCL I2C1SDA CAN1STX CAN1SRX CLKOUT GIOA[7]/INT[7] GIOA[6]/INT[6] HET[0] ADREFHI ADREFLO VCCAD VSSAD ADIN[4] ADIN[3] ADIN[2] ADIN[1] ADIN[0] PORRST TEST GIOH[5]/INT[13] GIOA[4]/INT[4] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] GIOA[1]/INT[1]/ECLK VCCIO VSSIO GIOA[0]/INT[0] TRST
HET[1] HET[2] VCCIO VSSIO HET[3] HET[4] HET[5] SPI2SCS SPI2ENA SPI2SIMO SPI2SOMI SPI2CLK CAN2STX CAN2SRX SCI2CLK SCI2RX SCI2TX SCI1CLK SCI1RX SCI1TX GIOB[0] GIOH[1]/INT[9] GIOH[2]/INT[10] GIOH[3]/INT[11] GIOH[4]/INT[12]
SPI1SCS SPI1ENA SPI1CLK SPI1SIMO SPI1SOMI HET[6] HET[7] HET[8] HET[18] TMS2 HET[20] HET[22] C2SILPN C2SIRX C2SITX VCCIO VSSIO I2CSCL I2C3SDA OSCOUT OSCIN
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
DESCRIPTION
TMS470R1A288 devices members Texas Instruments TMS470R1x family general-purpose 16/32-bit reduced instruction computer (RISC) microcontrollers. A288 microcontroller offers high performance utilizing high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting high instruction throughput while maintaining greater code efficiency. ARM7TDMI 16/32-bit RISC views memory linear collection bytes numbered upwards from zero. A288 utilizes big-endian format where most significant byte word stored lowest-numbered byte least significant byte highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining costs. A288 RISC core architecture offers solutions these performance cost demands while maintaining power consumption. A288 devices contain following: ARM7TDMI 16/32-Bit RISC TMS470R1x system module (SYS) with 470+ enhancements 288K-byte flash 16K-byte SRAM Zero-pin phase-locked loop (ZPLL) clock module Digital watchdog (DWD) timer Analog watchdog (AWD) timer Enhanced real-time interrupt (RTI) module Interrupt expansion module (IEM) Memory security module (MSM) JTAG security module (JSM) serial peripheral interface (SPI) modules serial communications interface (SCI) modules standard controllers (SCC) Three inter-integrated circuit (I2C) modules Class serial interface (C2SIb) module 10-bit multi-buffered analog-to-digital converter (MibADC), with input channels High-end timer lite (HET) controlling I/Os External clock prescale (ECP) Expansion module (EBM) pins (PGE only), only) functions performed 470+ system module (SYS) include: Address decoding Memory protection Memory peripherals supervision Reset abort exception management Prioritization internal interrupt sources Device clock control Parallel signature analysis (PSA) enhanced real-time interrupt (RTI) module A288 option driven oscillator clock. digital watchdog (DWD) 25-bit resettable decrementing counter that provides system reset when watchdog counter expires. This data sheet includes device-specific information such memory peripheral select assignment, interrupt priority, device memory map. more detailed functional description module, TMS470R1x System Module Reference Guide (literature number SPNU189). A288 memory includes general-purpose SRAM supporting single-cycle read/write accesses byte, half-word, word modes.
Throughout remainder this document, TMS470R1A288 will referred either full device name A288.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
flash memory this device nonvolatile, electrically erasable programmable memory implemented with 32-bit-wide data interface. When pipeline mode, flash operates with system clock frequency MHz. flash operates with system clock frequency MHz. more detailed information flash, Flash section this data sheet TMS470R1x Flash Reference Guide (literature number SPNU213). memory security module (MSM) JTAG security module (JSM) prevent unauthorized access visibility on-chip memory, thereby preventing reverse engineering manipulation proprietary code. more information, TMS470R1x Memory Security Module Reference Guide (literature number SPNU246) TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245). A288 device communication interfaces: SPIs, SCIs, SCCs, C2SI, three I2Cs. provides convenient method serial interaction high-speed communications between similar shift-register type devices. full-duplex, serial interface intended asynchronous communication between other peripherals using standard non-return-to-zero (NRZ) format. uses serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates megabit second (Mbps). ideal applications operating noisy harsh environments (e.g., industrial fields) that require reliable serial communication multiplexed wiring. C2SIb allows A288 transmit receive messages class network following J1850 standard. module multi-master communication module providing interface between A288 microcontroller I2C-compatible device serial bus. supports both Kbps Kbps speeds. more detailed functional information SPI, SCI, peripherals, specific reference guides (literature numbers SPNU195, SPNU196, SPNU197). more detailed functional information I2C, TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). more detailed functional information C2SI, TMS470R1x Class Serial Interface (C2SIb) Reference Guide (literature number SPNU214). advanced intelligent timer that provides sophisticated timing functions real-time applications. timer software-controlled, using reduced instruction set, with specialized timer micromachine attached port. used compare, capture, general-purpose I/O. especially well suited applications requiring multiple sensor information drive actuators with complex accurate time pulses. used this device high-end timer lite. fewer I/Os than usual standard HET. more detailed functional information HET, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). A288HET peripheral contains XOR-share feature. This feature allows adjacent high-resolution channels XORed together, making possible output smaller pulses than standard HET. more detailed information XOR-share feature, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). A288 device 10-bit-resolution, sample-and-hold MibADC. Each MibADC channels converted individually grouped software sequential conversion sequences. There three separate groupings, which triggered external event. Each sequence converted once when triggered configured continuous conversion mode. more detailed functional information MibADC, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). zero-pin phase-locked loop (ZPLL) clock module contains phase-locked loop, clock-monitor circuit, clock-enable circuit, prescaler (with prescale values 1-8). function ZPLL multiply external frequency reference higher frequency internal use. ZPLL provides ACLK system (SYS) module. module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), clock (MCLK), peripheral interface clock (ICLK) other A288 device modules. more detailed functional information ZPLL, TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212).
NOTE:
ACLK should confused with MibADC internal clock, ADCLK. ACLK continuous system clock from external resonator/crystal reference.
Standard J1850 Class Data Communication Network Interface
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
expansion module (EBM) standalone module that supports multiplexing functions expansion interface. more information EBM, TMS470R1x Expansion Module (EBM) Reference Guide (literature number SPNU222). A288 device also external clock prescaler (ECP) module that when enabled, outputs continuous external clock (ECLK) specified pin. ECLK frequency user-programmable ratio peripheral interface clock (ICLK) frequency. more detailed functional information ECP, TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Device Characteristics
A288 device derivative system emulation device SE470R1VB8AD. Table identifies characteristics A288 device except SYSTEM CPU, which generic. Table Device Characteristics
CHARACTERISTICS DEVICE DESCRIPTION TMS470R1A288 MEMORY number memory selects this device, Table TMS470R1A288 Memory Selection Assignment. Pipeline/Non-Pipeline 288K-Byte Flash 16K-Byte SRAM Memory Security Module (MSM) JTAG Security Module (JSM) Flash pipeline-capable. A288 implemented 16K-byte array selected memory-select signals (see Table TMS470R1A288 Memory Selection Assignment). COMMENTS
INTERNAL MEMORY
PERIPHERALS device-specific interrupt priority configurations, Table Interrupt Priority (IEM CIM). 1K-byte peripheral address ranges their peripheral selects, Table A288 Peripherals, System Module, Flash Base Addresses. CLOCK EXPANSION ZPLL Zero-pin phase-locked loop external loop filter pins. Expansion module with pins. Supports 16-bit memories. Table details. package, Port external pins, Port only external pin, Port external pins, Port external pins, Ports each have external pins, Port external pins. package, Port external pins, Port only external pin, Port external pins.
GENERAL-PURPOSE I/Os
(PGE Suffix) Suffix)
(HECC and/or SCC) (5-pin, 4-pin 3-pin) C2SIb
(3-pin) (5-pin) high-resolution (HR) SHARE feature allows even-numbered pins share next higher structures. This sharing independent whether available externally. available externally shared, then only used general-purpose I/O. more information SHARE, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). Both logic registers full 16-channel MibADC present. standard controllers
with SHARE
MibADC CORE VOLTAGE VOLTAGE PINS PACKAGES
64-Instruction Capacity 10-bit, 12-channel 64-word FIFO
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Functional Block Diagram
External Pins VCCP FLTP2 FLASH (288K Byte) Banks Sectors Memory Security Module (MSM) Address Data (16K Bytes) External Pins OSCIN ZPLL OSCOUT PLLDIS ADIN[11:0] MibADC 64-Word FIFO ADEVT ADREFHI ADREFLO VCCAD TMS470R1x Words Expansion Address/Data SCC1 VSSAD HET[0:8;18,30,22] CAN1TX CAN1RX CAN2TX CAN2RX SCI1CLK SCI1 SCI1TX SCI1RX SCI2CLK SCI2 SCI2TX SCI2RX HECC I2C3 I2C3SDA I2C3SCL I2C2SDA I2C2SCL I2C1SDA I2C1SCL Crystal
TRST TMS2 TEST PORRST CLKOUT Controller Channels Interrupt Expansion Module (IEM) TMS470R1x System Module with Enhanced Module(A) Breaker
SCC2
Digital Watchdog (DWD)
Analog Watchdog (AWD)
I2C2 C2SI SPI2 SPI1 GIO/EBM(A) I2C1
SPI2SIMO
SPI2SOMI
SPI1SIMO
SPI1SOMI
SPI2SCS
SPI1SCS
SPI2CLK
C2SILPN
SPI2ENA
SPI1ENA
SPI1CLK
C2SIRX
C2SITX
GIOA[1]/INT[1]/ECLK
GIOA[0]/INT[0]
GIOC[4:0]
GIOD[5:0]
GIOF[7:0]
enhanced module system module with extra bits disable ZPLL while STANDBY mode. GIOC[4:0], GIOD[5:0], GIOE[5:0], GIOF[7:0], GIOH[0], which muxed with EBM, available package. Table EBM-to-GIO mapping.
GIOH[5,0]/INT[13:8](A)
GIOA[7:2]/INT[7:2]
GIOE[7:0](A)
GIOG[7:0]
GIOB[0]
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT INTERNAL PULLUP/ PULLDOWN DESCRIPTION
HIGH-END TIMER (HET) HET[0] HET[1] HET[2] HET[3] HET[4] HET[5] HET[6] HET[7] HET[8] HET[18] HET[20] HET[22] CAN1SRX CAN1STX CAN2SRX CAN2STX C2SILPN C2SIRX C2SITX STANDARD CONTROLLER (SCC) tolerant 3.3-V tolerant 3.3-V 3.3-V tolerant 3.3-V GENERAL-PURPOSE (GIO) GIOA[0]/INT[0] GIOA[1]/INT[1]/ECLK GIOA[2]/INT[2] GIOA[3]/INT[3] GIOA[4]/INT[4] GIOA[5]/INT[5] GIOA[6]/INT[6] GIOA[7]/INT[7] GIOB[0]/DMAREQ[0] GIOC[0]/EBOE GIOC[1]/EBWR[0] GIOC[2]/EBWR[1] GIOC[3]/EBCS[5] GIOC[4]/EBCS[6] 3.3-V GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. Table tolerant General-purpose input/output pins. GIOA[7:0]/INT[7:0] interrupt-capable pins. GIOA[1]/INT[1]/ECLK multiplexed with external clock-out function external clock prescale (ECP) module. SCC1 receive SCC1 transmit SCC2 receive transmit C2SIb module loopback enable C2SIb module receive data input C2SIb module transmit data output 3.3-V Timer input capture output compare. HET[8:0,18,20,22] applicable pins programmed general-purpose input/output (GIO) pins. high-resolution pins. high-resolution (HR) SHARE feature allows even pins share next higher structures. This sharing independent whether available externally. available externally shared, then only used general-purpose I/O. more information SHARE, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
CLASS SERIAL INTERFACE (C2SIB)
power, ground, reference voltage, connect pins, except configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions (continued)
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT INTERNAL PULLUP/ PULLDOWN DESCRIPTION
GENERAL-PURPOSE (GIO) (CONTINUED) GIOD[0]/EBADDR[0] GIOD[1]/EBADDR[1] GIOD[2]/EBADDR[2] GIOD[3]/EBADDR[3] GIOD[4]/EBADDR[4] GIOD[5]/EBADDR[5] GIOE[0]/EBDATA[0] GIOE[1]/EBDATA[1] GIOE[2]/EBDATA[2] GIOE[3]/EBDATA[3] GIOE[4]/EBDATA[4] GIOE[5]/EBDATA[5] GIOE[6]/EBDATA[6] GIOE[7]/EBDATA[7] GIOF[0]/EBADDR[6]/ EBDATA[8] GIOF[1]/EBADDR[7]/ EBDATA[9] GIOF[2]/EBADDR[8]/ EBDATA[10] GIOF[3]/EBADDR[9]/ EBDATA[11] GIOF[4]/EBADDR[10]/ EBDATA[12] GIOF[5]/EBADDR[11]/ EBDATA[13] GIOF[6]/EBADDR[12]/ EBDATA[14] GIOF[7]/EBADDR[13]/ EBDATA[15] GIOG[0]/EBADDR[14] /EBADDR[6] GIOG[1]/EBADDR[15] /EBADDR[7] GIOG[2]/EBADDR[16] /EBADDR[8] GIOG[3]/EBADDR[17] /EBADDR[9] 3.3-V GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. Table
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions (continued)
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT INTERNAL PULLUP/ PULLDOWN DESCRIPTION
GENERAL-PURPOSE (GIO) (CONTINUED) GIOG[4]/EBADDR[18] /EBADDR[10] GIOG[5]/EBADDR[19] /EBADDR[11] GIOG[6]/EBADDR[20] /EBADDR[12] GIOG[7]/EBADDR[21] /EBADDR[13] GIOH[0]/EBADDR[22] /EBADDR[14]/INT[8] GIOH[1]/EBADDR[23] /EBADDR[15]/INT[9] GIOH[2]/EBADDR[24] /EBADDR[16]/INT[10] GIOH[3]/EBADDR[25] /EBADDR[17]/INT[11] GIOH[4]/EBADDR[26] /EBADDR[18]/INT[12] GIOH[5]/EBHOLD/ INT[13] 3.3-V MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) ADEVT ADIN[0] ADIN[1] ADIN[2] ADIN[3] ADIN[4] ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADREFHI ADREFLO VCCAD VSSAD 3.3-V 3.3-V MibADC module high-voltage reference input MibADC module low-voltage reference input MibADC analog supply voltage MibADC analog ground reference 3.3-V MibADC analog input pins 3.3-V MibADC event input. programmed pin. GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. Table GIOH[5:0]/INT[13:8] interrupt-capable pins.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions (continued)
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT INTERNAL PULLUP/ PULLDOWN DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI1) SPI1CLK SPI1ENA SPI1SCS SPI1SIMO SPI1SOMI tolerant SPI1 clock. SPI1CLK programmed pin. SPI1 chip enable. programmed pin. SPI1 slave chip select. programmed pin. SPI1 data stream. Slave in/master out. programmed pin. SPI1 data stream. Slave out/master programmed pin. SERIAL PERIPHERAL INTERFACE (SPI2) SPI2CLK SPI2ENA SPI2SCS SPI2SIMO SPI2SOMI INTER-INTEGRATED CIRCUIT (I2C) I2C1SDA I2C1SCL I2C2SDA I2C2SCL I2C3SDA I2C3SCL OSCIN OSCOUT 1.8-V tolerant I2C1 serial data I2C1 serial clock I2C2 serial data I2C2 serial clock I2C3 serial data I2C3 serial clock ZERO-PIN PHASE-LOCKED LOOP (ZPLL) Crystal connection external clock input External crystal connection Enable/disable ZPLL. ZPLL bypassed oscillator becomes system clock. bypass mode, recommends that this connected ground pulled down ground external resistor. SCI1 clock. SCI1CLK programmed pin. SCI1 data receive. SCI1RX programmed pin. SCI1 data transmit. SCI1TX programmed pin. SCI2 clock. SCI2CLK programmed pin. SCI2 data receive. SCI2RX programmed pin. SCI2 data transmit. SCI2TX programmed pin. tolerant SPI2 clock. programmed pin. SPI2 chip enable. programmed pin. SPI2 slave chip select. programmed pin. SPI2 data stream. Slave in/master out. programmed pin. SPI2 data stream. Slave out/master programmed pin.
PLLDIS
3.3-V
SERIAL COMMUNICATIONS INTERFACE (SCI1) SCI1CLK SCI1RX SCI1TX 3.3-V tolerant 3.3-V
SERIAL COMMUNICATIONS INTERFACE (SCI2) SCI2CLK SCI2RX SCI2TX 3.3-V tolerant 3.3-V
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions (continued)
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT INTERNAL PULLUP/ PULLDOWN DESCRIPTION
SYSTEM MODULE (SYS) CLKOUT PORRST 3.3-V 3.3-V Bidirectional pin. CLKOUT programmed output SYSCLK, ICLK, MCLK. Input master chip power-up reset. External monitor circuitry must assert power-on reset. Bidirectional reset. internal circuitry assert reset, external system reset assert device reset. this pin, output buffer implemented open drain (drives only). ensure external reset arbitrarily generated, recommends that external pullup resistor connected this pin. Analog watchdog reset. provides system reset written time system, providing external network circuit connected. user using AWD, recommends that this connected ground pulled down ground external resistor. more details external network circuit, TMS470R1x System Module Reference Guide (literature number SPNU189). Test clock. controls test hardware (JTAG). Test data inputs serial data test instruction register, test data register, programmable test address (JTAG). Test data out. outputs serial data from test instruction register, test data register, identification register, programmable test address (JTAG). Test enable. Reserved internal only. recommends that this connected ground pulled down ground external resistor. Serial input controlling state test access port (TAP) controller (JTAG). Serial input controlling second TAP. recommends that this connected VCCIO pulled VCCIO external resistor. Test hardware reset TAP1 TAP2. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic. recommends that this pulled down ground external resistor.
3.3-V
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
3.3-V
TEST/DEBUG (T/D)
TEST
3.3-V
TMS2
TRST
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table Terminal Functions (continued)
TERMINAL NAME INPUT VOLTAGE OUTPUT CURRENT FLASH FLTP2 VCCP VCCIO VSSIO SUPPLY VOLTAGE DIGITAL (3.3 SUPPLY GROUND CORE SUPPLY GROUND DIGITAL Digital supply ground reference Core supply ground reference 3.3-V Digital supply voltage 1.8-V Core logic supply voltage 3.3-V SUPPLY VOLTAGE CORE (1.8 Flash test proper operation, this must connected connect (NC)]. Flash external pump voltage (3.3 INTERNAL PULLUP/ PULLDOWN DESCRIPTION
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
TMS470R1A288 DEVICE-SPECIFIC INFORMATION
Memory
Memory Bytes) 0xFFFF_FFFF System Module Control Registers (512K Bytes) Peripheral Control Registers (512K Bytes) 0xFFF0_0000 0xFFEF_FFFF 0xFFE8_C000 0xFFE8_BFFF 0xFFE8_8000 0xFFE8_7FFF 0xFFE8_4021 0xFFE8_4020 0xFFE8_4000 Reserved Flash Control Registers Reserved Control Registers SYSTEM with PSA, CIM, RTI, DEC, DMA, MMC, Reserved Reserved Reserved SPI1 Reserved SCI2 SCI1 Reserved MibADC Reserved HECC HECC SCC2 SCC1 Reserved SCC2 Reserved SCC1 Reserved I2C3 I2C2 I2C1 Reserved SPI2 Reserved S2SIb Reserved 0xFFFF_FFFF 0xFFFF_FD00 0xFFFF_FC00 0xFFFF_F700 0xFFF8_0000 0xFFF7_FC00 0xFFF7_F800 0xFFF7_F500 0xFFF7_F400 0xFFF7_F000 0xFFF7_EF00 0xFFF7_ED00 0xFFF7_EC00 0xFFF7_E200 0xFFF7_E000 0xFFF7_DE00 0xFFF7_DC00 0xFFF7_DA00 0xFFF7_D900 0xFFF7_D800 0xFFF7_D400 0xFFF7_C800 0xFFF0_0000
0xFFF8_0000 0xFFF7_FFFF
Reserved MByte) 0xFFE0_0000
0x7FFF_FFFF
(61K Bytes)
Program Data Area
FLASH (288K Bytes) Banks Sectors
Bytes) Reserved Reserved Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x0000_0023 0x0000_0020 0x0000_001C 0x0000_0018 0x0000_0014 0x0000_0010 0x0000_000C 0x0000_0008 0x0000_0004 0x0000_0000
0x0000_0024 0x0000_0023 Exception, Interrupt, Reset Vectors 0x0000_0000
Memory addresses configurable system (SYS) module within range 0x0000_0000 0xFFE0_0000. registers part memory map.
Figure TMS470R1A288 Memory
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Memory Selects Memory selects allow user address memory arrays (i.e., flash, RAM, RAM) user-defined addresses. Each memory select (low high) memory base address registers (MFBAHRx MFBALRx) that, together, define array's starting (base) address, block size, protection. base address each memory select configurable memory address boundary that multiple decoded block size. more information control configure these memory select registers, structure memory sections TMS470R1x System Module Reference Guide (literature number SPNU189). memory selection assignments memory selected, Table Table TMS470R1A288 Memory Selection Assignment
MEMORY SELECT (fine) (fine) (fine) (fine) (fine) (coarse) MEMORY SELECTED (ALL INTERNAL) FLASH/ROM FLASH/ROM CS[5]/GIOC[3] MEMORY SIZE 288K (x8) (x16) (x8) (x16) MEMORY BASE ADDRESS REGISTER MFBAHR0 MFBALR0 MFBAHR1 MFBALR1 MFBAHR2 MFBALR2 MFBAHR3 MFBALR3 MFBAHR4 MFBALR4 MCBAHR2 MCBALR2 SMCR1 SMCR5 STATIC REGISTER
(coarse)
CS[6]/GIOC[4]
MCBAHR3 MCBALR3
SMCR6
refers size memory 8-bits; refers size memory 16-bits. starting addresses both memory-select signals cannot offset from each other multiple user-defined block size memory-base address register.
Memory Security Module A288 device also includes memory security module (MSM) provide additional security flexibility memory contents' protection. password unlocking located four words just before flash protection keys (see Flash Protection Keys section below). JTAG Security Module (JSM) A288 device includes JTAG security module provide maximum security memory contents. visible unlock code chosen sector first bank user-programmable memory. A288, visible unlock code sector. A288 device contains 16K-bytes internal static configurable module addressed within range 0x0000_0000 0xFFE0_0000. This A288 implemented 16K-byte array selected memory-select signals.
NOTE:
This A288 configuration imposes additional constraint memory RAM; starting addresses both memory selects cannot offset from each other multiples size physical (i.e., A288 device). A288 addressed through memory selects protected memory protection unit (MPU) portion module, allowing user finer blocks memory protection than allowed memory selects. ideal protecting operating system while allowing access current task. more detailed information portion module memory protection, memory section TMS470R1x System Module Reference Guide (literature number SPNU189).
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Flash flash memory nonvolatile electrically erasable programmable memory implemented with 32-bit-wide data interface. flash external state machine programming erase functions. Flash Read Flash Program Erase sections below.
Flash Protection Keys
A288 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/compaction operations from occurring until after four protection keys have been matched loading correct user keys into FMPKEY control register. protection keys A288 located last words first sector. more detailed information flash protection keys FMPKEY control register, "Optional Quadruple Protection Keys" "Programming Protection Keys" portions TMS470R1x Flash Reference Guide (literature number SPNU213).
Flash Read
A288 flash memory configurable module addressed within range 0x0000_0000 0xFFE0_0000. flash addressed through memory selects
NOTE:
flash external pump voltage (VCCP) required operations (program, erase, read).
Flash Pipeline Mode
When pipeline mode, flash operates with system clock frequency MHz. normal mode, flash operates with system clock frequency MHz. Flash pipeline mode capable accessing 64-bit words provides 32-bit pipelined words CPU. Also, pipeline mode flash read with wait states when memory addresses contiguous (after initial 2-wait-state reads).
NOTE:
After system reset, pipeline mode disabled (FMREGOPT[0] other words, A288 device powers comes reset non-pipeline mode. Furthermore, setting flash configuration mode (GBLCTRL[4]) will override pipeline mode.
Flash Program Erase
A288 device flash contains 32K-byte memory array bank) 256K-byte bank, total 288K-bytes flash, consists eight sectors. These eight sectors sized follows:
SECTOR SEGMENT Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes ADDRESS 0x0000_0000 0x0000_0000 0x0000_2000 0x0000_4000 0x0000_6000 0x0004_0000 0x0005_0000 0x0006_0000 0x0007_0000 HIGH ADDRESS 0x0000_07FF 0x0000_1FFF 0x0000_3FFF 0x0000_5FFF 0x0000_7FFF 0x0004_FFFF 0x0005_FFFF 0x0006_FFFF 0x0007_FFFF BANK1 (256K Bytes) BANK0 (32K Bytes) MEMORY ARRAYS BANKS)
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
minimum size erase operation sector. maximum size program operation 16-bit word.
NOTE:
flash external pump voltage (VCCP) required operations (program, erase, read). Execution occur from bank while programming/erasing sectors another bank. However, execution occur from sector within bank that being programmed erased. more detailed information flash program erase operations, TMS470R1x Flash Reference Guide (literature number SPNU213). A288 device contains RAM. 64-instruction capability. configurable module addressed within range 0x0000_0000 0xFFE0_0000. addressed through memory select Share A288 peripheral contains XOR-share feature. This feature allows adjacent high-resolution channels XORed together, making possible output smaller pulses than standard HET. more detailed information XOR-share feature, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). Peripheral Selects Base Addresses A288 device uses peripheral selects decode base addresses peripherals. These peripheral selects fixed transparent user because they part decoding scheme used module. Control registers peripherals, module, flash begin base addresses shown Table Table A288 Peripherals, System Module, Flash Base Addresses
CONNECTING MODULE SYSTEM RESERVED RESERVED RESERVED RESERVED BUFFER RESERVED RESERVED ADDRESS RANGE BASE ADDRESS 0xFFFF_FFD0 0xFFFF_FF70 0xFFFF_FF60 0xFFFF_FF40 0xFFFF_FF20 0xFFFF_FF00 0xFFFF_FE80 0xFFFF_FE00 0xFFFF_FD80 0xFFFF_FD00 0xFFFF_FC00 0xFFFF_FB00 0xFFFF_FA00 0xFFFF_F800 0xFFFF_F700 0xFFF8_0000 0xFFF7_FD00 0xFFF7_FC00 ENDING ADDRESS FFFF_FFFF 0xFFFF_FFCB FFFF_FF6F 0xFFFF_FF5F 0xFFFF_FF3F 0xFFFF_FF1F 0xFFFF_FEFF 0xFFFF_FE7F 0xFFFF_FDFF 0xFFFF_FD7F 0xFFFF_FCFF 0xFFFF_FBFF 0xFFFF_FAFF 0xFFFF_F9FF 0xFFFF_F7FF 0xFFFF_F6FF 0xFFF7_FFFF 0xFFF7_FCFF PERIPHERAL SELECTS PS[0]
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Table A288 Peripherals, System Module, Flash Base Addresses (continued)
CONNECTING MODULE RESERVED SPI1 RESERVED SCI2 SCI1 RESERVED MibADC RESERVED HECC RESERVED HECC RESERVED RESERVED SCC2 RESERVED SCC1 RESERVED SCC2 RESERVED SCC1 RESERVED I2C3 I2C2 I2C1 RESERVED SPI2 RESERVED RESERVED C2SIb RESERVED RESERVED Flash Control Registers RESERVED Control Registers RESERVED ADDRESS RANGE BASE ADDRESS 0xFFF7_F900 0xFFF7_F800 0xFFF7_F600 0XFFF7_F500 0xFFF7_F400 0xFFF7_F100 0xFFF7_F000 0xFFF7_EF00 0xFFF7_EE00 0xFFF7_ED00 0xFFF7_EC00 0xFFF7_EA00 0xFFF7_E800 0xFFF7_E600 0xFFF7_E400 0xFFF7_E300 0xFFF7_E200 0xFFF7_E100 0xFFF7_E000 0xFFF7_DF00 0xFFF7_DE00 0xFFF7_DD00 0xFFF7_DC00 0xFFF7_DB00 0xFFF7_DA00 0xFFF7_D900 0xFFF7_D800 0xFFF7_D500 0xFFF7_D400 0xFFF7_CC00 0xFFF7_C900 0xFFF7_C800 0xFFF7_C000 0xFFF0_0000 0xFFE8_8000 0xFFF8_4024 0xFFE8_4000 0xFFF8_0000 ENDING ADDRESS 0xFFF7_FBFF 0xFFF7_F8FF 0xFFF7_F7FF 0XFFF7_F5FF 0xFFF7_F4FF 0xFFF7_F3FF 0xFFF7_F0FF 0xFFF7_EFFF 0xFFF7_EEFF 0xFFF7_EDFF 0xFFF7_ECFF 0xFFF7_EBFF 0xFFF7_E9FF 0xFFF7_E7FF 0xFFF7_E5FF 0xFFF7_E3FF 0xFFF7_E2FF 0xFFF7_E1FF 0xFFF7_E0FF 0xFFF7_DFFF 0xFFF7_DEFF 0xFFF7_DDFF 0xFFF7_DCFF 0xFFF7_DBFF 0xFFF7_DAFF 0xFFF7_D9FF 0xFFF7_D8FF 0xFFF7_D7FF 0xFFF7_D4FF 0xFFF7_D3FF 0xFFF7_CBFF 0xFFF7_C8FF 0xFFF7_C7FF 0xFFF7_BFFF 0xFFE8_BFFF 0xFFF8_7FFF 0xFFE8_4023 0xFFF8_3FFF PS[10] PS[11] PS[12] PS[13] PS[14] PS[15] PS[9] PS[8] PS[7] PS[5] PS[6] PS[4] PS[3] PS[2] PERIPHERAL SELECTS PS[1]
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Direct-Memory Access (DMA) direct-memory access (DMA) controller transfers data from specified location A288 memory (except restricted memory locations such system control registers area). manages channels, supports data transfer both on-chip off-chip memories peripherals. controller connected both peripheral buses, enabling these data transfers occur parallel with activity thus maximizing overall system performance. Although controller possible configurations A288 device, controller configuration control packets channels. A288 request hardwired configuration, Table Table Request Lines Connections
MODULES SPI1 SPI1 MibADC/I2C1 MibADC/SCI1 MibADC/SCI1 I2C1 SPI2 SPI2 I2C2/C2SIb I2C2/C2SIb I2C3 I2C3 Reserved SCI2 SCI2 SCI2 end-receive SCI2 end-transmit SCI2DMA0 SCI2DMA1 SPI1 end-receive SPI1 end-transmit EV/I2C1 read G1/SCI1 end-receive G2/SCI1 end-transmit I2C1 write SPI2 end-receive SPI2 end-transmit I2C2 read end-receive/C2SIb end-receive I2C3 read I2C3 write REQUEST INTERRUPT SOURCES Expansion request EBDMAREQ0 SPI1DMA0 SPI1DMA1 MibADCDMA0/I2C1DMA0 MibADCDMA1/SCI1DMA0 MibADCDMA2/SCI1DMA1 I2C1DMA1 SPI2DMA0 SPI2DMA1 I2C2DMA0/C2SIDMA0 I2C3DMA0 I2C3DMA1 CHANNEL DMAREQ[0] DMAREQ[1] DMAREQ[2] DMAREQ[3] DMAREQ[4] DMAREQ[5] DMAREQ[6] DMAREQ[7] DMAREQ[8] DMAREQ[9] DMAREQ[10] DMAREQ[11] DMAREQ[12] DMAREQ[13] DMAREQ[14] DMAREQ[15]
I2C2 write end-transmit/C2SIb end-transmit I2C2DMA1/C2SIDMA1
channels with more than assigned request source, only sources listed request generator given application. device software control ensure that there conflicts between requesting modules.
Each channel control packets attached allowing continuously load generate periodic interrupts that data read CPU. control packets allow interrupt enable, channels determine priority level interrupt. transfers occur modes: Non-request mode (used when transferring from memory memory) Request mode (used when transferring from memory peripheral) more detailed functional information controller, TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194). Interrupt Priority (IEM CIM) Interrupt requests originating from A288 peripheral modules (i.e., SPI1 SPI2; SCI1 SCI2; RTI; etc.) assigned channels within 48-channel interrupt expansion module (IEM) where, programmable register mapping, these channels then mapped 32-channel central interrupt manager (CIM) portion module. Programming multiple interrupt sources same channel effectively shares channel between sources. request channels maskable that individual channels selectively disabled. interrupt requests programmed either type: Fast interrupt request (FIQ) Normal interrupt request (IRQ)
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
prioritizes interrupts. precedences request channels decrease with ascending channel order [highest] [lowest] priority). IEM-to-CIM default mapping, channel priorities, their associated modules, Table Table Interrupt Priority (IEM CIM)
MODULES SPI1 SPI2 Reserved I2C1 SCI1/SCI2 SCI1 C2SIb I2C2 SCC2 SCC1 Reserved MibADC SCI2 I2C3 SCI1 System Reserved SCC2 SCC1 SCI2 MibADC MibADC Reserved Reserved HECC HECC Reserved HECC interrupt HECC interrupt interrupt SCC2 interrupt SCC1 interrupt SCI2 transmit interrupt MibADC Group conversion Interrupt interrupt MibADC Group conversion MibADC event conversion SCI2 receive interrupt interrupt I2C3 interrupt SCI1 transmit interrupt interrupt (SSI) interrupt I2C1 interrupt SCI1 SCI2 error interrupt SCI1 receive interrupt C2SIb interrupt I2C2 interrupt SCC2 interrupt SCC1 interrupt INTERRUPT SOURCES SPI1 end-transfer/overrun COMP2 interrupt COMP1 interrupt interrupt SPI2 end-transfer/overrun interrupt DEFAULT INTERRUPT LEVEL/CHANNEL CHANNEL 32-37 40-47
more detailed functional information IEM, TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). more detailed functional information CIM, TMS470R1x System Module Reference Guide (literature number SPNU189).
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Expansion Module (EBM) expansion module (EBM) standalone module used bond both general-purpose input/output pins expansion interface pins. module supports 16-bit expansion memory interface mappings, well mapping following expansion signals: 27-bit address (EBADDR[26:0]) 19-bit address (EBADDR[18:0]) 16-bit data (EBDATA[7:0]or EBDATA[15:0]) write strobes (EBWR[1:0]) memory chip selects (EBCS[6:5]) output enable (EBOE) external hold signal interfacing slow memories (EBHOLD) Table shows multiplexing signals with expansion interface signals. mapping these pins varies depending memory mode. Table Expansion Mapping
GIOB[0] GIOC[0] GIOC[2:1] GIOC[4:3] GIOD[5:0] GIOE[7:0] GIOF[7:0] GIOG[7:0] GIOH[4:0] GIOH[5] EXPANSION MODULE PINS EBDMAREQ[0] EBOE EBWR[1:0] EBCS[6:5] EBADDR[5:0] EBDATA[7:0] EBADDR[13:6] EBADDR[21:14] EBADDR[26:22] EBHOLD EBDMAREQ[0] EBOE EBWR[1:0] EBCS[6:5] EBADDR[5:0] EBDATA[7:0] EBDATA[15:8] EBADDR[13:6] EBADDR[18:14] EBHOLD
These mappings controlled control registers (EBMXCRB EBMXCRH) control register (EBMCR1). GPIO functions, GIODIRx, GIODINx, GIODOUTx, GIODSETx, GIODCLRx. more detailed information, TMS470R1x General-Purpose Input/Output (GIO) Reference Guide (literature number SPNU192) TMS470R1x Expansion Module (EBM) Reference Guide (literature number SPNU222). refers size memory 8-bits; refers size memory 16-bits.
Table lists names expansion interface signals their functions. Table Expansion Pins
EBDMAREQ EBOE EBWR EBCS EBADDR EBDATA EBHOLD DESCRIPTION Expansion request Expansion output enable Expansion write strobe. EBWR[1] controls EBDATA[15:8] EBWR[0] controls EBDATA[7:0]. Expansion chip select Expansion address Expansion data Expansion hold: external device connected expansion assert this signal wait states expansion transaction.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
MibADC multi-buffered analog-to-digital converter (MibADC) accepts analog signal converts signal 10-bit digital value. A288 MibADC module function modes: compatibility mode, where programmer's model compatible with TMS470R1x module digital results stored digital result registers; buffered mode, where digital result registers replaced with three FIFO buffers, each conversion group [event, group1 (G1), group2 (G2)]. buffered mode, MibADC buffers serviced interrupts DMA. MibADC Event Trigger Enhancements MibADC includes major enhancements over event-triggering capability TMS470R1x ADC. Both group event group configured event-triggered operation, providing event-triggered groups. trigger source polarity selected individually both group event group from options identified Table Table MibADC Event Hookup Configuration
EVENT EVENT1 EVENT2 EVENT3 EVENT4 SOURCE SELECT BITS EVENT (G1SRC[1:0] EVSRC[1:0]) SIGNAL NAME ADEVT HET18 Reserved Reserved
group these event-triggered selections configured group source select bits (G1SRC[1:0]) event source register (ADEVTSRC[5:4]). event group, these event-triggered selections configured event group source select bits (EVSRC[1:0]) event source register (ADEVTSRC[1:0]). more detailed functional information MibADC, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). JTAG Interface There main test access ports (TAPs) A288 device: TMS470R1x Device factory test Some JTAG pins shared among these TAPs. hookup illustrated Figure
TMS470R1x TRST TRST
Factory Test TRST TMS2
Figure JTAG Interface
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Documentation Support Extensive documentation supports TMS470 microcontroller family generation devices. types documentation available include: data sheets with design specifications; complete user's guides devices development support tools; hardware software applications. Useful reference documentation includes: Bulletin TMS470 Microcontroller Family Product Bulletin (literature number SPNB086) User's Guides TMS470R1x System Module Reference Guide (literature number SPNU189) TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192) TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194) TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195) TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196) TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197) TMS470R1x High Timer (HET) Reference Guide (literature number SPNU199) TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202) TMS470R1x MultiBuffered Analog Digital (MibADC) Reference Guide (literature number SPNU206) TMS470R1x ZeroPin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212) TMS470R1x Flash Reference Guide (literature number SPNU213) TMS470R1x Class Serial Interface (C2SIb) Reference Guide (literature number SPNU214) TMS470R1x Class Serial Interface (C2SIa) Reference Guide (literature number SPNU218) TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245) TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246) TMS470 Peripherals Overview Reference Guide (literature number SPNU248) Errata Sheet TMS470R1A288 TMS470 Microcontrollers Silicon Errata (literature number SPNZ142)
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Device Development-Support Tool Nomenclature designate stages product development cycle, assigns prefixes part numbers devices support tools. Each commercial family member three prefixes: TMX, TMP, (e.g., TMS470R1A288). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMDX TMDS Experimental device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product
Support tool development evolutionary flow:
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. Figure illustrates numbering symbol nomenclature TMS470R1x family.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
PREFIX Fully Qualified Device FAMILY TMS470 RISC Embedded Microcontroller Family ARCHITECTURE ARM7TDM1 DEVICE TYPE With 288K-Bytes Flash Memory: 48-MHz Frequency 1.8-V Core, 3.3-V Flash Program Memory ZPLL Clock 1K-Byte Static 1K-Byte Instructions) 10-Bit, 12-Input MibADC Modules Modules C2SIb [SCC] HET, Channels Three Modules
OPTIONS
TEMPERATURE RANGE -40°C 85°C PACKAGE TYPE 100-pin Low-Profile Quad Flatpack (LQFP) 144-pin Low-Profile Quad Flatpack (LQFP) REVISION CHANGE Blank Original FLASH MEMORY 288K-Bytes Flash Memory
Figure TMS470R1x Family Nomenclature
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Device Identification Code Register device identification code register identifies silicon version, technology family (TF), flash device, assigned device-specific part number (see Figure A288 device identification code register value 0xn95F. Figure TMS470 Device Allocation Register [offset FFFF_FFF0h]
Reserved
VERSION
PART NUMBER
LEGEND: Read only, Value constant after RESET; Value after RESET
Table TMS470 Device Allocation Register Field Descriptions
31-16 15-12 Field Reserved VERSION PART NUMBER Value Description Reads undefined writes have effect. Silicon version (revision) bits These bits identify silicon version device. Initial device version numbers start 0000. Technology family This distinguishes technology family core power supply: F10/C10 devices F05/C05 devices ROM/flash This distinguishes between flash devices: Flash device device Device-specific part number bits These bits identify assigned device-specific part number. assigned device-specific part number A288 device 0101011. Mandatory High Bits tied high default.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Device Electrical Specifications Timing Parameters Absolute Maximum Ratings
over operating free-air temperature range, version unless otherwise noted
Supply voltage range: Supply voltage range: Input voltage range: Input clamp current:
VCCIO VCCAD VCCP (flash pump) tolerant input pins other input pins tolerant pins, PORRST, TRST, TEST, ADIN[0:11] VCCAD) other pins VCCAD)
-0.3 -0.3 4.1V -0.3 6.0V -0.3 4.1V -40°C 85°C -40°C 150°C -40°C 150°C
Operating free-air temperature ranges, Operating junction temperature range,
version
Storage temperature range, Tstg
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "Recommended Operating Conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect their associated grounds. These pins have internal clamp diode positive supply voltage.
Device Recommended Operating Conditions
VCCIO VCCAD VCCP VSSAD Digital logic supply voltage (Core) Digital logic supply voltage (I/O) MibADC supply voltage Flash pump supply voltage Digital logic supply ground MibADC supply ground Operating free-air temperature Operating junction temperature voltages with respect VSS, except VCCAD, which with respect VSSAD. version -0.1 1.71 2.05 UNIT
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range
PARAMETER Vhys Input hysteresis Low-level input voltage High-level input voltage Input threshold voltage Low-level output voltage High-level output voltage Input clamp current (I/O pins) Pulldown Input current (3.3 input pins) Pulldown Pullup Pullup other pins inputs inputs only VSSIO VCCIO VCCIO VCCIO pullup pulldown Input current tolerant input pins) VCCIO CLKOUT, AWD, TDI, TDO, TMS, TMS2 Low-level output current other tolerant CLKOUT, TDI, TDO, TMS, TMS2 High-level output current other tolerant SYSCLK MHz, ICLK MHz, 2.05 SYSCLK MHz, ICLK MHz, 2.05 30°C version, load, VCCIO 2.05 2.05 VCCIO VCCIO TEST CONDITIONS 0.15 -0.3 1.35 VCCIO VCCIO UNIT
Digital supply current (operating mode)
Digital supply current (standby mode) OSCIN 4MHz, 2.05 Digital supply current (halt mode)
Source currents (out device) negative while sink currents (into device) positive. This does apply PORRST pin. PORRST exceptions, PORRST timings section. These values help determine external network circuit. more details, TMS470R1x System Module Reference Guide (literature number SPNU189). linear with respect amount load current (IOL/IOH) applied. Parameter does apply input-only output-only pins. buffers this device called zero-dominant buffers. these buffers shorted together outputting level other outputting high level, resulting value will always low. flash banks/pumps sleep mode. reduced power consumption power mode, CANSRX CANSTX should driven output LOW.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Electrical Characteristics (continued)
over recommended operating free-air temperature range
PARAMETER VCCIO Digital supply current (operating mode) VCCIO Digital supply current (standby mode) ICCIO VCCIO Digital supply current (halt mode) TEST CONDITIONS load, VCCIO load, VCCIO 30°C version, load, VCCIO load, VCCIO VCCAD supply current (operating mode) VCCAD supply current (standby mode) ICCAD VCCAD supply current (halt mode) frequencies, VCCAD load, VCCAD 30°C version, load, VCCAD VCCAD ICCP VCCP read operation VCCP program erase VCCP standby mode operation VCCP pump supply current 30°C version, load, VCCP halt mode operation VCCP halt mode operation Input capacitance Output capacitance UNIT
pins configured inputs outputs with load. pulldown inputs pullup inputs VCCIO
Parameter Measurement Information
Tester Electronics LOAD Output Under Test
respective respective pin(A) 150-pF typical load-circuit capacitance(B)
Where:
VLOAD
these values, "Electrical Characteristics over Recommended Operating Free-Air Temperature Range" table. timing parameters measured using external load capacitance unless otherwise noted.
Figure Test Load Circuit
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Timing Parameter Symbology
Timing parameter symbols have been created accordance with JEDEC Standard 100. shorten symbols, some names other related terminology have been abbreviated follows: ICLK OSC, OSCI OSCO Compaction, CMPCT CLKOUT Erase Interface clock Master mode OSCIN OSCOUT Program, PROG Ready Read margin RDMRGN0 Read margin RDMRGN1 SIMO SOMI Read Reset, SCInRX Slave mode SCInCLK SPInSIMO SPInSOMI SPInCLK System clock SCInTX
Lowercase subscripts their meanings are: access time cycle time (period) delay time fall time hold time rise time setup time transition time valid time pulse duration (width)
following additional letters used with these meanings: High Valid Unknown, changing, don't care level High impedance
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
External Reference Resonator/Crystal Oscillator Clock Option
oscillator enabled connecting appropriate fundamental 4-10 resonator/crystal load capacitors across external OSCIN OSCOUT pins shown Figure oscillator single-stage inverter held bias integrated bias resistor. This resistor disabled during leakage test measurement HALT mode. strongly encourages each customer submit samples device resonator/crystal vendors validation. vendors equipped determine what load capacitors will best tune their resonator/crystal microcontroller device optimum start-up operation over temperature/voltage extremes. external oscillator source used connecting 1.8-V clock signal OSCIN leaving OSCOUT unconnected (open) shown Figure
OSCIN OSCOUT OSCIN OSCOUT
C1(A)
Crystal
C2(A)
External Clock Signal (toggling 0-1.8
values should provided resonator/crystal vendor.
Figure Crystal/Clock Connection
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
ZPLL CLOCK SPECIFICATIONS Timing Requirements ZPLL Circuits Enabled Disabled
f(OSC) tc(OSC) tw(OSCIL) tw(OSCIH) f(OSCRST) Input clock frequency Cycle time, OSCIN Pulse duration, OSCIN Pulse duration, OSCIN high FAIL frequency UNIT
Causes device reset (specifically clock reset) setting FAIL (GLBCTRL[15]) FAIL flag (GLBSTAT[1]) bits equal more detailed information these bits device resets, TMS470R1x System Module Reference Guide (literature number SPNU189).
Switching Characteristics Over Recommended Operating Conditions Clocks
PARAMETER f(SYS) f(CONFIG) f(ICLK) f(ECLK) tc(SYS) tc(CONFIG) tc(ICLK) tc(ECLK) System clock frequency System clock frequency flash config mode Interface clock frequency External clock output frequency module Cycle time, system clock Cycle time, system clock flash config mode Cycle time, interface clock Cycle time, module external clock output Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled 20.8 41.6 41.6 41.6 41.6 TEST CONDITIONS Pipeline mode enabled Pipeline mode disabled UNIT
f(SYS) f(OSC) where {8}, {1,2,3,4,5,6,7,8} when PLLDIS system-clock divider determined CLKDIVPRE [2:0] bits global control register (GLBCTRL[2:0]) multiplier determined MULT4 also GLBCTRL register (GLBCTRL.3). f(SYS) f(OSC) where {1,2,3,4,5,6,7,8} when PLLDIS f(ICLK) f(SYS) where interface clock divider ratio determined PCR0[4:1] bits module. f(ECLK) f(ICLK) where 256}. prescale value defined ECPCTRL[7:0] register bits module. Pipeline mode enabled disabled determined ENPIPE (FMREGOPT[0]). Flash Vread must achieve maximum system clock frequency.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Switching Characteristics Over Recommended Operating Conditions External Clocks
(see Figure Figure
PARAMETER tw(COL) Pulse duration, CLKOUT TEST CONDITIONS SYSCLK MCLK ICLK: even ICLK: SYSCLK MCLK tw(COH) Pulse duration, CLKOUT high ICLK: even ICLK: even even tw(EOL) Pulse duration, ECLK even even even tw(EOH) Pulse duration, ECLK high even 0.5tc(SYS) 0.5tc(ICLK) 0.5tc(ICLK) 0.5tc(SYS) 0.5tc(SYS) 0.5tc(ICLK) 0.5tc(ICLK) 0.5tc(SYS) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(SYS) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(SYS) UNIT
interface clock divider ratio determined PCR0[4:1] bits module. 256}. prescale value defined ECPCTRL[7:0] register bits module. CLKOUT/ECLK pulse durations (low/high) function OSCIN pulse durations when PLLDIS active. Clock source bits selected either SYSCLK (CLKCNTL[6:5] binary) MCLK (CLKCNTL[6:5] binary). Clock source bits selected ICLK (CLKCNTL[6:5] binary).
tw(COH) CLKOUT tw(COL)
Figure CLKOUT Timing Diagram
tw(EOH) ECLK tw(EOL)
Figure ECLK Timing Diagram
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
PORRST TIMINGS Timing Requirements PORRST
(see Figure
VCCPORL VCCPORH VCCIOPORL VCCIOPORH VIL(PORRST) tsu(PORRST)r tsu(VCCIO)r th(PORRST)r tsu(PORRST)f th(PORRST)rio th(PORRST)d tsu(PORRST)fio tsu(VCCIO)f supply level when PORRST must active during power high supply level when PORRST must remain active during power become active during power down VCCIO supply level when PORRST must active during power VCCIO high supply level when PORRST must remain active during power become active during power down Low-level input voltage after VCCIO VCCIOPORH Low-level input voltage PORRST before CCIO VCCIOPORL Setup time, PORRST active before VCCIO VCCIOPORL during power Setup time, VCCIO VCCIOPORL before VCCPORL Hold time, PORRST active after VCCPORH Setup time, PORRST active before VCCPORH during power down Hold time, PORRST active after VCCIOPORH Hold time, PORRST active after VCCPORL Setup time, PORRST active before VCCIOPORH during power down Setup time, VCCPORL before VCCIO VCCIOPORL
CCIOPORH CCIO
UNIT VCCIO
2.75
CCIOPORH tsu(VCCIO)f
/VCCIO
th(PORRST)rio
CCPORH
tsu(PORRST)f th(PORRST)r
tsu(PORRST)fio tsu(PORRST)f th(PORRST)r CCPORL th(PORRST)d IL(PORRST)
CCPORH
CCIOPORL VCCP/VCCIO PORRST
CCPORL tsu(VCCIO)r tsu(PORRST)r IL(PORRST)
CCIOPORL
Figure PORRST Timing Diagram
Switching Characteristics Over Recommended Operating Conditions
PARAMETER tv(RST) tfsu Valid time, active after PORRST inactive Valid time, active (all others) Flash start-up time, from inactive fetch first instruction from flash (flash pump stabilization time) 4112tc(OSC) 8tc(SYS) 670tc(OSC) UNIT
Specified values include rise/fall times. rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
JTAG SCAN INTERFACE TIMING
(JTAG Clock Specification 10-MHz 50-pF Load Output)
tc(JTAG) tsu(TDI/TMS TCKr) th(TCKr
-TDI/TMS)
UNIT
Cycle time, JTAG high period Setup time, TDI, before rise (TCKr) Hold time, TDI, after TCKr Hold time, after TCKf Delay time, valid after fall (TCKf)
th(TCKf -TDO) td(TCKf -TDO)
tc(JTAG) tsu(TDI/TMS TCKr) th(TCKr TDI/TMS) th(TCKf TDO) td(TCKf TDO) tc(JTAG)
Figure JTAG Scan Timings
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
OUTPUT TIMINGS Switching Characteristics Output Timings versus Load Capacitance (CL)
(see Figure
PARAMETER Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 Rise time, Fall time, Rise time, tolerant pins Fall time, tolerant pins Rise time, other output pins Fall time, other output pins
Output
12.5 12.5
UNIT
Figure CMOS-Level Outputs
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
INPUT TIMINGS Timing Requirements Input Timings
(see Figure
Input minimum pulse width tc(ICLK) interface clock cycle time f(ICLK)
Input
UNIT
tc(ICLK)
Figure CMOS-Level Inputs
FLASH TIMINGS Timing Requirements Program Flash
tprog(16-bit) tprog(Total) terase(sector) twec tfp(RST) tfp(SLEEP) tfp(STANDBY) Half word (16-bit) programming time 288K-byte programming time Sector erase time Write/erase cycles 105°C Flash pump settling time from SLEEP Initial flash pump settling time from SLEEP STANDBY Initial flash pump settling time from STANDBY ACTIVE 1000 10000 134tc(SYS) 134tc(SYS) 67tc(SYS) UNIT cycles
more detailed information flash core sectors, flash program erase section this data sheet. 288K-byte programming time includes overhead state machine.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SPIn MASTER MODE TIMING PARAMETERS SPIn Master Mode External Timing Parameters
(CLOCK PHASE SPInCLK output, SPInSIMO output, SPInSOMI input) (see Figure
tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M td(SPCH-SIMO)M td(SPCL-SIMO)M tv(SPCL-SIMO)M tv(SPCH-SIMO)M tsu(SOMI-SPCL)M tsu(SOMI-SPCH)M tv(SPCL-SOMI)M tv(SPCH-SOMI)M Cycle time, SPInCLK Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Delay time, SPInCLK high SPInSIMO valid (clock polarity Delay time, SPInCLK SPInSIMO valid (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Setup time, SPInSOMI before SPInCLK (clock polarity Setup time, SPInSOMI before SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity tc(SPC)M tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 256tc(ICLK) 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M UNIT
MASTER (SPInCTRL2.3) CLOCK PHASE (SPInCTRL2[0]) cleared. tc(ICLK) interface clock cycle time f(ICLK) rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table. When master mode, following must true: values from 255: tc(SPC)M +1)tc(ICLK) where prescale value SPInCTL1[12:5] register bits. values tc(SPC)M 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2[1]).
SPInCLK (clock polarity
SPInCLK (clock polarity SPInSIMO Master Data Valid
SPInSOMI
Master Data Must Valid
Figure SPIn Master Mode External Timing (CLOCK PHASE
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SPIn Master Mode External Timing Parameters
(CLOCK PHASE SPInCLK output, SPInSIMO output, SPInSOMI input) (see Figure
tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M tv(SIMO-SPCH)M tv(SIMO-SPCL)M tv(SPCH-SIMO)M tv(SPCL-SIMO)M tsu(SOMI-SPCH)M tsu(SOMI-SPCL)M tv(SPCH-SOMI)M tv(SPCL-SOMI)M Cycle time, SPInCLK Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Valid time, SPInCLK high after SPInSIMO data valid (clock polarity Valid time, SPInCLK after SPInSIMO data valid (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity Setup time, SPInSOMI before SPInCLK high (clock polarity Setup time, SPInSOMI before SPInCLK (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 256tc(ICLK) 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M UNIT
MASTER (SPInCTRL2.3) CLOCK PHASE (SPInCTRL2[0]) set. tc(ICLK) interface clock cycle time f(ICLK) rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table. When master mode, following must true: values from 255: tc(SPC)M +1)tc(ICLK) where prescale value SPInCTL1[12:5] register bits. values tc(SPC)M 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2[1]).
SPInCLK (clock polarity
SPInCLK (clock polarity
SPInSIMO
Master Data Valid
Data Valid
SPInSOMI
Master Data Must Valid
Figure SPIn Master Mode External Timing (CLOCK PHASE
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SPIn SLAVE MODE TIMING PARAMETERS SPIn Slave Mode External Timing Parameters
(CLOCK PHASE SPInCLK input, SPInSIMO input, SPInSOMI output) (see Figure
tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S td(SPCH-SOMI)S td(SPCL-SOMI)S tv(SPCH-SOMI)S tv(SPCL-SOMI)S tsu(SIMO-SPCL)S 6(6) tsu(SIMO-SPCH)S tv(SPCL-SIMO)S 7(6) tv(SPCH-SIMO)S Cycle time, SPInCLK Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Delay time, SPInCLK high SPInSOMI valid (clock polarity Delay time, SPInCLK SPInSOMI valid (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity tc(SPC)S tc(SPC)S 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 256tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) UNIT
MASTER (SPInCTRL2.3) cleared CLOCK PHASE (SPInCTRL2[0]) cleared. slave mode, following must true: tc(SPC)S tc(ICLK), where prescale value SPInCTL1[12:5]. rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table. tc(ICLK) interface clock cycle time /f(ICLK) When SPIn slave mode, following must true: values from 255: tc(SPC)S +1)tc(ICLK) where prescale value SPInCTL1[12:5] register bits. values tc(SPC)S 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2[1]).
SPInCLK (clock polarity
SPInCLK (clock polarity
SPInSOMI SPISOMI Data Valid
SPInSIMO
SPISIMO Data Must Valid
Figure SPIn Slave Mode External Timing (CLOCK PHASE
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SPIn Slave Mode External Timing Parameters
(CLOCK PHASE SPInCLK input, SPInSIMO input, SPInSOMI output) (see Figure
tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S tv(SOMI-SPCH)S tv(SOMI-SPCL)S tv(SPCH-SOMI)S tv(SPCL-SOMI)S tsu(SIMO-SPCH)S 6(6) tsu(SIMO-SPCL)S tv(SPCH-SIMO)S 7(6) tv(SPCL-SIMO)S Cycle time, SPInCLK Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Valid time, SPInCLK high after SPInSOMI data valid (clock polarity Valid time, SPInCLK after SPInSOMI data valid (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK high (clock polarity Setup time, SPInSIMO before SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.5tc(SPC)S 0.5tc(SPC)S 0.5tc(SPC)S 256tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) UNIT
MASTER (SPInCTRL2.3) cleared CLOCK PHASE (SPInCTRL2[0]) set. slave mode, following must true: tc(SPC)S tc(ICLK), where prescale value SPInCTL1[12:5]. rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table. tc(ICLK) interface clock cycle time /f(ICLK) When SPIn slave mode, following must true: values from 255: tc(SPC)S +1)tc(ICLK) where prescale value SPInCTL1[12:5] register bits. values tc(SPC)S 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2[1]).
SPInCLK (clock polarity
SPInCLK (clock polarity
SPInSOMI
SPISOMI Data Valid
Data Valid
SPInSIMO
SPISIMO Data Must Valid
Figure SPIn Slave Mode External Timing (CLOCK PHASE
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK Timing Requirements Internal Clock SCIn Isosynchronous Mode
(see Figure
(BAUD EVEN BAUD tc(SCC) tw(SCCL) tw(SCCH) td(SCCH-TXV) Cycle time, SCInCLK Pulse duration, SCInCLK Pulse duration, SCInCLK high Delay time, SCInCLK high SCInTX valid Valid time, SCInTX data after SCInCLK Setup time, SCInRX before SCInCLK Valid time, SCInRX data after SCInCLK tc(SCC) 2tc(ICLK) 0.5tc(SCC) 0.5tc(SCC) tc(ICLK) 0.5tc(SCC) 0.5tc(SCC) 3tc(ICLK) 0.5tc(SCC) 0.5tc(ICLK) 0.5tc(SCC) 0.5tc(ICLK) (BAUD BAUD (224 tc(ICLK) 0.5tc(SCC) 0.5tc(ICLK) 0.5tc(SCC) 0.5tc(ICLK) UNIT
tv(TX)
tc(SCC)
tsu(RX-SCCL)
tc(ICLK)
tc(ICLK)
tv(SCCL-RX)
-tc(ICLK)
tc(ICLK)
BAUD 24-bit concatenated value formed SCI[H,M,L]BAUD registers. tc(ICLK) interface clock cycle time 1/f(ICLK) rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table.
tc(SCC) tw(SCCH) tw(SCCL) SCICLK tv(TX) td(SCCH TXV) SCITX tsu(RX SCCL) Data Valid Data Valid
tv(SCCL
SCIRX
Data transmission reception characteristics isosynchronous mode with external clocking similar asynchronous mode. Data transmission occurs SCICLK rising edge, data reception occurs SCICLK falling edge.
Figure SCIn Isosynchronous Mode Timing Diagram External Clock
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK Timing Requirements External Clock SCIn Isosynchronous Mode
(see Figure
tc(SCC) tw(SCCH) tw(SCCL) td(SCCH-TXV) tv(TX) tsu(RX-SCCL) tv(SCCL-RX) Cycle time, SCInCLK Pulse duration, SCInCLK high Pulse duration, SCInCLK Delay time, SCInCLK high SCInTX valid Valid time, SCInTX data after SCInCLK Setup time, SCInRX before SCInCLK Valid time, SCInRX data after SCInCLK 2tc(SCC) 2tc(ICLK) 8tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 2tc(ICLK) UNIT
tc(ICLK) interface clock cycle time f(ICLK) rise fall timings, "Switching Characteristics Output Timings versus Load Capacitance" table. When driving external SCInCLK, following must true: tc(SCC) 8tc(ICLK).
tc(SCC) tw(SCCL) SCICLK td(SCCH TXV) SCITX tsu(RX SCCL) tv(TX) tw(SCCH)
Data Valid
tv(SCCL
SCIRX
Data Valid
Data transmission/reception characteristics isosynchronous mode with internal clocking similar asynchronous mode. Data transmission occurs SCICLK rising edge, data reception occurs SCICLK falling edge.
Figure SCIn Isosynchronous Mode Timing Diagram Internal Clock
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
TIMING
Table below assumes testing over recommended operating conditions. Table Signals (SDA SCL) Switching Characteristics
PARAMETER tc(I2CCLK) tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SCLH) th(SDA-SCLL) tw(SDAH) tsu(SCLH-SDAH) tw(SP)
STANDARD MODE devices 3.45
FAST MODE
UNIT
Cycle time, module clock Cycle time, Setup time, high before (for repeated START condition) Hold time, after (for repeated START condition) Pulse duration, Pulse duration, high Setup time, valid before high Hold time, valid after
Pulse duration, high between STOP START conditions Setup time, high before high (for STOP condition) Pulse duration, spike (must suppressed) Capacitive load each line
pins feature fail-safe buffers. These pins could potentially draw current when device powered down. maximum th(SDA-SCLL) devices needs only device does stretch period (tw(SCLL)) signal. total capacitance line
tw(SDAH) tr(SCL) tw(SCLL) tc(SCL) tf(SCL) th(SDA-SCLL) th(SCLL-SDAL) Stop Start th(SCLL-SDAL) tsu(SCLH-SDAL) tw(SCLH) tsu(SDA-SCLH) tw(SP) tsu(SCLH-SDAH)
Repeated
Stop
device must internally provide hold time least signal (referred VIHmin signal) bridge undefined region falling edge SCL. maximum th(SDA-SCLL) needs only device does stretch period (tw(SCLL)) signal. fast-mode I2C-bus device used standard-mode I2C-bus system, requirement tsu(SDA-SCLH) must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line tsu(SDA-SCLH). total capacitance line mixed with HS=mode devices, faster fall-times allowed.
Figure Timings
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
STANDARD CONTROLLER (SCC) MODE TIMINGS Dynamic Characteristics CANSTX CANSRX Pins
PARAMETER td(CANSTX) td(CANSRX) Delay time, transmit shift register CANSTX Delay time, CANSRX receive shift register UNIT
These values include rise/fall times output buffer.
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
EXPANSION MODULE TIMING Expansion Timing Parameters, -40°C 150°C,
(see Figure Figure
tc(CO) td(COH-EBADV) th(COH-EBADIV) td(COH-EBOE) th(COH-EBOEH) td(COL-EBWR) th(COL-EBWRH) tsu(EBRDATV-COH) th(COH-EBRDATIV) td(COL-EBWDATV) th(COL-EBWDATIV) td(COH-EBCS0) th(COH-EBCS0H) tsu(COH-EBHOLDL) tsu(COH-EBHOLDH) Cycle time, CLKOUT Delay time, CLKOUT high EBADDR valid Hold time, EBADDR invalid after CLKOUT high Delay time, CLKOUT high EBOE fall Hold time, EBOE rise after CLKOUT high Delay time, CLKOUT write strobe (EBWR) Hold time, EBWR high after CLKOUT Setup time, EBDATA valid before CLKOUT high (READ) Hold time, EBDATA invalid after CLKOUT high (READ) Delay time, CLKOUT EBDATA valid (WRITE) Hold time, EBDATA invalid after CLKOUT (WRITE) SECONDARY TIMES Delay, CLKOUT high EBCS0 fall Hold, EBCS0 rise after CLKOUT high Setup time, EBHOLD CLKOUT high Setup time, EBHOLD high CLKOUT high 10.9 10.5 13.6 13.2 15.2 (-14.7) 16.1 14.7 20.8 21.4 12.4 11.4 11.4 11.3 11.6 UNIT
Setup time minimum time under worst case conditions. Data with less setup time will work. Valid after CLKOUT goes write cycles.
tc(CO) CLKOUT th(COH-EBADIV)
td(COH-EBADV) EBADDR Valid
tsu(EBRDATV-COH) EBDATA Valid
th(COH-EBRDATIV)
th(COH-EBOEH) td(COH-EBOE) EBOE
td(COH-EBCS0) EBCS0
th(COH-EBCS0H)
tsu(COH-EBHOLDH) tsu(COH-EBHOLDL) EBHOLD Hold State
Figure Expansion Memory Signal Timing Reads
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
tc(CO) CLKOUT th(COH-EBADIV)
td(COH-EBADV) EBADDR td(COL-EBWDATV) EBDATA Valid Valid
th(COL-EBWDATIV)
th(COL-EBWRH) td(COL-EBWR) EBWR td(COH-EBCS0)
td(COH-EBCS0) EBCS0
tsu(COH-EBHOLDH) tsu(COH-EBHOLDL) EBHOLD Hold State
Figure Expansion Memory Signal Timing Writes
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
HIGH-END TIMER (HET) TIMINGS Minimum Output Pulse Width:
This equal high resolution clock period (HRP). defined 6-bit high resolution prescale factor (hr), which user defined, giving prescale factors with linear increment codes. Therefore, minimum output pulse width HRP(min) hr(min)/SYSCLK 1/SYSCLK example, SYSCLK MHz, minimum output pulse width 1/30 33.33ns
Minimum Input Pulses that Captured:
input pulse width must greater equal resolution clock period (LRP), i.e., loop (the program must within LRP). defined 3-bit loop-resolution prescale factor (lr), which user defined, with power increment codes. That value Therefore, minimum input pulse width LRP(min) hr(min) lr(min)/SYSCLK 1/SYSCLK example, with SYSCLK MHz, minimum input pulse width 1/30 33.33
NOTE:
Once input pulse width greater than LRP, resolution measurement still HRP. (That captured value gives number clocks inside pulse.) Abbreviations: high resolution divide rate 3,.63, resolution divide rate High resolution clock period hr/SYSCLK Loop resolution clock period hr*lr/SYSCLK
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
multi-buffered A-to-D converter (MibADC) separate power analog circuitry that enhances A-to-D performance preventing digital switching noise logic circuitry, which could present VCC, from coupling into A-to-D analog stage. A-to-D specifications given with respect ADREFLO unless otherwise noted. Resolution Monotonic Output conversion code bits (1024 values) Assured 3FFh ADREFLO; ADREFHI] Table MibADC Recommended Operating Conditions
ADREFHI ADREFLO IAIC A-to-D high-voltage reference source A-to-D low-voltage reference source Analog input voltage Analog input clamp current (VAI VSSAD VCCAD 0.3) VSSAD VSSAD VSSAD VCCAD VCCAD VCCAD UNIT
VCCAD VSSAD recommended operating conditions, "Device Recommended Operating Conditions" table. Input currents into input channel outside specified limits could affect conversion results other channels.
Table Operating Characteristics Over Full Ranges Recommended Operating Conditions
PARAMETER IAIL IADREFHI EDNL Analog input resistance Analog input capacitance Analog input leakage current ADREFHI input current Conversion range over which specified accuracy maintained Differential nonlinearity error DESCRIPTION/CONDITIONS Figure Figure Figure ADREFHI ADREFLO VSSAD ADREFHI ADREFLO Difference between actual step width ideal value. Figure Maximum deviation from best straight line through MibADC. MibADC transfer characteristics, excluding quantization error. Figure Maximum value difference between analog value ideal midstep value. Figure Conversion Sampling UNIT
EINL
Integral nonlinearity error
Total error/absolute accuracy
VCCAD ADREFHI (ADREFHI ADREFLO)/ MibADC
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
External MibADC Input Sample Switch
Parasitic Capacitance
Sample Capacitor
leak
Figure MibADC Input Equivalent Circuit
Multi-Buffer Timing Requirements
tc(ADCLK) td(SH) td(C) td(SHC)
UNIT
Cycle time, MibADC clock Delay time, sample hold time Delay time, conversion time Delay time, total sample/hold conversion time
0.05 0.55 1.55
This minimum sample/hold conversion time that achieved. These parameters dependent many factors; more details, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
differential nonlinearity error shown Figure (sometimes referred differential linearity) difference between actual step width ideal value LSB.
Analog Input Value (LSB) Differential Linearity Error(1/2 LSB)
Differential Linearity Error(- LSB)
(ADREFHI ADREFLO)/210
Figure Differential Nonlinearity (DNL)
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
integral nonlinearity error shown Figure (sometimes referred linearity error) deviation values actual transfer function from straight line.
Analog Input Value (LSB) Transition 011/100 LSB) End-Point Lin. Error Transition 001/010 LSB) Ideal Transition Actual Transition
(ADREFHI ADREFLO)/210
Figure Integral Nonlinearity (INL) Error absolute accuracy total error MibADC shown Figure maximum value difference between analog value ideal midstep value.
Analog Input Value (LSB) Total Error Step (1/2 LSB)
Total Error Step LSB)
(ADREFHI ADREFLO)/210
Figure Absolute Accuracy (Total) Error
TMS470R1A288 16/32-Bit RISC Flash Microcontroller
SPNS106 SEPTEMBER 2005
Thermal Resistance Characteristics
PARAMETER °C/W
Thermal Resistance Characteristics
PARAMETER °C/W
MECHANICAL DATA
MTQF013A OCTOBER 1994 REVISED DECEMBER 1996
(S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,50
0,27 0,17
0,08
0,13
12,00 14,20 13,80 16,20 15,80 1,45 1,35
Gage Plane
0,05
0,25
0,75 0,45 Seating Plane
1,60
0,08
4040149 11/96 NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF017A OCTOBER 1994 REVISED DECEMBER 1996
(S-PQFP-G144)
PLASTIC QUAD FLATPACK
0,27 0,17 0,08
0,50
0,13
17,50 20,20 19,80 22,20 21,80
Gage Plane
0,05
0,25
1,45 1,35
0,75 0,45
Seating Plane 1,60 0,08
4040147 10/96 NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Other recent searches
K4S64323LF-S - K4S64323LF-S K4S64323LF-S Datasheet
IDT74LVC543A - IDT74LVC543A IDT74LVC543A Datasheet
D1022UK - D1022UK D1022UK Datasheet
BZG04- - BZG04- BZG04- Datasheet
bq2013HEVM - bq2013HEVM bq2013HEVM Datasheet
74LVX32 - 74LVX32 74LVX32 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
