Product data Supersedes data 2003 2004 Product data 13-bit G

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GTL2006 13-bit GTL-/GTL/GTL+ LVTTL translator
Product data Supersedes data 2003 2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
FEATURES
Operates GTL-/GTL/GTL+ LVTTL sampling receiver operation LVTTL tolerant Series termination LVTTL outputs protection exceeds 2000 JESD22-A114,
JESD22-A115 JESD22-C101 LVTTL GTL-/GTL/GTL+ driver
CONFIGURATION
VREF 11BI 10AI1 10AI2 7BO1 7BO2 11BO 10BOI 10BO2
Latch-up testing done JESDEC Standard JESD78 which
exceeds
Package offered: TSSOP28
DESCRIPTION
GTL2006 13-bit translator interface between LVTTL chip Xeonprocessor GTL-/GTL/GTL+ I/O. GTL2006 designed platform health management dual processor applications.
SW01091
Figure configuration
DESCRIPTION
NUMBER 2-6, 10-13, 17-27 SYMBOL VREF NAME FUNCTION reference voltage Data inputs/outputs (LVTTL) Data inputs/outputs (GTL-/GTL/GTL+) Ground Positive supply voltage
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CI/O PARAMETER Propagation delay capacitance CONDITIONS Tamb Outputs disabled; VI/O TYPICAL UNIT
ORDERING INFORMATION
PACKAGES 28-Pin Plastic TSSOP TEMPERATURE RANGE ORDER CODE GTL2006PW TOPSIDE MARK GTL2006 NUMBER SOT361-1
Standard packing quantities other packaging data available www.philipslogic.com/packaging.
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
FUNCTION TABLES
INPUT 1BI/2BI/3BI/4BI/9BI INPUT 10AI1/10AI2 OUTPUT 1AO/2AO/3AO/4AO/9AO INPUT INPUT OUTPUT 10BO1/10BO2 OUTPUT
INPUT 5BI/6BI
INPUT/OUTPUT 5A/6A (OPEN DRAIN)
OUTPUT 7BO1/7BO2
INPUT 11BI
INPUT/OUTPUT (OPEN DRAIN)
OUTPUT 11BO
HIGH voltage level voltage level NOTES: enable 7BO1/7BO2 include delay that prevents transient condition where 5BI/6BI from HIGH, HIGH 5A/6A lags from causing glitch 7BO1/7BO2 outputs. Open Drain Input/Output terminal driven logic state other driver.
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
LOGIC SYMBOL
GTL2006
VREF LVTTL OUTPUTS INPUTS
(OPEN DRAIN) LVTTL (OPEN DRAIN)
7BO1
7BO2
OUTPUTS
LVTTL INPUT INPUT 11BI
DELAY1
11BO
LVTTL (OPEN DRAIN)
INPUT
DELAY1 INPUTS
LVTTL OUTPUTS
10AI1 LVTTL INPUTS 10AI2
10BO1 OUTPUTS 10BO2
LVTTL OUTPUT
SW01092
NOTE: enable 7BO1/7BO2 include delay that prevents transient condition where 5BI/6BI from HIGH, HIGH 5A/6A lags from causing glitch 7BO1/7BO2 outputs. Figure Logic symbol
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
APPLICATION INFORMATION
PLATFORM HEALTH MANAGEMENT VREF CPU1 IERR_L CPU1 THRMTRIP CPU1 PROCHOT CPU2 PROCHOT FORCEPR_L NMI_L 11BI CPU2 IERR_L CPU2 THRMTRIP CPU1 CPU2 SMI_BUFF_L 10AI1 10AI2 7BO1 7BO2 11B0 10BO1 10BO2
CPU1 IERR_L THRMTRIP FORCEPR_L PROCHOT CPU1
FORCEPR_L PROCHOT IERR_L THRMTRIP CPU2 CPU2
GTL2006
SOUTHBRIDGE SOUTHBRIDGE SMI_L OPTIONAL SIGNAL LINE
SW01094
Figure Application diagram
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
Frequently Asked Questions
Question GTL2006 LVTTL inputs, specifically 10AI1 10AI2, when GTL2006 unpowered, these inputs pulled want make sure that there leakage path power rail under this condition. LVTTL inputs HIGH Impedance when device unpowered will there leakage? Answer When device unpowered, LVTTL inputs will high-impedance state will leak they pulled high while device unpowered. Question LVTTL inputs have same unpowered characteristic? Answer Yes. Question What condition other LVTTL output pins when device unpowered? Answer open drain outputs, both LVTTL, will leak power supply they pulled high while device unpowered. inputs will also leak power supply under same conditions. LVTTL totem pole outputs, however, open drain type outputs there will current flow these pins they pulled high when ground. Question When this sequence occurs: 11BI driven time driven time 11BI stops driving time 4)Pin stops driving time there wired-OR glitches 11BO time Answer output 11BI physically wired pin. There will glitch when external driver turns drives LOW, unless external driver long distance away pull-up value. pull-up line current were equally shared, bounce would pull-up voltage, presumably VDD. input threshold input, glitch propagate 11BO. glitch very short propagate, pull-up were higher amplitude would small propagate, external driver were sinking more than half total current, would propagate. external driver weak long away will most likely glitch 11BO, because there will large glitch 11A. Question give some guideline high pull-up resistor value needs avoid glitches 11BO? Answer pin, generally pull-up resistor used pins chosen minimize power rather than match line impedance. Most line impedances range pull-up that even current being sunk GTL2006, initial bounce would only would only last round trip time external driver, provided that external driver sink current, bounce will return LOW. high level GTL2006 pin, bounce would show 11BO pin. Normal choices pull-up would several range, depending speed current considerations. Question Please explain timing specification Characteristics table. Which specific inputs/outputs does cover, transition slow? Answer refers 7BO1 path 7BO2 path. times disable enable times since should reflected 7BO1 7BO2. tPLH corresponds disable time, tPHL corresponds enable time. enable time deliberately slow prevent glitches/false LOWs 7BOn outputs, because drives which open-drain have slow rise time. drives that open-drain that also have slow rise time. Question that examine circuit from data sheet, just little concerned. describe function first: This circuit used monitoring driving PROCHOT#. monitor device Heceta7 part output bi-directional, CPU1_PROCHOT# connected output called PROCHOT#, which goes input call FRCPROCHOT# that comes from 7BO1. When generating PROCHPT# (5BI), want input FRCPROCHOT# (7BO1) also this signal. Scenario driving PROCHOT# input HIGH goes LOW; output HIGH goes following 5BI. output should stay HIGH. input goes HIGH; output goes HIGH following 5BI. output 7BO1 should stay HIGH. Scenario Heceta7 driving CPU1_PROCHOT# input HIGH goes LOW; output 7BO1 HIGH goes following input should stay HIGH. input goes HIGH; output 7BO1 goes HIGH following output should stay HIGH. reason delay enable path that keep output disabled account potentially slow riser time mind, there should also delay block shown path that H-to-L disable driver 7BO1 before signal appears input/output, thus appearing input driver 7BO1. Have characterized what sort glitch 7BO1 output H-to-L transition 5BI? Answer disable 7BO1 comes directly from internal signal, design always disables 7BO1 before propagate 5AI/O back 7BO1. Question operate GTL2006 VREF Answer Yes; operate VREF between adjust high noise margins your application. don't have follow GTL-/GTL/GTL+ specifications. will around VREF within range
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
ABSOLUTE MAXIMUM RATINGS1
accordance with Absolute Maximum System (IEC 134); voltages referenced (ground SYMBOL Tstg TJ(MAX) PARAMETER supply voltage input diode current input voltage3 output diode current output voltage3 Current into output state Current into output HIGH state Storage temperature range Maximum junction temperature port (LVTTL) port(GTL) Output HIGH state; port Output HIGH state; port port port port CONDITIONS RATING -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 +150 +125 UNIT
NOTES: Stresses beyond those listed cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "Recommended Operating Conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. performance capability high-performance integrated circuit conjunction with thermal environment create junction temperatures which detrimental reliability. maximum junction temperature this integrated circuit should exceed 150°C. input output negative voltage ratings exceeded input output clamp current ratings observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Supply voltage GTL- Termination voltage GTL+ Overall VREF Supply voltage GTL- GTL+ Tamb Input voltage HIGH-level HIGH level input voltage LOW-level level input voltage HIGH-level output current LOW-level level output current Operating free-air temperature range port port port port port port port port port CONDITIONS 0.85 1.14 1.35 0.76 0.87 VREF
0.95 1.26 1.65 0.63 0.84 1.10 VREF
UNIT
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages referenced (ground LIMITS SYMBOL PARAMETER TEST CONDITIONS port port port port port
TYP1 VCC-0.2
UNIT
-100 V;VI GND;
port port control inputs port port
NOTES: typical values measured Tamb input output voltage ratings exceeded input output current ratings observed. This increase supply current each input that specified LVTTL voltage level rather than GND.
CHARACTERISTICS (3.3 RANGE)
LIMITS (GTL-) SYMBOL PARAMETER WAVEFORM VREF tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL2 tPLZ tPZH 10BOn 11BI 11BO (I/O) TYP1 LIMITS (GTL) VREF TYP1 LIMITS (GTL+) VREF TYP1 UNIT
tPLH tPHL NOTES: typical values Tamb Includes rise time test load pull-up 11A, pull-up load about rise time.
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
WAVEFORMS
ports; VREF ports
tpulse VOLTAGE WAVEFORMS PULSE DURATION port VREF port port port Output Input tPLH tPHL Output VREF VREF VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES port port INPUT MHz, tPLH tPHL Input VREF VREF
SW00469
Waveform
SW01093
Waveform
OUTPUT
tPZL
tPLZ
SW02235
Waveform
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
PERFORMANCE CURVES
1100 Tamb 1000 Vref (mV) VTH+ VTH- 1000 1100 Tamb Vref (mV) VTH+ VTH-
VTH+ VTH- (mV)
VTH+ VTH- (mV) Vref
Vref
1100 Tamb 1000 Vref (mV) VTH+ VTH-
VTH+ VTH- (mV)
Vref
SW02255
Figure VTH+ VTH- versus VREF
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
TEST CIRCUIT
D.U.T. PULSE GENERATOR D.U.T.
PULSE GENERATOR
Test circuit switching times DEFINITIONS
Load resistor Load capacitance includes probe capacitance Termination resistance should equal ZOUT pulse generators.
SW02066
Figure Load circuit outputs
SW00471
Figure Load circuitry outputs
PULSE GENERATOR D.U.T.
Test Circuit open drain LVTTL DEFINITIONS
Load resistor Load capacitance includes probe capacitance Termination resistance should equal ZOUT pulse generators.
SW02067
Figure Load circuitry open drain LVTTL
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
TSSOP28: plastic thin shrink small outline package; leads; body width
SOT361-1
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
REVISION HISTORY
Date 20040621 Description Product data (9397 13063). Supersedes data 2003 Modifications:
figures numbered. Figure "Logic symbol" modified. Page Frequently asked Questions: questions/answers Page Characteristics (3.3 Range); tPHL GTL+ maximum: change from ns'. "Performance curves" section page
20031218 Product data (9397 12562); 853-2440 01-A14985 dated December 2003.
2004
Product data
13-bit GTL-/GTL/GTL+ LVTTL translator
GTL2006
Data sheet status
Level
Data sheet status
Objective data
Product status
Development
Definitions
This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Preliminary data
Qualification
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products-including circuits, standard cells, and/or software-described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Contact information
additional information please visit Fax: 24825
Koninklijke Philips Electronics N.V. 2004 rights reserved. Printed U.S.A. Date release: 06-04
sales offices addresses send e-mail
Document order number:
9397 13063
2004

Product data Supersedes data 2003 2004 Product data 13-bit G

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