Single-Supply, 2.2Msps, 14-Bit Self-Calibrating Monolithic 14-Bit

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Single-Supply, 2.2Msps, 14-Bit Self-Calibrating Monolithic 14-Bit

Datasheet Thumbnail

Top Searches for this datasheet

19-4776; 11/98
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
Monolithic 14-Bit, 2.2Msps Signal-to-Noise Ratio 83dB Spurious-Free Dynamic Range 91dB Differential Nonlinearity Error: ±0.3LSB Integral Nonlinearity Error: ±1.2LSB Single Analog Supply, Digital Supply Power Dissipation: 269mW On-Demand Self-Calibration Three-State, Two's Complement Output Data
MAX1201
MAX1201 14-bit, monolithic, analog-to-digital converter (ADC) capable conversion rates 2.2Msps. This integrated circuit, built CMOS process, uses fully differential, pipelined architecture with digital error correction short self-calibration procedure that corrects capacitor gain mismatches ensures 14-bit linearity full sample rates. on-chip track-and-hold (T/H) maintains superb dynamic performance Nyquist frequency. MAX1201 operates from single supply. fully differential inputs allow input swing ±VREF. single-ended input also possible using operational amplifiers. reference also differential with positive reference (RFPF) typically connected +4.096V negative reference (RFNF) tied analog ground. Additional sensing pins (RFPS, RFNS) provided compensate resistive divider action that occur finite internal external resistances. power dissipation typically only 269mW sampling rate 2.2Msps. device employs CMOS compatible, 14-bit parallel, two's complement output data format. MAX1201 available 44-pin MQFP package specified over commercial temperature (0°C +70°C) extended (-40°C +85°C) temperature ranges.
Ordering Information
PART MAX1201CMH MAX1201EMH TEMP. RANGE +70°C -40°C +85°C PIN-PACKAGE MQFP MQFP
Configuration
TEST0
RFNS RFNF
xDSL Instrumentation Medical Imaging Scanners Imaging Spectrum Analysis
ST_CAL AGND AVDD AGND AGND AVDD
RFPS RFPF
Applications
VIEW
END_CAL
N.C. N.C.
MAX1201
DVDD DGND DGND DVDD TEST1 TEST2 TEST3
DGND
Maxim Integrated Products
DRVDD
MQFP
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
ABSOLUTE MAXIMUM RATINGS
AVDD AGND, DGND .+7V DVDD DGND, AGND.+7V DRVDD DGND, AGND .+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM.(AGND 0.3V) (AVDD 0.3V) Digital Inputs DGND .-0.3V (DVDD 0.3V) Digital Output (DAV) DGND .-0.3V (DRVDD 0.3V) Other Digital Outputs DGND .-0.3V (DRVDD 0.3V) Continuous Power Dissipation +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C).889mW Operating Temperature Ranges (TA) MAX1201CMH .0°C +70°C MAX1201EMH .-40°C +85°C Storage Temperature Range .-65°C +160°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048, -0.5dBFS, fCLK 4.5056MHz, digital output load 20pF, TMIN TMAX +70°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER SYMBOL Single-ended Differential side Track Mode CONDITIONS 4.096 ±4.096 4.096 1000 ±4.5 UNITS
Input Voltage Range (Notes Input Resistance (Note Input Capacitance Reference Voltage (Note Reference Input Resistance Resolution missing codes; Note Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Full-Power Bandwidth Small-Signal Bandwidth
VREF
After calibration, guaranteed
±1.2 -0.1 ±0.3 ±0.004 -1.7 2.2528 +0.1
Bits %FSR %FSR µVRMS Msps fSAMPLE Cycles
fCLK fSAMPLE fSAMPLE fCLK/2
tACQ tOVR
full-scale step (0.006%)
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
ELECTRICAL CHARACTERISTICS (continued)
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048, -0.5dBFS, fCLK 4.5056MHz, digital output load 20pF, TMIN TMAX +70°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Signal-to-Noise Ratio (Note SYMBOL 100.1kHz 502.7kHz 1.0021MHz Spurious-Free Dynamic Range (Note 100.1kHz SFDR 502.7kHz 1.0021MHz Total Harmonic Distortion (Note 100.1kHz 502.7kHz 1.0021MHz Signal-to-Noise Ratio Distortion (Note POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio PSRR Offset Gain AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS 10pF loads D0-D13 4.75 5.25 5.25 DVDD 100.1kHz SINAD 502.7kHz 1.0021MHz CONDITIONS UNITS
MAX1201
TIMING CHARACTERISTICS
(AVDD +5V, DVDD DRVDD +3.3V, fCLK 4.5056MHz, TMIN TMAX +70°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Conversion Time Clock Period Clock High Time Clock Time Output Delay Pulse Width CLK-to-DAV Rising Edge Data Access Time Relinquish Time Calibration Time SYMBOL tCONV tCLK tDAV tREL tCAL ST_CAL DVDD 20pF CONDITIONS 4/fSAMPLE 113.5 113.5 1/fCLK 17,400 UNITS fCLK cycles
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
DIGITAL INPUT OUTPUT CHARACTERISTICS
(AVDD +5V, DVDD DRVDD +3.3V, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Input Voltage Input High Voltage Input Capacitance Input Voltage Input High Voltage Input Current Input Capacitance Digital Input Current Output Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance CLKVIL CLKVIH ICLK CCLK ILEAKAGE COUT VIN_ VIN_ DVDD ISINK 1.6mA ISOURCE 200µA DVDD VIN_ DVDD AVDD ±0.1 ±0.1 DVDD 0.03 ±0.1 SYMBOL DVDD CONDITIONS UNITS
Note Reference inputs driven operational amplifiers Kelvin-sensed operation. Note unipolar mode, analog input voltage, VINP, must within VREF, VINN VREF where VREF VRFPS VRFNS. differential mode, analog input voltages VINP VINN must within VREF; where VREF VRFPS VRFNS. common-mode voltage inputs VREF Note Minimum maximum parameters tested. Guaranteed design. Note Input resistance varies inversely with sample rate. Note Calibration remains valid temperature changes within ±20°C power-supply variations ±5%. Note specifications shown differential mode.
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
_Typical Operating Characteristics
(AVDD +5V, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, fCLK 4.5056MHz, differential input, +2.048V, calibrated, +25°C, unless otherwise noted.)
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE INPUT AMPLITUDE (fIN 100.1kHz)
MAX1201 toc01
MAX1201
SIGNAL-TO-NOISE PLUS DISTORTION INPUT FREQUENCY
-0.5dBFS
MAX1201 toc02
TOTAL HARMONIC DISTORTION INPUT FREQUENCY
(dB) -6dBFS -20dBFS
MAX1201 toc03
SFDR (dB) INPUT AMPLITUDE (dBFS) dBFS
SINAD (dB)
-6dBFS
-20dBFS
-0.5dBFS 100k
100k
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
SIGNAL-TO-NOISE-RATIO INPUT FREQUENCY
MAX1201 toc04
SIGNAL-TO-NOISE-RATIO PLUS DISTORTION SAMPLE RATE (fIN 100.1kHz)
MAX1201 toc05
TYPICAL FFT, 100.1kHz, 2048 VALUE RECORD
AMPLITUDE (dBFS) -105 -120 -135
MAX1201 toc06
SINAD (dB)
-0.5dBFS
(dB)
-0.5dBFS
-6dBFS
-20dBFS
100k
100k
SAMPLE RATE (sps)
200k
400k
600k
800k
1.2M
INPUT FREQUENCY (Hz)
FREQUENCY (Hz)
TYPICAL FFT, 1.0021MHz, 2048 VALUE RECORD
AMPLITUDE (dBFS) -105 -120 -135 200k 400k 600k 800k 1.2M (LSB) -0.5 -1.0 -1.5
MAX1201 toc07
INTEGRAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1201 toc08
-2.0 -8192 -6144 -4096 -2048
2048 4096 6144 8192
FREQUENCY (Hz)
TWO'S COMPLEMENT OUTPUT CODE
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
Typical Operating Characteristics (continued)
(AVDD +5V, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, fCLK 4.5056MHz, differential input, +2.048V, calibrated, +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1201 toc9
EFFECTIVE NUMBER BITS INPUT FREQUENCY
13.5 13.0 ENOB (BITS) 12.5 12.0 -6dBFS 11.5 11.0 10.5 -20dBFS 100k -0.5dBFS
MAX1201 toc10
14.0
(LSB)
-0.5
-1.0 -8192 -6144 -4096 -2048
10.0 2048 4096 6144 8192 INPUT FREQUENCY (Hz)
TWO'S COMPLEMENT OUTPUT CODE
Description
NAME ST_CAL AGND AVDD DRVDD DGND Digital Input Start Calibration. ST_CAL Normal conversion mode. ST_CAL Start self-calibration. Analog Ground Analog Power Supply, Data Out-of-Range (MSB) Digital Power Supply Output Drivers. +5.25V, DRVDD DVDD. Digital Ground FUNCTION
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
Description (continued)
NAME TEST3 TEST2 TEST1 DVDD (LSB) Test Leave unconnected. Test Leave unconnected. Test Leave unconnected. Digital Power Supply, +5.25V. Input Clock. Receives power from AVDD reduce jitter. Data Valid Clock. Digital Output. This clock used transfer data memory other data-acquisition system. Output Enable: Digital Input. D0-D13 high impedance. bits active. Test Leave unconnected. Common-Mode Voltage. Analog Input. Drive midway between positive negative reference voltages. Positive Reference Voltage. Force Input. Positive Reference Voltage. Sense Input. Negative Reference Voltage. Force Input. Negative Reference Voltage, Sense Input. Positive Input Voltage Connected. internal connection. Negative Input Voltage Digital Output Calibration. END_CAL Calibration progress. END_CAL Normal conversion mode. FUNCTION
MAX1201
TEST0 RFPF RFPS RFNF RFNS N.C. END_CAL
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
Detailed Description
Converter Operation
MAX1201 14-bit, monolithic, analog-to-digital converter (ADC) capable conversion rates 2.2Msps. uses multistage, fully differential, pipelined architecture with digital error correction selfcalibration provide 90dB (typ) spurious-free dynamic range 2.2Msps sampling rate. signal-to-noise ratio, harmonic distortion, intermodulation products also consistent with 14-bit accuracy Nyquist frequency. This makes device suitable applications such xDSL, digital radio, instrumentation, imaging. Figure shows simplified, internal structure ADC. switched-capacitor pipelined architecture used digitize signal high throughput rate. first four stages pipeline resolution quantizer approximate input signal. multiplying digital-to-analog converter (MDAC) stage used subtract quantized analog signal from input. residue then amplified with fixed gain passed next stage. accuracy converter improved digital calibration algorithm which corrects mismatches between capacitors switched capacitor MDAC. Note that pipeline introduces latency four sampling periods between input being sampled output appearing D13-D0. While device handle both singleended differential inputs (see Requirements Reference Analog Signal Inputs), latter mode operation will guarantee best SFDR performance. differential input provides following advantages compared single-ended operation: Twice much signal input span Common-mode noise immunity Virtual elimination even-order harmonics Less stringent requirements input signal processing amplifiers
Requirements Reference Analog Signal Inputs
Fully differential switched capacitor circuits (SC) used both reference analog inputs (Figure This allows either single-ended differential signals used reference and/or analog signal paths. signal voltage these pins (INP, INN, RFP_, RFN_) should neither exceed analog supply rail, AVDD fall below ground.
RFP_
RFN_
AVDD
AGND
STAGE1 MDAC
STAGE2
STAGE3
STAGE4
DVDD ST_CAL DGND DRVDD
CLOCK GENERATOR
CORRECTION CALIBRATION LOGIC END_CAL
MAX1201
OUTPUT DRIVERS
D13-D0
Figure Internal Block Diagram
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
RFPF RFNF
RFPS RFPF
RFNF RFPF RFNS
Figure Simplified MDAC Architecture
Figure Equivalent Input Reference Pins. sense pins should draw current.
Choice Reference
important choose low-noise reference, such MAX6341, which provide both excellent load regulation temperature drift. equivalent input circuit reference pins shown Figure Note that reference pins drive approximately resistance chip. They also drive switched capacitor 21pF. meet dynamic performance, reference voltage required settle 0.0015% within clock cycle. Carefully choose appropriate driving circuit (Figure capacitors reference pins (RFPF, RFNF) provide dynamic charge required during each clock cycle, while amps ensure accuracy reference signals. These capacitors must have dielectric-absorption characteristics, such polystyrene teflon capacitors. reference pins connected either singleended differential voltages within specified maximum levels. Typically, positive reference (RFPF) would driven 4.096V, negative reference (RFNF) connected analog ground. There sense pins, RFPS RFNS, which used with external amplifiers compensate resistive drop these lines, internal external chip. Assure correct reference voltage using proper Kelvin connections sense pins.
VRFP 4.096V
CHIP BOUNDARY RFPF
MAX410
RFPS
VRFN
RFNF
MAX410
RFNS
MAX410
Common-Mode Voltage
switched capacitor circuit analog input allows signals between AGND analog power supply. Since common-mode voltage strong influence performance ADC, best results obtained choosing half difference between reference voltages VRFP VRFN. Achieve
Figure Drive Circuit Reference Pins Common-Mode
this using resistive divider between reference potentials. Figure shows driving circuit good dynamic performance.
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
Analog Signal Conditioning
single-ended inputs, negative analog input (INN) tied common-mode voltage (CM), positive analog input (INP) connected input signal. common-mode voltage must equal common-mode input. take full advantage ADC's superior performance Nyquist frequency, drive chip with differential signals. While communication systems signals inherently available differential mode, medical and/or other applications only provide singleended inputs. this case, convert single-ended signals into differential ones using circuit recommended Figure low-noise, wideband amplifiers, such MAX4108, maintain signal purity over full-power bandwidth MAX1201. Lowpass bandpass filters required improve signal-to-noise-and-distortion ratio incoming signal. low-frequency signals (<100kHz), active filters used. higher frequencies, passive filters more convenient.
Single-Ended Differential Conversion Using Transformers
alternative single-ended differential-ended conversion method balun transformer such CTX03-13675 from Coiltronics. important benefit these transformers their ability level-shift singleended signal, referred ground primary side, optimum common-mode voltages secondary side. frequencies below 20kHz, transformer core begins saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need duty cycle clock. avoid this constraint, MAX1201 provides divide-by-two circuit which relaxes this requirement. clock generator should chosen commensurate with frequency range, amplitude slew rate signal source. slew rate input signal low, jitter requirement clock relaxed. However, slew rate high, clock jitter needs kept minimum. full-scale amplitude input sine wave, maximum possible completely clock jitter given SNRMAX JITTER
MAX4108
example, 1MHz JITTER 10ps RMS, then limit jitter approximately 84dB. Generating such clock source requires low-noise comparator low-phase noise signal generator. clock circuit shown Figure possible solution.
0.1µF CLK_IN
0.1µF
MAX4108
MAX961
V0.1µF
Figure simple circuit generates differential signals from single-ended input referred analog ground. commonmode voltage same
Figure Clock Generation Circuit Using Low-Noise Comparator
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
Calibration Procedure
Since MAX1201 based pipelined architecture, low-resolution quantizers ("coarse ADCs") used approximate input signal. MDACs same resolution then used reconstruct input signal, which subtracted from input residue amplified switched-capacitor gain stage. This residue then passed next stage. accuracy MAX1201 limited precision MDAC, which strongly dependent matching capacitors used. mismatch between capacitors determined stored on-chip memory, which later used during conversion input signal. During calibration procedure, clock must running continuously. ST_CAL (start calibration) initiated positive pulse with minimum width four clock cycles longer than about 17,400 clock cycles (Figure ST_CAL input asynchronous with clock, since retimed internally. With ST_CAL activated, END_CAL goes clock cycles later remains until calibration complete. During this period, reference voltages must stable less than 0.01%; otherwise, calibration will invalid. During calibration, analog inputs used; however, better performance achieved these inputs static. Once END_CAL goes high (indicating that calibration procedure complete), ready conversion. Once calibrated, MAX1201 insensitive small changes (±5%) power supply, voltage, temperature. Following calibration, temperature changes more than ±20°C, device should recalibrated maintain optimum performance.
ST_CAL tCLK END_CAL ~17,400 CYCLES
MAX1201
Figure Timing Start Calibration
D0-D13 tREL
HIGH IMPEDANCE (THREE-STATED)
Figure Timing Access Relinquish- Controlled Output Enable (OE)
Two's Complement Output
MAX1201 outputs data two's complement format. Table shows convert various fullscale inputs into their two's complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNR(MAX) (6.02 1.76)dB reality, there other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, computed taking ratio signal noise which includes spectral components minus fundamental, first nine harmonics, offset.
SAMPLE CLOCK D0-D13
Figure Main Timing Diagram
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
Table Binary Output Codes
SCALE +FSR 1LSB +3/4FSR +1/2FSR +1/4FSR -1/4FSR -1/2FSR -3/4FSR -FSR +1LSB -FSR OFFSET BINARY 1111 1111 1110 0000 1100 0000 1010 0000 1000 0000 0110 0000 0100 0000 0010 0000 0000 0001 0000 0000 ONE'S COMPLEMENT 0111 1111 0110 0000 0100 0000 0010 0000 0000 0000 1111 1111 1101 1111 1011 1111 1001 1111 1000 0000 TWO'S COMPLEMENT 0111 1111 0110 0000 0100 0000 0010 0000 0000 0000 1110 0000 1100 0000 1010 0000 1000 0001 1000 0000
Signal-to-Noise Plus Distortion (SINAD)
SINAD ratio fundamental input frequency's amplitude other output signals. SINAD (dB) [SignalRMS (Noise Distortion)RMS]
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Grounding Power-Supply Decoupling
Grounding power-supply decoupling strongly influence performance MAX1201. 14-bit resolution, unwanted digital crosstalk couple through input, reference, power supply, ground connections; this adversely affects signal-to-noise ratio spurious-free dynamic range. addition, electromagnetic interference (EMI) either couple into generated MAX1201. Therefore, grounding power-supply decoupling guidelines should closely followed. First, multilayer, printed circuit board (PCB) with separate ground power-supply planes recommended. high-speed signal traces lines directly above ground plane. Since MAX1201 separate analog digital ground buses (AGND DGND, respectively), should also have separate analog digital ground sections connected only point (star ground). Digital signals should above digital ground plane analog signals should above analog ground plane. Digital signals should kept away from sensitive analog inputs, reference input senses, common-mode input, clock input.
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists only quantization noise. With input range equal full-scale range ADC, effective number bits calculated follows: ENOB (SINAD 1.76) 6.02
Total Harmonic Distortion (THD)
ratio first nine harmonics input signal fundamental itself. This expressed
where fundamental amplitude, through amplitudes through 9th-order harmonics.
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
MAX1201 three power-supply inputs: analog digital drive (DRVDD). Each AVDD input should decoupled with parallel ceramic chip capacitors values 0.1µF 0.001µF, with these capacitors close possible with shortest possible connection ground plane. DVDD pins should also have separate 0.1µF capacitors again adjacent their respective pins, should DRVDD pin. Minimize digital load capacitance. However, total load capacitance each digital output exceeds 20pF, DRVDD decoupling capacitor should increased preferably, digital buffers should added. power-supply voltages should also decoupled with large tantalum electrolytic capacitors point voltages enter PCB. Ferrite beads with additional decoupling capacitors forming network could also improve performance. analog power-supply input MAX1201 typically +5V, while digital supplies vary from +3V. Usually, DVDD DRVDD pins connected same power supply. Note that DVDD supply voltage must greater than equal voltage. example, digital +3.3V supply could connected DRVDD while cleaner supply connected DVDD resulting slightly improved performance. Alternatively, +3.3V supply could connected both DRVDD DVDD. However, +3.3V supply should connected DVDD while supply connected DRVDD (Table
Table Power-Supply-Voltage Combinations
AVDD DVDD DRVDD ALLOWED/ ALLOWED Allowed Allowed Allowed Allowed
Chip Information
TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED AGND
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating MAX1201
Package Information
MQFP44.EPS
Single-Supply, 2.2Msps, 14-Bit Self-Calibrating
NOTES
MAX1201
Single-Supply, 2.2Msps, 14-Bit Self Calibrating MAX1201
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Single-Supply, 2.2Msps, 14-Bit Self-Calibrating Monolithic 14-Bit

Top Searches for this datasheet

Other recent searches