Single-Supply, 1Msps, 14-Bit Self-Calibrating Monolithic, 14-Bit,

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Single-Supply, 1Msps, 14-Bit Self-Calibrating Monolithic, 14-Bit,

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19-4794; 11/98
Single-Supply, 1Msps, 14-Bit Self-Calibrating
Monolithic, 14-Bit, 1Msps Single Supply 80dB 500kHz SFDR 87dB 500kHz Power Dissipation: 257mW On-Demand Self-Calibration Differential Nonlinearity Error: ±0.3LSB Integral Nonlinearity Error: ±1.2LSB Three-State, Two's Complement Output Data
MAX1205
END_CAL
MAX1205 14-bit, monolithic, analog-to-digital converter (ADC) capable conversion rates 1Msps. This integrated circuit, built CMOS process, uses fully differential, pipelined architecture with digital error correction short self-calibration procedure that corrects capacitor gain mismatches ensures 14-bit linearity full sample rates. on-chip track/hold (T/H) maintains superb dynamic performance Nyquist frequency. MAX1205 operates from single supply. fully differential inputs allow input swing ±VREF. reference also differential, with positive reference (RFPF) typically connected +4.096V negative reference (RFNF) connected analog ground. Additional sensing pins (RFPS, RFNS) provided compensate resistive-divider action that occur finite internal external resistances reference traces on-chip resistance reference pins. single-ended input also possible using operational amplifiers. power dissipation typically 257mW +5V, sampling rate 1Msps. device employs CMOScompatible, 14-bit parallel, two's complement output data format. higher sampling rates, MAX1201 2.2Msps pin-compatible upgrade MAX1205. MAX1205 available MQFP package, operates over commercial (0°C +70°C) extended (-40°C +85°C) temperature ranges.
Ordering Information
PART MAX1205CMH MAX1205EMH TEMP. RANGE +70°C -40°C +85°C PIN-PACKAGE MQFP MQFP
Configuration
VIEW
Imaging Communications Medical Scanners Data Acquisition
ST_CAL AGND AVDD AGND AGND AVDD
Applications
TEST0
RFNS RFNF
RFPS RFPF
N.C. N.C.
MAX1205
DVDD DGND DGND DVDD TEST1 TEST2 TEST3
DGND
Maxim Integrated Products
DRVDD
MQFP
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
Single-Supply, 1Msps, 14-Bit Self-Calibrating MAX1205
ABSOLUTE MAXIMUM RATINGS
AVDD AGND, DGND .+7V DVDD DGND, AGND.+7V DRVDD DGND, AGND .+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM.(AGND 0.3V) (AVDD 0.3V) Digital Inputs DGND .-0.3V (DVDD 0.3V) Digital Output (DAV) DGND .-0.3V (DRVDD 0.3V) Other Digital Outputs DGND .-0.3V (DRVDD 0.3V) Continuous Power Dissipation +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C).889mW Operating Temperature Ranges (TA) MAX1205CMH .0°C +70°C MAX1205EMH .-40°C +85°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, -0.5dBFS, fCLK= 2.048MHz, digital output load 20pF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER ANALOG INPUT Input Voltage Range (Notes Input Resistance (Note Input Capacitance (Note REFERENCE/EXTERNAL Reference Voltage (Note Reference Input Resistance TRANSFER CHARACTERISTICS Resolution missing codes) (Note Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise DYNAMIC SPECIFICATIONS (Note Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Full-Power Bandwidth Small-Signal Bandwidth tACQ tOVR full-scale step (0.006%) fSAMPLE fSAMPLE fCLK 1.024 Msps fSAMPLE Cycles -0.2 After calibration, guaranteed ±1.2 ±0.3 ±0.003 -3.0 +0.2 Bits %FSR %FSR µVRMS VREF 4.096 1000 side track mode Single-ended Differential 4.096 ±4.096 ±4.5 SYMBOL CONDITIONS UNITS
Single-Supply, 1Msps, 14-Bit Self-Calibrating
ELECTRICAL CHARACTERISTICS (continued)
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, -0.5dBFS, fCLK= 2.048MHz, digital output load 20pF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Signal-to-Noise Ratio (Note SYMBOL 99.5kHz 300.5kHz 504.5kHz Spurious-Free Dynamic Range (Note 99.5kHz SFDR 300.5kHz 504.5kHz Total Harmonic Distortion (Note 99.5kHz 300.5kHz 504.5kHz Signal-to-Noise Ratio plus Distortion (Note POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio PSRR Offset Gain AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS 10pF loads D0-D13 4.75 5.25 5.25 DVDD 99.5kHz SINAD 300.5kHz 504.5kHz CONDITIONS 81.5 UNITS
MAX1205
Single-Supply, 1Msps, 14-Bit Self-Calibrating MAX1205
TIMING CHARACTERISTICS
(AVDD ±5%, DVDD DRVDD +3.3V, fCLK 2.048MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Conversion Time Clock Period Clock High Time Clock Time Acquisition Time Output Delay Pulse Width CLK-to-DAV Rising Edge Data Access Time Relinquish Time Calibration Time SYMBOL tCONV tCLK tACQ tDAV tREL tCAL ST_CAL Figure 20pF CONDITIONS fSAMPLE tCLK fCLK 17,400 UNITS fCLK cycles
DIGITAL INPUTS OUTPUTS
(AVDD ±5%, DVDD DRVDD +3.3V, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Input Voltage Input High Voltage Input Capacitance Input Voltage Input High Voltage Input Capacitance Digital Input Current Clock Input Current Output Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance CLKVIL CLKVIH CCLK IIN_ ICLK ILEAKAGE COUT ISINK 1.6mA ISOURCE 200µA DVDD VIN_ DVDD AVDD ±0.1 DVDD 0.03 ±0.1 SYMBOL DVDD CONDITIONS UNITS
Note Reference inputs driven operational amplifiers Kelvin-sensed operation. Note unipolar mode, analog input voltage VINP must within VREF, VINN VREF where VREF VRFPS VRFNS. differential mode, analog inputs must within VREF; where VREF VRFPS VRFNS. common mode inputs VREF Note Minimum maximum parameters tested. Guaranteed design. Note varies inversely with sample rate. Note Calibration remains valid temperature changes within ±20°C power-supply variations ±5%. Note specifications shown differential mode.
Single-Supply, 1Msps, 14-Bit Self-Calibrating
Typical Operating Characteristics
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, differential input, fCLK= 2.048MHz, calibrated, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1205-01
MAX1205
DIFFERENTIAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1205-02
1.00 0.75 0.50
SFDR (dB)
dBFS
(LSB)
(LSB)
0.25 -0.25 -0.50 -0.75 -1.00 -1.25 -8192 -6144 -4096 -2048 2048 4096 6144 8192
-0.5
-1.0 -8192 -6144 -4096 -2048
2048 4096 6144 8192 INPUT AMPLITUDE (dBFS)
TWO'S COMPLEMENT OUTPUT CODE
TWO'S COMPLEMENT OUTPUT CODE
SIGNAL-TO-NOISE RATIO PLUS DISTORTION INPUT FREQUENCY
MAX1205-04
TOTAL HARMONIC DISTORTION INPUT FREQUENCY
MAX1205-05
SIGNAL-TO-NOISE RATIO INPUT FREQUENCY
-0.5dBFS -6dBFS (dB)
MAX1205-06
SINAD (dB) -6dBFS -0.5dBFS
(dB) -20dBFS -6dBFS
-20dBFS 1000 1000 INPUT FREQUENCY (kHz) -0.5dBFS 1000 INPUT FREQUENCY (kHz) -20dBFS
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION SAMPLING RATE (fIN 99.5kHz)
MAX1205-07
TYPICAL (fIN 99.5kHz, 2048 VALUE RECORD)
AMPLITUDE (dBFS) -105 -120 -135
MAX1205-08
-0.5dBFS SINAD (dB)
SAMPLE RATE (Msps)
FREQUENCY (kHz)
MAX1205-03
1.25
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE INPUT AMPLITUDE (fIN 99.5kHz)
Single-Supply, 1Msps, 14-Bit Self-Calibrating MAX1205
Typical Operating Characteristics (continued)
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, differential input, fCLK= 2.048MHz, calibrated, +25°C, unless otherwise noted.)
TYPICAL (fIN 504.5kHz, 2048 VALUE RECORD)
MAX1205-09
EFFECTIVE NUMBER BITS INPUT FREQUENCY
13.5 13.0 ENOB (Bits) 12.5 12.0 11.5 11.0 10.5 10.0 -20dBFS -6dBFS -0.5dBFS
MAX1205-10
14.0
AMPLITUDE (dBFS) -105 -120 -135
1000
FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Description
NAME ST_CAL AGND AVDD DRVDD DGND TEST3 Digital Input Start Calibration. ST_CAL Normal conversion mode. ST_CAL Start self-calibration. Analog Ground Analog Power Supply, Data Out-of-Range (MSB) Digital Power Supply Output Drivers, +5.25V, DRVDD DVDD Digital Ground (LSB) Test Leave unconnected. FUNCTION
Single-Supply, 1Msps, 14-Bit Self-Calibrating
Description (continued)
NAME TEST2 TEST1 DVDD Test Leave unconnected. Test Leave unconnected. Digital Power Supply, +5.25V Input Clock. Receives power from AVDD reduce jitter. Data Valid Clock Output. This clock used transfer data memory other data-acquisition system. Output Enable Input. D0-D13 high impedance. bits active. Test Leave unconnected. Common-Mode Voltage. Analog Input. Drive midway between positive negative reference voltages. Positive Reference Voltage. Force input. Positive Reference Voltage. Sense input. Negative Reference Voltage. Force input. Negative Reference Voltage. Sense input. Positive Input Voltage Connected. internal connection. Negative Input Voltage Digital Output Calibration. END_CAL Calibration progress. END_CAL Normal conversion mode. FUNCTION
MAX1205
TEST0 RFPF RFPS RFNF RFNS N.C. END_CAL
_Detailed Description
Converter Operation
MAX1205 14-bit, monolithic, analog-to-digital converter (ADC) capable conversion rates 1Msps. uses multistage, fully differential pipelined architecture with digital error correction self-calibration provide typically greater than 91dB spuriousfree dynamic range 1Msps sampling rate. signal-to-noise ratio, harmonic distortion, intermodulation products also consistent with 14-bit accuracy Nyquist frequency. This makes device suitable applications such imaging, scanners, data acquisition, digital communications. Figure shows simplified, internal structure ADC. switched-capacitor pipelined architecture used digitize signal high throughput rate. first four stages pipeline low-resolution quantizer approximate input signal. multiplying digital-to-analog converter (MDAC) stage used subtract quantized analog signal from input. residue then amplified with fixed gain
passed next stage. accuracy converter improved digital calibration algorithm which corrects mismatches between capacitors switched capacitor MDAC. Note that pipeline introduces latency four sampling periods between input being sampled output appearing D13-D0. While device handle both single-ended differential inputs (see Requirements Reference Analog Signal Inputs), latter mode operation will guarantee best SFDR performance. differential input provides following advantages compared single-ended operation: Twice much signal input span Common-mode noise immunity Virtual elimination even-order harmonics Less stringent requirements input signal processing amplifiers
Single-Supply, 1Msps, 14-Bit Self-Calibrating MAX1205
RFP_ STAGE1 MDAC RFN_ STAGE2 AVDD STAGE3 AGND STAGE4
DVDD ST_CAL DGND DRVDD
CLOCK GENERATOR
CORRECTION CALIBRATION LOGIC END_CAL
MAX1205
OUTPUT DRIVERS
D13-D0
Figure Internal Block Diagram
Requirements Reference Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) used both reference analog inputs (Figure This allows either single-ended differential signals used reference and/or analog signal paths. signal voltage these pins (INP, INN, RFN_, RFP_) should never exceed analog supply rail, AVDD, should fall below ground.
Choice Reference
important choose low-noise reference, such MAX6341, which provide both excellent load regulation temperature drift. equivalent input circuit reference pins shown Figure Note that reference pins drive approximately
resistance chip. They also drive switched capacitor 21pF. meet dynamic performance, reference voltage required settle 0.0015% within clock cycle. Accomplish this choosing appropriate driving circuit (Figure capacitors reference pins (RFPF, RFNF) provide dynamic charge required during each clock cycle, while amps ensure accuracy reference signals. These capacitors must have dielectric-absorption characteristics, such polystyrene teflon capacitors. reference pins connected either singleended differential voltages within specified maximum levels. Typically positive reference (RFPF) would driven 4.096V, negative reference (RFNF) connected analog ground. There sense pins, RFPS RFNS, which used with
RFPF RFNF RFPF
RFPS RFPF
RFNF RFNS
Figure Simplified MDAC Architecture
Figure Equivalent Input Reference Pins. sense pins should draw current.
Single-Supply, 1Msps, 14-Bit Self-Calibrating
external amplifiers compensate resistive drop these lines, internal external chip. Ensure correct reference voltage using proper Kelvin connections sense pins. gle-ended inputs. this case, convert singleended signals into differential ones using circuit recommended Figure low-noise, wideband amplifiers such MAX4108 maintain signal purity over full-power bandwidth MAX1205 input. Lowpass bandpass signals required improve signal-to-noise-and-distortion ratio incoming signal. low-frequency signals (<100kHz), active filters used. higher frequencies, passive filters more convenient.
MAX1205
Common-Mode Voltage
switched capacitor input circuit analog input allows signals between AGND analog power supply. Since common-mode voltage strong influence performance ADC, best results obtained choosing half difference between reference voltages VRFN. Achieve this using resistive divider between reference potentials. Figure shows typical driving circuit good dynamic performance.
Single-Ended Differential Conversion Using Transformers
alternative single-ended differential-ended conversion method balun transformer such CTX03-13675 from Coiltronics. important benefit these transformers their ability level-shift singleended signals referred ground primary side optimum common-mode voltages secondary side. frequencies below 20kHz, transformer core begins saturate, causing odd-order harmonics.
Analog Signal Conditioning
single-ended inputs negative analog input (INN) connected common-mode voltage (CM), positive analog input (INP) connected input. take full advantage ADC's superior performance Nyquist frequency, drive chip with differential signals. communication systems, signals inherently available differential mode. Medical and/or other applications only provide sin-
Clock Source Requirements
Pipelined ADCs typically need duty cycle clock. avoid this constraint, MAX1205 provides
4.096V
CHIP BOUNDARY RFPF
MAX410
MAX4108
RFPS
MAX410
RFNF
RFNS
MAX4108
MAX410
Figure Drive Circuit Reference Pins CommonMode
Figure simple circuit generates differential signals from single-ended input referred analog ground. commonmode voltage same
Single-Supply, 1Msps, 14-Bit Self-Calibrating MAX1205
divide-by-two circuit, which relaxes this requirement. clock generator should chosen commensurate with frequency range, amplitude, slew rate signal source. slew rate input signal small, jitter requirement clock relaxed. However, slew rate high, clock jitter needs kept minimum. full-scale amplitude input sine wave, maximum possible signal-to-noise ratio (SNR) completely clock jitter given SNRMAX 2fIN JITTER initiated positive pulse with minimum width four clock cycles, longer than about 17,400 clock cycles (Figure ST_CAL input asynchronous with clock, since retimed internally. With ST_CAL activated, END_CAL goes clock cycles later remains until calibration complete. During this period, reference voltages must stable less than 0.01%; otherwise calibration will invalid. During calibration, analog inputs used; however, better performance achieved these inputs static. Once END_CAL goes high (indicating that calibration procedure complete), ready conversion. Once calibrated, MAX1205 insensitive small changes (<5%) power-supply voltage temperature. Following calibration, temperature changes more than ±20°C, device should recalibrated maintain optimum performance.
SAMPLE CLOCK D0-D13
example, 0.5MHz JITTER 20ps RMS, then limit jitter about 84dB. Generating such clock source requires low-noise comparator low-phase-noise signal generator. clock circuit shown Figure possible solution.
Calibration Procedure
Since MAX1205 based pipelined architecture, low-resolution quantizers ("coarse ADCs") used approximate input signal. MDACs same resolution then used reconstruct input signal, which subtracted from input residue amplified gain stage. This residue then passed next stage. accuracy MAX1205 limited precision MDAC, which strongly dependent matching capacitors used. mismatch between capacitors determined stored on-chip memory, which later used during conversion input signal. During calibration procedure, clock must running continuously. ST_CAL (start calibration)
Figure Main Timing Diagram
ST_CAL tCLK 0.1µF CLK_IN 0.1µF END_CAL ~17,400 Cycles
Figure Timing Start Calibration
MAX961
0.1µF D0-D13 tREL
Figure Clock Generation Circuit Using Low-Noise Comparator
Figure Timing Access Relinquish- Controlled Output Enable (OE)
Single-Supply, 1Msps, 14-Bit Self-Calibrating
Two's Complement Output
MAX1205 outputs data two's complement format. Table shows convert various fullscale inputs into their two's complement output codes. effective number bits calculated follows: ENOB (SINAD 1.76) 6.02
MAX1205
Applications Information
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNR(MAX) (6.02N 1.76)dB reality, there other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, computed taking ratio signal noise, which includes spectral components minus fundamental, first nine harmonics, offset.
Total Harmonic Distortion (THD)
ratio first nine harmonics input signal fundamental itself. This expressed 20log
where fundamental amplitude, through amplitudes through order harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD ratio fundamental input frequency's amplitude other output signals: SINAD (dB) 20log [(SignalRMS (Noise Distortion)RMS]
Grounding Power-Supply Decoupling
Grounding power-supply decoupling strongly influence performance MAX1205. 14-bit resolution, unwanted digital crosstalk couple through input, reference, power-supply, ground connections; this adversely affects SFDR. addition, electromagnetic interference (EMI) either couple into generated MAX1205. Therefore, grounding power-supply decoupling guidelines should closely followed.
TWO'S COMPLEMENT 0111.1111 0110.0000 0100.0000 0010.0000 0000.0000 1110.0000 1100.0000 1010.0000 1000.0001 1000.0000 ONE'S COMPLEMENT 0111.1111 0110.0000 0100.0000 0010.0000 0000.0000 1111.1111 1101.1111 1011.1111 1001.1111 1000.0000
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists quantization noise only. With input range equal full-scale range ADC,
Table Two's Complement Conversion
SCALE +FSR 1LSB +3/4FSR +1/2FSR +1/4FSR -1/4FSR -1/2FSR -3/4FSR -FSR 1LSB -FSR OFFSET BINARY 1111.1111 1110.0000 1100.0000 1010.0000 1000.0000 0110.0000 0100.0000 0010.0000 0000.0001 0000.0000
Single-Supply, 1Msps, 14-Bit Self-Calibrating
First, multilayer printed circuit board (PCB) with separate ground power-supply planes recommended. high-speed signal traces directly above ground plane. Since MAX1205 separate analog digital ground buses (AGND DGND respectively), should also have separate analog digital ground sections connected only point (star ground). Digital signals should above digital ground plane analog signals should above analog ground plane. Digital signals should kept away from sensitive analog inputs, reference inputs senses, common-mode input, clock input. MAX1205 three power-supply inputs: analog (AVDD), digital (DVDD), drive (DRVDD). Each AVDD input should decoupled with parallel ceramic-chip capacitors values 0.1µF 0.001µF, with these capacitors close possible with shortest possible connection ground plane. DVDD pins should also have separate 0.1µF capacitors adjacent their respective pins, should pin. Minimize digital load capacitance. However, total load capacitance each digital output exceeds 20pF, DRVDD decoupling capacitor should increased preferably, digital buffers should added. power-supply voltages should decoupled with large tantalum electrolytic capacitors point they enter PCB. Ferrite beads with additional decoupling capacitors forming pi-network improve performance. analog power-supply input MAX1205 typically while digital supplies vary from +3V. Usually, DVDD DRVDD pins connected same power supply. Note that DVDD supply voltage must greater than equal DRVDD voltage. example, digital +3.3V supply could connected DRVDD while cleaner supply connected resulting slightly improved performance. Alternatively, +3.3V supply could connected both However, +3.3V supply should connected DVDD while supply connected DRVDD (Table
MAX1205
Table Power-Supply Voltage Combinations
AVDD DVDD DRVDD ALLOWED/NOT ALLOWED +3.3 +3.3 +3.3 +3.3 Allowed Allowed Allowed Allowed
_Chip Information
TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED AGND
Package Information
MQFP44.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Single-Supply, 1Msps, 14-Bit Self-Calibrating Monolithic, 14-Bit,

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