Single-Supply, 1Msps, 16-Bit Self-Calibrating Monolithic 16-Bit,

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Single-Supply, 1Msps, 16-Bit Self-Calibrating Monolithic 16-Bit,

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19-1413; 12/98
Single-Supply, 1Msps, 16-Bit Self-Calibrating
Monolithic 16-Bit, 1Msps Converter Single Supply ±VREF Differential Input Voltage Range 87dB 100kHz 91dB SFDR 100kHz 273mW Low-Power Dissipation ±0.5LSB Differential Nonlinearity Error Three-State, Two's Complement Output Data On-Demand Self-Calibration Pin-Compatible 14-Bit Versions Available (1Msps MAX1205, 2.2Msps MAX1201)
MAX1200
MAX1200 16-bit, monolithic, analog-to-digital converter (ADC) capable conversion rates 1Msps. This CMOS integrated circuit uses fully differential, pipelined architecture with digital error correction short self-calibration ensure 16-bit linearity full sample rates. on-chip track/hold (T/H) maintains superb dynamic performance Nyquist frequency. MAX1200 operates from single supply. fully differential inputs allow input swing ±VREF. reference also differential with positive reference (RFPF) typically connected +4.096V negative reference (RFNF) connected analog ground. Additional sensing pins (RFPS, RFNS) provided compensate resistive divider action that occur. single-ended input also possible using operational amplifiers. Power dissipation typically only 273mW +5V, sampling rate 1Msps. device employs CMOScompatible, 16-bit parallel, two's complement output data format. higher sampling speed 2.2Msps) lower resolution (14-bit), select MAX1201, pin-compatible version MAX1200. MAX1200 available MQFP package operates over commercial (0°C +70°C) extended-industrial (-40°C +85°C) temperature ranges.
Ordering Information
PART MAX1200ACMH MAX1200BCMH MAX1200AEMH MAX1200BEMH TEMP. RANGE +70°C +70°C -40°C +85°C -40°C +85°C PIN-PACKAGE MQFP MQFP MQFP MQFP (LSB) ±0.5 ±0.5
Configuration
VIEW
TEST0
RFNS RFNF
High-Resolution Imaging Communications Scanners Data Acquisition Instrumentation
ST_CAL AGND AVDD AGND AGND AVDD
RFPS RFPF
N.C. N.C.
Applications
END_CAL
MAX1200
DVDD DGND DGND DVDD TEST1
DRVDD
DGND
MQFP Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
ABSOLUTE MAXIMUM RATINGS
AVDD AGND, DGND .+7V DVDD DGND, AGND.+7V DRVDD DGND, AGND .+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM.(AGND 0.3V) (AVDD 0.3V) Digital Inputs DGND .-0.3V (DVDD 0.3V) Digital Output (DAV) DGND .-0.3V (DRVDD 0.3V) Other Digital Outputs DGND .-0.3V (DRVDD 0.3V) Continuous Power Dissipation +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C).889mW Operating Temperature Ranges (TA) MAX1200_CMH .0°C +70°C MAX1200_EMH.-40°C +85°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, -0.5dBFS, fCLK 2.048MHz; digital output load 20pF; TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER ANALOG INPUT Input Voltage Range (Note Input Resistance (Note Input Capacitance EXTERNAL REFERENCE Reference Voltage (Note Reference Input Resistance TRANSFER CHARACTERISTICS Resolution missing codes; Note Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise DYNAMIC SPECIFICATIONS (Note Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Aperture Jitter Full-Power Bandwidth Small-Signal Bandwidth tACQ tOVR full-scale step (0.006%) fSAMPLE fSAMPLE fCLK 1.024 Msps fSAMPLE Cycles psRMS MAX1200A MAX1200B -0.2 After calibration, guaranteed MAX1200A only ±3.5 ±0.5 ±0.6 ±0.003 +0.2 Bits %FSR %FSR µVRMS VREF RREF 4.096 1000 side track mode Single-ended Differential 4.096 ±4.096 SYMBOL CONDITIONS UNITS
Single-Supply, 1Msps, 16-Bit Self-Calibrating
ELECTRICAL CHARACTERISTICS (continued)
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND, +2.048V, -0.5dBFS, fCLK 2.048MHz; digital output load 20pF; TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER SYMBOL CONDITIONS VRFPS 4.096V, VRFNS AGND Signal-to-Noise Ratio (Note VRFPS 3.5V, VRFNS 1.5V 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 99.5kHz 300.5kHz 504.5kHz 4.75 10pF loads D0-D15 PSRR Offset Gain 80.5 79.5 5.25 5.25 DVDD UNITS
MAX1200
VRFPS 4.096V, VRFNS AGND Spurious-Free Dynamic Range (Note SFDR VRFPS 3.5V, VRFNS 1.5V
VRFPS 4.096V, VRFNS AGND Total Harmonic Distortion (Note VRFPS 3.5V, VRFNS 1.5V
VRFPS 4.096V, VRFNS AGND Signal-to-Noise Ratio plus Distortion (Note SINAD VRFPS 3.5V, VRFNS 1.5V POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
TIMING CHARACTERISTICS (Figures
(AVDD ±5%, DVDD DRVDD +3.3V, fCLK 2.048MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Conversion Time Clock Period Clock HIGH Time Clock Time Acquisition Time Output Delay Pulse Width CLK-to-DAV Rising Edge Data Access Time Relinquish Time Calibration Time SYMBOL tCONV tCLK tACQ tDAV tREL tCAL ST_CAL DVDD 20pF CONDITIONS fSAMPLE tCLK fCLK 17,400 UNITS fCLK Cycles
DIGITAL INPUT OUTPUT CHARACTERISTICS
(AVDD ±5%, DVDD DRVDD +3.3V, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Input Voltage Input HIGH Voltage Input Capacitance Input Voltage Input HIGH Voltage Input Current Input Capacitance Digital Input Current Output Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance VCLK VCLK ICLK CCLK ILEAKAGE COUT DVDD ISINK 1.6mA ISOURCE 200µA DVDD AVDD ±0.1 DVDD 0.03 ±0.1 SYMBOL DVDD CONDITIONS UNITS
Note Reference inputs driven operational amplifiers Kelvin-sensed operation. Note unipolar mode, analog input voltage, VINP, must within VREF, VINN where VREF VRFPS VRFNS. differential mode, analog input voltages VINP VINN must within VREF; where VREF VRFPS VRFNS. common-mode voltage inputs (VRFPS VRFNS) Note varies inversely with sample rate. Note Minimum maximum parameters tested. Guaranteed design. Note Calibration remains valid temperature changes within ±20°C power-supply variations ±5%. Guaranteed design. Note specifications shown differential mode.
Single-Supply, 1Msps, 16-Bit Self-Calibrating
_Typical Operating Characteristics
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +4.096V, VRFNS AGND; +2.048V, differential input, fCLK 2.048MHz, calibrated, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc01
MAX1200
DIFFERENTIAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1200toc02
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE INPUT AMPLITUDE (fIN 99.5kHz)
(dBFS) SFDR (dB) (dBc)
MAX1200toc03
0.75 0.50 (LSB) 0.25 -0.25 -0.50 -0.75
(LSB)
-32768 -16384 16384 32768
-1.0 -32,768
-16,384
16,384
32,768
TWO'S COMPLEMENT OUTPUT CODE
TWO'S COMPLEMENT OUTPUT CODE
INPUT AMPLITUDE (dBFS)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION INPUT FREQUENCY
MAX1200 toc04
TOTAL HARMONIC DISTORTION INPUT FREQUENCY
-20dBFS (dB) (dB) -6dBFS
MAX1200 toc05
SIGNAL-TO-NOISE RATIO INPUT FREQUENCY
-0.5dBFS -6dBFS
vsMAX1200 toc06
SINAD (dB) -20dBFS -6dBFS -0.5dBFS
-0.5dBFS 1000 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) -20dBFS
1000
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION SAMPLING RATE (fIN 99.5kHz)
MAX1200 toc07
TYPICAL FFT, 99.5kHz, 8192 VALUE RECORD
MAX1200 toc08
TYPICAL FFT, 504.5MHz, 8192 VALUE RECORD
AMPLITUDE (dBFS) -105 -120 -135 -150
MAX1200 toc09
AMPLITUDE (dBFS) -105 -120 -135
SINAD (dB)
SAMPLE RATE (Msps)
-150 FREQUENCY (kHz)
FREQUENCY (kHz)
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
Typical Operating Characteristics
(AVDD ±5%, DVDD DRVDD +3.3V, VRFPS +3.5V, VRFNS +1.5V; +2.5V, differential input, fCLK 2.048MHz, calibrated, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc11
DIFFERENTIAL NONLINEARITY TWO'S COMPLEMENT OUTPUT CODE
MAX1200 toc12
(LSB)
SFDR (dB)
(dBFS)
(LSB)
-0.5 -1.0 -1.5 -2.0 -2.5 -32,768 -16,384 16,384 32,768
-0.2 -0.4 -0.6 -0.8 -1.0 -32,768 -16,384 16,384 32,768
(dB)
INPUT AMPLITUDE (dBFS)
TWO'S COMPLEMENT OUTPUT CODE
TWO'S COMPLEMENT OUTPUT CODE
SIGNAL-TO-NOISE RATIO PLUS DISTORTION INPUT FREQUENCY
MAX1200 toc14
TOTAL HARMONIC DISTORTION INPUT FREQUENCY
MAX1200 TOC15
SIGNAL-TO-NOISE RATIO INPUT FREQUENCY
MAX1200 toc16
SINAD (dB) -20dBFS -0.5dBFS
-20dBFS
-0.5dBFS
-6dBFS (dB)
-6dBFS (dB)
-6dBFS
1000 1000 INPUT FREQUENCY (kHz) -0.5dBFS -20dBFS 1000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION SAMPLING RATE (fIN 99.5kHz)
MAX1200 toc17
TYPICAL FFT, 99.5kHz, 8192 VALUE RECORD
MAX1200 toc18
TYPICAL FFT, 504.5MHz, 8192 VALUE RECORD
AMPLITUDE (dBFS) -105 -120 -135 -150
MAX1200 toc19
SINAD (dB) SAMPLE RATE (Msps)
AMPLITUDE (dBFS) -105 -120 -135 -150
FREQUENCY (kHz)
FREQUENCY (kHz)
MAX1200 toc13
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE INPUT AMPLITUDE (fIN 99.5kHz)
Single-Supply, 1Msps, 16-Bit Self-Calibrating
Description
NAME ST_CAL AGND AVDD DRVDD DGND TEST1 DVDD TEST0 RFPF RFPS RFNF RFNS N.C. END_CAL Digital Input Start Calibration. ST_CAL Normal conversion mode. ST_CAL Start self-calibration. Analog Ground Analog Power Supply, Data Out-of-Range (MSB) Digital Power Supply Output Drivers. +5.25V, DRVDD DVDD Digital Ground (LSB) Test connect. Digital Power Supply, +5.25V Input Clock. Receives power from AVDD reduce jitter. Data Valid Clock. This clock used transfer data memory other data acquisition system. Output Enable. D0-D15 high impedance. bits active. Test connect. Common-Mode Voltage. Analog Input. Drive midway between positive negative reference voltages. Positive Reference Voltage, Force Input Positive Reference Voltage, Sense Input Negative Reference Voltage, Force Input Negative Reference Voltage, Sense Input Positive Input Voltage Connected. internal connection. Negative Input Voltage Digital Output Calibration. END_CAL Calibration progress. END_CAL Normal conversion mode. FUNCTION
MAX1200
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
Detailed Description
Converter Operation
MAX1200 16-bit, monolithic analog-to-digital converter (ADC) capable conversion rates 1Msps. uses multistage, fully differential, pipelined architecture with digital error correction self-calibration provide typically 91dB spurious-free dynamic range 1Msps sampling rate. also provides excellent performance Nyquist frequency. This makes device suitable applications such data acquisition, high-resolution imaging, scanners, digital communication, instrumentation. Figure shows simplified, internal structure ADC. switched-capacitor, pipelined architecture used digitize signal high throughput rate. first four stages pipeline low-resolution quantizer approximate input signal. multiplying digital-to-analog converter (MDAC) stage used subtract quantized analog signal from input. residue then amplified with fixed gain passed next stage. accuracy converter improved digital calibration algorithm which corrects mismatches between capacitors switched-capacitor MDAC. Note that pipeline introduces latency four sampling periods between input being sampled output appearing D15-D0. While device handle both single-ended differential inputs (see Requirements Reference Analog Signal Inputs section), latter mode operation will guarantee best SFDR performance. differential input provides following advantages compared single-ended operation: Twice much signal input span Common-mode noise immunity Virtual elimination even-order harmonics Less stringent requirements input signal processing amplifiers
Requirements Reference Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) used both reference analog inputs (Figure This allows either single-ended differential signals used reference and/or analog signal paths. signal voltage these pins (INP, INN, RFP_, RFN_) should never exceed analog supply rail, AVDD, fall below ground.
RFP_
RFN_
AVDD
AGND
STAGE1 MDAC
STAGE2
STAGE3
STAGE4
DVDD ST_CAL DGND DRVDD
CLOCK GENERATOR
CORRECTION CALIBRATION LOGIC END_CAL
MAX1200
OUTPUT DRIVERS
D15-D0
Figure Internal Functional Diagram
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
RFPF RFNF
RFPS RFPF
RFNF RFPF RFNS
Figure Simplified MDAC Architecture
Figure Equivalent Input Reference Pins. sense pins should draw current.
Choice Reference
important choose low-noise reference such MAX6341, which provide both excellent load regulation temperature drift. equivalent input circuit reference pins shown Figure Note that reference pins drive approximately resistance on-chip. They also drive switched capacitor 21pF. meet dynamic performance, reference voltage required settle 0.0015% within clock cycle. Carefully choose appropriate driving circuit (Figure capacitors reference pins (RFPF, RFNF) provide dynamic charge required during each clock cycle, while amps ensure accuracy reference signals. These capacitors must have dielectric-absorption characteristics, such polystyrene teflon capacitors. reference pins connected either singleended differential voltages within specified maximum levels. Typically positive reference (RFPF) would driven +4.096V, negative reference (RFNF) connected analog ground best performance. performance more important application than signal-to-noise ratio, choose lower level, differential voltage such RFPS +3.5V VRFNS +1.5V. There sense pins, RFPS RFNS, which used with external amplifiers compensate resistive drop these lines, internal external chip. Ensure correct reference voltage using proper Kelvin connections sense pins.
VRFP +4.096V CHIP BOUNDARY RFPF
MAX410
RFPS
VRFN
RFNF
MAX410
RFNS
MAX410
Figure Drive Circuit Reference Pins Common-Mode
Common-Mode Voltage
switched-capacitor input circuit analog input allows signals between AGND analog power supply. Since common-mode voltage strong
influence performance ADC, best results obtained choosing RFPS VRFNS) This achieved using resistive divider between reference potentials. Figure shows typical driving circuit good dynamic performance.
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
Analog Signal Conditioning
single-ended inputs, negative analog input (INN) connected common-mode voltage (CM) positive analog input (INP) connected input. take full advantage ADC's superior performance Nyquist frequency, drive chip with differential signals. communication systems signals inherently available differential mode; however medical and/or other applications only provide single-ended inputs. this case, convert single-ended signals into differential ones using circuit recommended Figure low-noise, wideband amplifiers, such MAX4108, maintain signal purity over full-power bandwidth MAX1200 input. Lowpass bandpass signals required improve signal-to-noise distortion incoming signal. low-frequency signals (<100kHz), active filters used. higher frequencies, passive filters more convenient.
Single-Ended Differential Conversion Using Transformers
alternative single-ended differential-ended conversion method balun transformer such CTX03-13675 from Coiltronics. important benefit these transformers their ability level-shift singleended signals referred ground primary side optimum common-mode voltages secondary side. frequencies below 20kHz transformer core begins saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need duty cycle clock. avoid this constraint, MAX1200 provides divide-by-two circuit relax this requirement. clock generator should chosen commensurate with frequency range, amplitude, slew rate signal source. slew rate input signal small, jitter requirement clock relaxed. However, slew rate high, clock jitter needs kept minimum. full-scale amplitude input sine wave, maximum possible signal-to-noise ratio (SNR) completely clock jitter given SNRMAX JITTER
MAX4108
example, 500kHz JITTER 10ps RMS, then limit jitter about 90dB. Generating such clock source requires low-noise comparator low-phase-noise signal generator. clock circuit shown Figure possible solution.
0.1µF 0.1µF CLK_IN
MAX4108
MAX961
0.1µF
Figure simple circuit generates differential signals from single-ended input referred analog ground. commonmode voltage same
Figure Clock Generation Circuit Using Low-Noise Comparator
Single-Supply, 1Msps, 16-Bit Self-Calibrating
Calibration Procedure
Since MAX1200 based pipelined architecture, low-resolution quantizers ("coarse ADCs") used approximate input signal. MDACs same resolution then used reconstruct input signal, which subtracted from input residue amplified gain stage. This residue then passed next stage. accuracy MAX1200 limited precision MDAC, which strongly dependent matching capacitors used. mismatch between capacitors determined stored on-chip memory, which later used during conversion input signal. During calibration procedure, clock must running continuously. ST_CAL (start calibration) initiated positive pulse with minimum width four clock cycles, longer than about 17,400 clock cycles (Figure ST_CAL input asynchronous with clock, since retimed internally. With ST_CAL activated, END_CAL goes clock cycles later remains until calibration complete. During this period, reference voltages must stable less than 0.01%; otherwise calibration will invalid. During calibration, analog inputs used; however, better performance achieved these inputs static. Once END_CAL goes high (indicating that calibration procedure complete), ready conversion. Once calibrated, MAX1200 insensitive small changes (±5%) power-supply voltage temperature. Following calibration, temperature changes more than ±20°C, device should recalibrated maintain optimum performance.
MAX1200
ST_CAL tCLK END_CAL ~17,400 CYCLES
Figure Timing Start Calibration
D0-D15 tREL
HIGH IMPEDANCE (THREE-STATED)
Figure Timing Access Relinquish- Controlled Output Enable (OE)
Two's Complement Output
MAX1200 outputs data two's complement format. Table shows convert various fullscale inputs into their two's complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNR(MAX) (6.02 1.76)dB reality, there other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, computed taking ratio signal noise which includes spectral components minus fundamental, first nine harmonics, offset.
SAMPLE CLOCK D0-D15
Figure Main Timing Diagram
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
Table Two's Complement Output Codes
SCALE +FSR 1LSB +3/4FSR +1/2FSR +1/4FSR -1/4FSR -1/2FSR -3/4FSR -FSR +1LSB -FSR OFFSET BINARY 1111 1111 1110 0000 1100 0000 1010 0000 1000 0000 0110 0000 0100 0000 0010 0000 0000 0001 0000 0000 ONE'S COMPLEMENT 0111 1111 0110 0000 0100 0000 0010 0000 0000 0000 1110 0000 1100 0000 1010 0000 1000 0001 1000 0000 TWO'S COMPLEMENT 0111 1111 0110 0000 0100 0000 0010 0000 0000 0000 1111 1111 1101 1111 1011 1111 1001 1111 1000 0000
Signal-to-Noise Plus Distortion (SINAD)
SINAD ratio fundamental input frequency's amplitude other output signals: SINAD (dB) 20log [SignalRMS (Noise Distortion)RMS]
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Grounding Power-Supply Decoupling
Grounding power-supply decoupling strongly influence performance MAX1200. 16-bit resolution, unwanted digital crosstalk couple through input, reference, power supply, ground connections; this adversely affects SFDR. addition, electromagnetic interference (EMI) either couple into generated MAX1200. Therefore, grounding power-supply decoupling guidelines should closely followed. First, multilayer printed circuit board (PCB) with separate ground power-supply planes recommended. high-speed signal traces directly above ground plane. Since MAX1200 separate analog digital ground buses (AGND DGND respectively), should also have separate analog digital ground sections connected only point (star ground). Digital signals should above digital ground plane analog signals should above analog ground plane. Digital signals should kept away from sensitive analog inputs, reference input senses, common-mode input, clock input.
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists quantization noise only. With input range equal full-scale range ADC, effective number bits calculated follows: ENOB (SINAD 1.76) 6.02
Total Harmonic Distortion (THD)
ratio first nine harmonics input signal fundamental itself. This expressed 20log where fundamental amplitude, through amplitudes through 9th-order harmonics.
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
MAX1200 three power-supply inputs: analog digital drive (DRVDD). Each AVDD input should decoupled with parallel ceramic chip capacitors values 0.1µF 0.001µF, with these capacitors close possible with shortest possible connection ground plane. DVDD pins should also have separate 0.1µF capacitors again adjacent their respective pins, should DRVDD pin. Minimize digital load capacitance. However, total load capacitance each digital output exceeds 20pF, DRVDD decoupling capacitor should increased preferably, digital buffers should added. power-supply voltages should also decoupled with large tantalum electrolytic capacitors point they enter PCB. Ferrite beads with additional decoupling capacitors forming network improve performance. analog power-supply input MAX1200 typically while digital supplies vary from +5V. Usually, DVDD DRVDD pins connected same power supply. Note that DVDD supply voltage must greater than equal DRVDD voltage. example, digital +3.3V supply could connected DRVDD while cleaner supply connected resulting slightly improved performance. Alternatively, +3.3V supply could connected both However, +3.3V supply must connected DVDD while supply connected DRVDD (Table
Table Power-Supply Voltage Combinations
AVDD DVDD +3.3 +3.3 DRVDD +3.3 +3.3 ALLOWED/ ALLOWED Allowed Allowed Allowed Allowed
Chip Information
TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED AGND
Single-Supply, 1Msps, 16-Bit Self-Calibrating MAX1200
Package Information
MQFP44.EPS
Single-Supply, 1Msps, 16-Bit Self-Calibrating
NOTES
MAX1200
Single-Supply, 1Msps, 16-Bit Self Calibrating MAX1200
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Single-Supply, 1Msps, 16-Bit Self-Calibrating Monolithic 16-Bit,

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