VCXO Clock Generator Integrated voltage-controlled crystal oscill
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PLL501-01/-03
VCXO Clock Generator
Integrated voltage-controlled crystal oscillator circuitry (VCXO) (pull range 200ppm minimum). Ideal ADSL (35.328MHz) Set-Top multimedia (27MHz) applications. VCXO tuning range: 0-3.3V. Uses inexpensive fundamental-mode parallel resonant crystals (from 20MHz). Integrated phase-locked loop (PLL) provides pullable output frequency (PLL501-01) (PLL501-03) crystal frequency. 3.3V supply voltage. Small circuit board footprint (8-pin 0.150'' SOIC). 12mA output drives capability level.
CONFIGURATION
XOUT
Table Crystal Output Frequencies
DEVICE PLL501-01 PLL501-03 (MHz) (MHz)
PLL501-XX
DESCRIPTIONS
PLL501-01 PLL501-03 monolithic jitter, high performance CMOS VCXO chips. They allow control output frequency with input voltage (VIN), using cost crystal. While PLL501-03 provides pullable output clock times input crystal frequency, PLL501-01 provides pullable output clock input crystal frequency. This makes PLL501-01 ideal 35.328MHz ADSL applications (using 17.664MHz crystal) 27MHz Set-Top multimedia applications (with 13.5MHz crystal).
Note: Contact PhaseLink custom Frequencies
BLOCK DIAGRAM
VCXO
XOUT
Output Buffer
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
PLL501-01/-03
VCXO Clock Generator
DESCRIPTIONS
Name XOUT Number Type Description Crystal input connection (parallel resonant crystal, 10pF). 3.3V Power Supply. Voltage Input VCXO Frequency Control. Ground Core. Clock Output. 3.3V Power Supply. Ground. Crystal connection.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
PLL501-01/-03
VCXO Clock Generator
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection SYMBOL MIN. MAX. UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
Electrical Specifications PARAMETERS
Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output High Voltage Output Voltage Output High Voltage CMOS level Operating Supply Current Short Circuit Current VIN, VCXO Control Voltage
SYMBOL
CONDITIONS
20MHz Ouput load 10pF
MIN.
TYP.
MAX.
UNITS
3.13 -12mA 12mA -4mA Load
3.47
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
PLL501-01/-03
VCXO Clock Generator
Electrical Specifications PARAMETERS
Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Absolute Jitter Short Circuit Current
SYMBOL
CONDITIONS
PLL501-01 PLL501-03 0.8V 2.0V 2.0V 0.8V Measured 1.4V Short Term
MIN.
TYP.
MAX.
UNITS
Voltage Control Crystal Oscillator PARAMETERS
Stabilization Time VCXO Stabilization Time Output Frequency Synthesis Error VCXO Tuning Range output pullability VCXO Tuning Characteristic
SYMBOL
PLLSTB VCXOSTB
CONDITIONS
From VCXO stable From power valid (Unless otherwise noted Frequency Table) 20MHz; XTAL 250; =10pF 0VVIN3.3V
MIN.
TYP.
MAX.
UNITS
±100
ppm/V
Note: Parameters denoted with asterisk represent nominal characterization data production tested specific limits.
Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX.
Crystal Resonator Frequency Parallel Fundamental Mode
(PLL501-01)
UNITS
(PLL501-03)
Crystal Loading Capacitance Rating Crystal Pullability Recommended
(xtal) (xtal)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
PLL501-01/-03
VCXO Clock Generator
External Components Layout Recommendations PLL501-01/-03 requires minimum number external components proper operation. standard frequency decoupling capacitor 4.7µF more should used between (pin well Additionally, higher frequency decoupling capacitors 0.1µF required between (between between These higher frequency decoupling capacitors must connected close PLL501-01/-03 chip possible, preferably directly next PLL501-01/-03 pins. series termination resistor used clock output. input crystal must connected close chip possible, preferably directly next PLL50101/-03 pins. crystal with higher than 10pF used, will requires additional loading capacitors externally complement internal 10pF PLL501-01/-03: between each crystal electrode GND, close crystal possible, preferably directly next crystal electrodes. Consult PhaseLink recommended suppliers.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
PLL501-01/-03
VCXO Clock Generator
PACKAGE INFORMATION
Narrow SOIC
SOIC Symbol Min. 1.55 0.15 0.35 0.19 4.80 3.81 5.84 0.41 1.27 Max. 1.73 0.18 0.49 0.25 4.98 3.99 6.20 0.89
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
order number this device combination following: Device number, Package type Operating temperature range
PART NUMBER
PLL501-0x
PART NUMBER TEMPERATURATRE
C=COMMERCIAL M=MILITARY
I=INDUSTRAL
S=SOIC
PACKAGE TYPE
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/10/01 Page
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