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Phase Noise VCXO (17MHz 36MHz) VCXO output 17MHz 36MHz range phas
Top Searches for this datasheetPLL500-17 Phase Noise VCXO (17MHz 36MHz) VCXO output 17MHz 36MHz range phase noise (-130 10kHz offset 35.328MHz). CMOS output with tri-state control. 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability output. pull range, linearity. jitter (RMS): 2.5ps period jitter. 3.3V operation. Available 8-Pin SOIC, 6-pin SOT23 packages, DIE. BLOCK DIAGRAM CONFIGURATION VDD* XOUT VDD* Denotes internal Pull-up Only needs connected PLL500-17 DESCRIPTION PLL500-17 cost, high performance phase noise VCXO 36MHz range, providing less than -130dBc 10kHz offset 35.328MHz. very jitter (2.5 period jitter) makes this chip ideal applications requiring voltage controlled frequency sources. Input crystal range from 36MHz (fundamental resonant mode). PLL500-17 FREQUENCY RANGE MULTIPLIER FREQUENCY OUTPUT BUFFER CMOS 8-pin SOIC 6-pin XOUT XTAL VARICAP VCON 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 03/29/05 Page PLL500-17 Phase Noise VCXO (17MHz 36MHz) LAYOUT (812,986) SPECIFICATIONS Name Value XOUT Size Reverse side dimensions Thickness micron micron VCON PLL500-17: C500A0404-04A (0,0) Note: denotes internal pull ASSIGNMENT (8-pin SOIC package) DESCRIPTION (8-pin SOIC package) Name VCON XOUT Pin# Position (µm) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 (µm) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type Description Crystal input pin. power supply pin. Only necessary. Frequency control voltage input pin. Ground pin. Output clock pin. power supply pin. Only necessary. Output Enable input pin. Disables output when low. Internal pull-up enables output default connected low. Crystal output pin. Clock input. (Output Enable) available SOT-26 package, output will always enabled build pull-up resister. ASSIGNMNET DESCRIPTION (6-pin SOIC package) Name XOUT VCON Pin# Type Description Crystal Output pin. Ref. Clock input. Ground pin. Output clock pin. Frequency control voltage input pin. power supply pin. Crystal input pin. 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 03/29/05 Page PLL500-17 Phase Noise VCXO (17MHz 36MHz) ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Protection, Human Body Model SYMBOL MIN. -0.5 -0.5 MAX. +0.5 +0.5 UNITS Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. Note: Operating Temperature guaranteed design parts (COMMERCIAL INDUSTRIAL), tested COMMERCIAL grade only. Electrical Specifications PARAMETERS Input Crystal Frequency Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current 0.8V 2.0V with load 0.3V 3.0V with load Measured 1.4V SYMBOL CONDITIONS MIN. TYP. 1.15 MAX. UNITS Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time VCXO Tuning Range output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON input impedance VCON modulation PWSRR SYMBOL VCXOSTB CONDITIONS From power valid 25MHz; XTAL VCON 3.3V VCON=1.65V, ±1.65V MIN. TYP. MAX. UNITS ppm/V ±150 Frequency change with varied VCON 3.3V, -3dB 2000 Note: Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Jitter Phase Noise Specifications 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 03/29/05 Page PLL500-17 Phase Noise VCXO (17MHz 36MHz) PARAMETERS Period Jitter sigma 1000 samples) Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier CONDITIONS With capacitive decoupling between GND. 36MHz @100Hz offset 36MHz @1kHz offset 36MHz @10kHz offset 36MHz @100kHz offset 36MHz @1MHz offset MIN. TYP. -110 -130 -138 -145 MAX. UNITS dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Voltage CMOS level Output High Voltage CMOS level Output drive current Short Circuit Current VCXO Control Voltage SYMBOL CONDITIONS 36MHz Output load 15pF MIN. TYP. MAX. 3.63 UNITS 2.25 +4mA -4mA <0.4V >2.4V VCON Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating (VCON 1.65V) Maximum Sustainable Drive Level Operating Drive Level C0/C1 SYMBOL (xtal) MIN. TYP. MAX. UNITS Note: crystal must such that oscillates (parallel resonant) nominal frequency when presented Load specified above. crystal requires more load nominal frequency, additional load must added externally. This however reduce pull range. 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 03/29/05 Page PLL500-17 Phase Noise VCXO (17MHz 36MHz) PACKAGE INFORMATION dimensions Narrow SOIC Symbol Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 1.27 6-pin (Dimensions 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 03/29/05 Page PLL500-17 Phase Noise VCXO (17MHz 36MHz) ORDERING INFORMATION part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER order number this device combination following: Device number, Package type Operating temperature range PLL500-17 Part Number Package S=SOIC D=Die NONE= TUBE R=TAPE REEL Temperature C=Commercial Industrial Part Order Number PLL500-17DC PLL500-17SC PLL500-17SC-R PLL500-17SCL PLL500-17SCL-R PLL500-17TC PLL500-17TC-R PLL500-17TCL PLL500-17TCL-R Marking P500-17DC P500-17 P500-17 P500-17L P500-17L P500-17 P500-17 P500-17L P500-17L Package Option (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape Reel) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape Reel) 6-Pin (Tube) 6-Pin (Tape Reel) 6-Pin (Tube) 6-Pin (Tape Reel) PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 01/21/05 Page Other recent searchesZFSC-16-12+ - ZFSC-16-12+ ZFSC-16-12+ Datasheet SGI-1 - SGI-1 SGI-1 Datasheet LP38859 - LP38859 LP38859 Datasheet
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