3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, VOLT TOLERANT BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion Drive Features LVCH16373A High Output Drivers: ±24mA Reduced system switching noise
DESCRIPTION
LVCH16373A 16-bit transparent D-type latch built using advanced dual metal CMOS technology. This high-speed, low-power latch ideal temporary storage data. LVCH16373A used implementing memory address latches, ports, drivers. Output Enable Latch Enable controls organized operate each device 8-bit latches 16-bit latch. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. pins LVCH16373A driven from either 3.3V devices. This feature allows device translator mixed 3.3V/5V supply system. LVCH16373A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
Functional Block Diagram
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4735/-
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Unit
Link
48-1 48-2 48-3
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
CI/O
NOTE: applicable device type.
SSOP/ TSSOP/ TVSOP VIEW
FUNCTION TABLE(1)
Inputs Outputs Q0(2)
DESCRIPTION
Names Description Data Inputs Latch Enable Input Output Enable Input (Active LOW) 3-State Outputs
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance Output level before indicated steady-state input conditions were established.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Latch Outputs enabled Power Dissipation Capacitance Latch Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Output Enable Time Output Disable Time Set-up Time HIGH LOW, data before Hold Time HIGH LOW, data after Pulse Width HIGH Output Skew(2)
2.7V Min. Max. 3.3V±0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
Bus-Hold XXXX evice Type Package ange
373A
Shrink Outline Package (SO48-1) Thin Shrink Outline Package (SO48-2) Thin Very Outline Package (SO48-3) 16-Bit Transparent D-Type Latch State Outputs ouble-Density esistors, ±24m
Bus-hold -40°C +85°C
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3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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