3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT T

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3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT T

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IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT TOLERANT
MICRON CMOS Technology 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 1.27mm pitch SOIC, 0.65mm pitch SSOP, 0.635mm pitch QSOP, 0.65mm pitch TSSOP packages Extended commercial range 40°C +85°C 3.3V ±0.3V, Normal Range 2.3V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin inputs, outputs Volt tolerant Supports insertion Drive Features LVC843A: High Output Drivers: ±24mA Reduced system switching noise
IDT74LVC843A ADVANCE INFORMATION
cally driving highly capacitive relatively low-impedance loads. device particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. nine latches transparent D-type latches. device noninverting data inputs provides true data outputs. buffered output-enable (OE) input used place nine outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without interface pullup components. does affect internal operations latch. Previously stored data retained data entered while outputs highimpedance state. LVC843A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. Inputs driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V system environment.
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
DESCRIPTION:
LVC843A 9-bit bus-interface D-type latch built using advanced dual metal CMOS technology. LVC843A device designed specifi-
Functional Block Diagram
EIGH
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4629/-
IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Unit
8LVC
SO24-2 SO24-7 SO24-8 SO24-9
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25°C, 1.0MHZ)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
8LVC Link
SOIC/ SSOP/ QSOP/ TSSOP VIEW
NOTE: applicable device type.
DESCRIPTION
Names Description Output-enable Input (Active LOW) Preset Input (Active LOW) Latch-enable Input Clear Input (Active LOW) Data Inputs 3-State Outputs
FUNCTION TABLE
Inputs
Outputs
NOTE: HIGH Voltage Level Voltage Level Don't Care High-Impedance Level before indicated steady-state input conditions were established.
IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V, other inputs
8LVC Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
8LVC Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance latch Outputs enabled Power Dissipation Capacitance latch Outputs disabled 2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay, Propagation Delay, Propagation Delay Propagation Delay Output Enable Time Output Disable Time Pulse Duration, Pulse Duration, Pulse Duration, HIGH Setup Time, data before Setup Time, inactive Setup Time, inactive tSK(0) Hold Time, data before Output Skew(2) Min. Max. 3.3V±0.3V Min. Max. Unit Test Conditions 0pF, 10Mhz Typical
Unit
SWITCHING CHARACTERISTICS
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V ±0.3V
TEST CIRCUITS WAVEFORMS PROPAGATION DELAY
VCC(2)= 2.5V ±0.2V Unit
8LVC Link
VCC(1) 2.7V
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
Link
TEST CIRCUITS OUTPUTS
Pulse Generator
LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED OUTPUT SWITCH NORMALLY OPEN HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2 OH-V
Link
D.U.T.
Link
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
SET-UP, HOLD, RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL tREM
Link
Open
8LVC Link
OUTPUT SKEW
INPUT tPLH1 tPHL1
SYNCHRONOUS CONTROL
PULSE WIDTH
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2 tPHL2
tPLH2 tPLH1 tPHL2 tPHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank. Link
IDT74LVC843A 3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
ORDERING INFORMATION
Bus-Hold XXXX ange Device Type Package
utline (gull ing) 24-2) hrink utline acka 24-7) uarte utline ackage 24-8) Thin hrink utlin ackage 24-9)
9-Bit Bus-Interface D-Type Latch with 3-State Outputs, ±24mA
lank
Bus-hold -40°C +85°C
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3.3V CMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT T

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