16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162 low-power, 16-bit

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16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162 low-power, 16-bit

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19-2525; 7/02
16-Bit, +5V, 200ksps with 10µA Shutdown
MAX1162 low-power, 16-bit analog-to-digital converter (ADC) features successive-approximation ADC, automatic power-down, fast 1.1µs wakeup, highspeed interface. MAX1162 operates with single analog supply features separate digital supply, allowing direct interfacing with +2.7V +5.25V digital logic. maximum sampling rate 200ksps, MAX1162 consumes only 2.5mA. Power consumption only 12.5mW (AVDD DVDD +5V) 200ksps (max) sampling rate. AutoShutdownreduces supply current 130µA 10ksps less than 10µA reduced sampling rates. Excellent dynamic performance power, combined with ease small package size (10-pin µMAX 10-pin DFN) make MAX1162 ideal battery-powered data-acquisition applications other circuits with demanding power consumption space requirements. Single-Supply Operation Adjustable Logic Level (+2.7V +5.25V) Input Voltage Range: VREF Internal Track/Hold, 4MHz Input Bandwidth SPI/QSPI/MICROWIRE-Compatible Serial Interface Small 10-Pin µMAX 10-Pin Package Power 2.5mA 200ksps 130µA 10ksps 0.1µA Power-Down Mode
Features
16-Bit Resolution, Missing Codes
MAX1162
Ordering Information
PART MAX1162ACUB TEMP RANGE +70°C +70°C +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PINPACKAGE µMAX µMAX µMAX µMAX µMAX µMAX (LSB)
Applications
Motor Control Industrial Process Control Industrial Modules Data-Acquisition Systems Thermocouple Measurements Accelerometer Measurements Portable- Battery-Powered Equipment
MAX1162AC_B* MAX1162BCUB MAX1162BC_B* MAX1162CCUB MAX1162CC_B* MAX1162AEUB MAX1162AE_B* MAX1162BEUB MAX1162BE_B* MAX1162CEUB MAX1162CE_B*
*Future product-contact factory package availability.
Configuration
Functional Diagram appears data sheet. VIEW
AVDD AGND AGND DVDD DGND DOUT
MAX1162
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp. AutoShutdown trademark Maxim Integrated Products, Inc.
SCLK
µMAX/DFN
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
ABSOLUTE MAXIMUM RATINGS
AVDD AGND .-0.3V DVDD DGND.-0.3V DGND AGND.-0.3V +0.3V AIN, AGND .-0.3V (AVDD 0.3V) SCLK, DGND .-0.3V DOUT DGND .-0.3V (DVDD 0.3V) Maximum Current Into .50mA Continuous Power Dissipation +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) .444mW Operating Temperature Ranges MAX1162_CUB .0°C +70°C MAX1162_EUB .-40°C +85°C Maximum Junction Temperature .+150°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD DVDD +4.75V +5.25V, fSCLK 4.8MHz (50% duty cycle), clocks/conversion (200ksps), VREF +4.096V, CREF 4.7µF, TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER ACCURACY (NOTE Resolution MAX1162A Relative Accuracy (Note MAX1162B MAX1162C Differential Nonlinearity Transition Noise Offset Error Gain Error Offset Drift Gain Drift Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time Serial Clock Frequency Aperture Delay Aperture Jitter Sample Rate Track/Hold Acquisition Time tCONV fSCLK tACQ fSCLK (Note ksps SINAD SFDR -3dB point SINAD 86dB (Note DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 89.5 (Note missing codes over temperature MAX1162C noise ±0.65 ±0.002 ±0.01 MAX1162A MAX1162B ±1.75 LSBRMS %FSR ppm/oC ppm/oC Bits SYMBOL CONDITIONS UNITS
16-Bit, +5V, 200ksps with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(AVDD DVDD +4.75V +5.25V, fSCLK 4.8MHz (50% duty cycle), clocks/conversion (200ksps), VREF +4.096V, CREF 4.7µF, TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER ANALOG INPUT (AIN) Input Range Input Capacitance EXTERNAL REFERENCE Input Voltage Range Input Current DIGITAL INPUTS (SCLK, Input High Voltage Input Voltage Input Leakage Current Input Hysteresis Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Voltage Three-State Output Leakage Current Three-State Output Capacitance POWER SUPPLIES Analog Supply Digital Supply AVDD DVDD 200ksps Analog Supply Current IAVDD DGND 100ksps 10ksps 1ksps 200ksps Digital Supply Current IDVDD DGND, DOUT zeros 100ksps 10ksps 1ksps 4.75 0.01 0.03 0.003 5.25 5.25 COUT ISOURCE 0.5mA, DVDD +2.7V +5.25V ISINK 10mA, DVDD +4.75V +5.25V ISINK 1.6mA, DVDD +2.7V +5.25V DVDD DVDD ±0.1 DVDD 0.25V VHYST DVDD +2.7V +5.25V DVDD +2.7V +5.25V DVDD ±0.1 DVDD DVDD VREF VREF +4.096V, fSCLK 4.8MHz IREF VREF +4.096V, SCLK idle DVDD, SCLK idle 0.01 0.01 AVDD VAIN CAIN VREF SYMBOL CONDITIONS UNITS
MAX1162
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
ELECTRICAL CHARACTERISTICS (continued)
(AVDD DVDD +4.75V +5.25V, fSCLK 4.8MHz (50% duty cycle), clocks/conversion (200ksps), VREF +4.096V, CREF 4.7µF, TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Shutdown Supply Current Power-Supply Rejection Ratio SYMBOL IAVDD IDVDD PSRR CONDITIONS DVDD, SCLK idle AVDD DVDD +4.75V +5.25V, full-scale input (Note UNITS
TIMING CHARACTERISTICS (Figures
(AVDD DVDD +4.75V +5.25V, fSCLK 4.8MHz (50% duty cycle), clocks/conversion (200ksps), VREF +4.096V, TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Acquisition Time SCLK DOUT Valid Fall DOUT Enable Rise DOUT Disable Pulse Width Fall SCLK Rise Setup Rise SCLK Rise Hold SCLK High Pulse Width SCLK Pulse Width SCLK Period SYMBOL tACQ tCSW tCSS tCSH CDOUT 50pF CDOUT 50pF CDOUT 50pF CONDITIONS UNITS
TIMING CHARACTERISTICS (Figures
(AVDD +4.75V +5.25V, DVDD +2.7V +5.25V, fSCLK 4.8MHz (50% duty cycle), clocks/conversion (200ksps), VREF +4.096V, TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Acquisition Time SCLK DOUT Valid Fall DOUT Enable Rise DOUT Disable Pulse Width Fall SCLK Rise Setup Rise SCLK Rise Hold SCLK High Pulse Width SCLK Pulse Width SCLK Period SYMBOL tACQ tCSW tCSS tCSH CDOUT 50pF CDOUT 50pF CDOUT 50pF CONDITIONS UNITS
Note AVDD DVDD +5V. Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Offset reference errors nulled. Note Conversion time defined number clock cycles multiplied clock period; clock duty cycle. Note Defined change positive full scale caused variation nominal supply voltage.
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
Typical Operating Characteristics
(AVDD DVDD +5V, fSCLK 4.8MHz, CLOAD 50pF, CREF 4.7µF, VREF +4.096V, +25°C, unless otherwise noted.)
MAX1162
MAX1162 toc02 MAX1162 toc03
OUTPUT CODE
MAX1162 toc01
OUTPUT CODE
(LSB) -0.5 -1.0 -1.5 -2.0 MAGNITUDE (dB) -100 -120 -140 13107 26214 39322 52429 65536 OUTPUT CODE
(LSB) -0.5 -1.0 -1.5 -2.0 13107 26214 39322 52429
65536
OUTPUT CODE
FREQUENCY (kHz)
SINAD FREQUENCY
MAX1162 toc04
SFDR FREQUENCY
SFDR (dB)
MAX1162 toc05
FREQUENCY
-100 -110 -120
MAX1162 toc06
SINAD (dB)
(dB)
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT CONVERSION RATE
MAX1162 toc07
SUPPLY CURRENT SUPPLY VOLTAGE
MAX1162 toc08
SUPPLY CURRENT TEMPERATURE
MAX1162 toc09
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.01
0.001 0.0001 0.01
1000 4.75 4.85 4.95 5.05 5.15 5.25 CONVERSION RATE (kHz) SUPPLY VOLTAGE
TEMPERATURE (°C)
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
Typical Operating Characteristics (continued)
(AVDD DVDD +5V, fSCLK 4.8MHz, CLOAD 50pF, CREF 4.7µF, VREF +4.096V, +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE
MAX1162 toc10
SHUTDOWN SUPPLY CURRENT TEMPERATURE
MAX1162 toc11
ISHDN (nA) 4.75 4.85 4.95 5.05 5.15
SHUTDOWN SUPPLY CURRENT (nA)
5.25
SUPPLY VOLTAGE
TEMPERATURE (°C)
OFFSET ERROR ANALOG SUPPLY VOLTAGE
MAX1162 toc12
OFFSET ERROR TEMPERATURE
OFFSET ERROR (µV) -200 -400 -600 -800 -1000
MAX1162 toc13
1000 OFFSET ERROR (µV) -200 -400 -600 -800 -1000 4.75 4.85 4.95 5.05 5.15
1000
5.25
SUPPLY VOLTAGE
TEMPERATURE (°C)
GAIN ERROR ANALOG SUPPLY VOLTAGE
MAX1162 toc14
GAIN ERROR TEMPERATURE
0.015 0.010 GAIN ERROR 0.005 -0.005 -0.010 -0.015 -0.020
MAX1162 toc15
0.020 0.015 0.010 GAIN ERROR 0.005 -0.005 -0.010 -0.015 -0.020 4.75 4.85 4.95 5.05 5.15
0.020
5.25
SUPPLY VOLTAGE
TEMPERATURE (°C)
16-Bit, +5V, 200ksps with 10µA Shutdown
Description
NAME AVDD AGND FUNCTION External Reference Voltage Input. Sets analog voltage range. Bypass AGND with 4.7µF capacitor. Analog Supply Voltage. Bypass AGND (pin with 0.1µF capacitor. Analog Ground. Connect pins together. Place star ground Active-Low Chip-Select Input. Forcing high places MAX1162 shutdown with typical current 0.1µA. high-to-low transition activates normal operating mode initiates conversion. Serial Clock Input. SCLK drives conversion process clocks data data rates 4.8MHz. Serial Data Output. Data changes state SCLK's falling edge. DOUT high impedance when high. Digital Ground Digital Supply Voltage. Bypass DGND with 0.1µF capacitor. Analog Input
MAX1162
SCLK DOUT DGND DVDD
Detailed Description
MAX1162 includes input track-and-hold (T/H) successive-approximation register (SAR) circuitry convert analog input signal digital 16-bit output. Figure shows MAX1162 simplest configuration. serial interface requires only three digital lines (SCLK, DOUT) provides easy interface microprocessors (µPs). MAX1162 power modes: normal shutdown. Driving high places MAX1162 shutdown, reducing supply current 0.1µA (typ), while pulling places MAX1162 normal operating mode. Falling edges initiate conversions that driven SCLK. conversion result available DOUT unipolar serial format. serial data stream consists eight zeros followed data bits (MSB first). Figure shows interface timing diagram.
During acquisition, analog input (AIN) charges capacitor CDAC. acquisition interval ends falling edge sixth clock cycle (Figure this instant, switches open. retained charge CDAC represents sample input. hold mode, capacitive digital-to-analog converter (DAC) adjusts during remainder conversion cycle restore node ZERO zero within limits 16-bit resolution. conversion, force high then reset input side CDAC switches back AIN, charge CDAC input signal again. time required acquire input signal function quickly input capacitance charged. input signal's source impedance high, acquisition time lengthens more time must allowed between conversions. acquisition time (tACQ) maximum time device takes acquire signal. following formula calculate acquisition time: tACQ 13(RS RIN) 35pF where 800, input signal's source impedance, never less than 1.1µs. source impedance less than does significantly affect ADC's performance. improve input signal bandwidth under conditions, drive with wideband buffer (>4MHz) that drive ADC's input capacitance settle quickly.
Analog Input
Figure illustrates input sampling architecture ADC. voltage applied sets full-scale input voltage. Track-and-Hold (T/H) track mode, analog signal acquired internal hold capacitor. hold mode, switches open capacitive samples analog input.
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
DOUT DGND CLOAD 50pF DOUT CLOAD 50pF DGND HIGH-Z DOUT DGND HIGH-Z CLOAD 50pF DOUT
CLOAD 50pF DGND HIGH-Z
Figure Load Circuits DOUT Enable Time SCLK DOUT Delay Time
Figure Load Circuits DOUT Disable Time
tCSW tCSS SCLK tCSH
DOUT
TIMING SCALE.
Figure Detailed Serial Interface Timing
Input Bandwidth ADC's input tracking circuitry 4MHz smallsignal bandwidth, possible digitize highspeed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid aliasing unwanted high-frequency signals into frequency band interest, anti-alias filtering. Analog Input Protection Internal protection diodes, which clamp analog input AVDD AGND, allow input swing from AGND 0.3V AVDD 0.3V, without damaging device. analog input exceeds 300mV beyond supplies, limit input current 10mA.
VREF 4.7µF 0.1µF 0.1µF
AVDD DVDD MAX1162
SCLK DOUT
SCLK DOUT
AGND DGND
Figure Typical Operating Circuit
16-Bit, +5V, 200ksps with 10µA Shutdown
Digital Interface
Initialization after Power-Up Starting Conversion
digital interface consists inputs, SCLK output, DOUT. logic high places MAX1162 shutdown (AutoShutdown) places DOUT high-impedance state. logic places MAX1162 fully powered mode. start conversion, pull low. falling edge initiates acquisition. SCLK drives conversion shifts conversion results (MSB first) DOUT.
CSWITCH TRACK CAPACITIVE ZERO HOLD HOLD CDAC 32pF TRACK
MAX1162
AUTO-ZERO RAIL
Timing Control
Conversion-start data-read operations controlled SCLK digital inputs (Figures Ensure that duty cycle SCLK between 4.8MHz (the maximum clock frequency). lower clock frequencies, ensure that minimum high times least 65ns. Conversions with SCLK rates less than 100kHz result reduced accuracy leakage. Note: Coupling between SCLK analog inputs (AIN REF) result offset. Variations frequency, duty cycle, other aspects clock signal's shape result changing offset. falling edge initiates acquisition sequence. analog input stored capacitive DAC, DOUT changes from high impedance logic low, begins convert after sixth clock cycle. SCLK drives conversion process shifts conversion result DOUT. SCLK begins shifting data (MSB first) after falling edge SCLK pulse. Twenty-four falling
Figure Equivalent Input Circuit
clock edges needed shift eight leading zeros data bits. Extra clock pulses occurring after conversion result been clocked out, prior rising edge produce trailing zeros DOUT have effect converter operation. Force high after reading conversion's reset internal registers place MAX1162 shutdown. maximum throughput, force again initiate next conversion immediately after specified minimum time (tCSW). Note: Forcing high middle conversion immediately aborts conversion places MAX1162 shutdown.
Output Coding Transfer Function
SCLK DOUT
tCSS tACQ tCSH
Figure External Timing Diagram
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
COMPLETE CONVERSION SEQUENCE
DOUT CONVERSION CONVERSION
POWERED TIMING SCALE.
POWERED DOWN
POWERED
Figure Shutdown Sequence
data output from MAX1162 binary Figure depicts nominal transfer function. Code transitions occur halfway between successive-integer values (VREF 4.096V 1LSB 63µV 4.096V/65536).
OUTPUT CODE FULL-SCALE TRANSITION
Applications Information
External Reference
MAX1162 requires external reference with +3.8V AVDD voltage range. Connect external reference directly REF. Bypass AGND (pin with 4.7µF capacitor. When using low-ESR bypass capacitor, 0.1µF ceramic capacitor parallel with 4.7µF capacitor. Noise reference degrades conversion accuracy. input impedance currents. During conversion external reference must deliver 100µA load current have output impedance less. optimal performance, buffer reference through bypass input. Consider MAX1162's equivalent input noise (38µV when choosing reference.
INPUT VOLTAGE (LSB)
VREF 1LSB 65536
3/2LSB
Figure Unipolar Transfer Function, Full Scale (FS) VREF, Zero Scale (ZS)
Input Buffer
Most applications require input buffer amplifier achieve 16-bit accuracy. input signal multiplexed, switch input channel immediately after acquisition, rather than near after conversion (Figure This allows maximum time input buffer amplifier respond large step change input signal. input amplifier must have slew rate least 2V/µs complete required output voltage change before beginning acquisition time. beginning acquisition, internal sampling capacitor array connects (the amplifier output),
causing some output disturbance. Ensure that sampled voltage settled before acquisition time. Digital Noise Digital noise couple REF. conversion clock (SCLK) other digital signals active during input acquisition contribute noise conversion result. Noise signals synchronous with sampling interval result effective input offset. Asynchronous signals produce random noise input, whose high-frequency components aliased into frequency band interest. Minimize noise presenting impedance frequencies contained
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
4-TO-1
MAX1162
CONVERSION ACQUISITION
TIMING SCALE.
CHANGE INPUT HERE
Figure Change Multiplexer Input Near Beginning Conversion Allow Time Slewing Settling
noise signal) inputs. This requires bypassing AGND, buffering input with amplifier that small-signal bandwidth several MHz, preferably both. 4MHz (typ) bandwidth. Distortion Avoid degrading dynamic performance choosing amplifier with distortion much less than MAX1162's total harmonic distortion (THD -102dB 1kHz) frequencies interest. chosen amplifier insufficient common-mode rejection, which results degraded performance, inverting configuration (positive input grounded) eliminate errors from this source. temperature-coefficient, gain-setting resistors reduce linearity errors caused resistance changes selfheating. reduce linearity errors finite amplifier gain, amplifier circuits with sufficient loop gain frequencies interest.
Accuracy improve accuracy, choose buffer with offset much less than MAX1162's offset (1mV (max) supply), whose offset trimmed while maintaining stability over required temperature range.
Serial Interfaces
MAX1162's interface fully compatible with SPI, QSPI, MICROWIRE standard serial interfaces. serial interface available, establish CPU's serial interface master, that generates serial clock MAX1162. Select clock frequency between 100kHz 4.8MHz: general-purpose line pull low. Activate SCLK minimum clock cycles. serial data stream eight leading zeros followed conversion result begins falling edge DOUT transitions SCLK's falling edge output available MSB-first
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
format. Observe SCLK DOUT valid timing characteristic. Clock data into SCLK's rising edge. Pull high after 24th falling clock edge. remains low, trailing zeros clocked after least significant LSB). With high, wait least 50ns (tCSW) before starting conversion pulling low. conversion aborted pulling high before conversion ends. Wait least 50ns before starting conversion. Data output three 8-bit sequences continuously. bytes contain results conversion padded with eight leading zeros before MSB. serial clock been idled after (D0) been kept low, DOUT sends trailing zeros.
MICROWIRE Interfaces
When using (Figure 10a) MICROWIRE (Figure 10b) interfaces, CPOL CPHA Conversion begins with falling edge (Figure 10c). Three consecutive 8-bit readings necessary obtain entire 16-bit result from ADC. DOUT data transitions serial clock's falling edge. first 8-bit data stream contains leading zeros. second 8-bit data stream contains through third 8-bit data stream contains through
QSPI Interface
Using high-speed QSPI interface with CPOL CPHA MAX1162 supports maximum fSCLK 4.8MHz. Figure shows MAX1162 connected QSPI master Figure shows associated interface timing.
MISO
SCLK DOUT MICROWIRE
SCLK DOUT
MAX1162
MAX1162
Figure 10a. Connections
BYTE READ SCLK
Figure 10b. MICROWIRE Connections
BYTE READ
DOUT*
*WHEN HIGH, DOUT HIGH-Z BYTE READ
HIGH-Z TIMING SCALE.
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL CPHA
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
QSPI MISO
SCLK DOUT
MAX1162
Figure 11a. QSPI Connections
SCLK DOUT*
ACQUISITION
HIGH-Z
*WHEN HIGH, DOUT HIGH-Z
Figure 11b. QSPI Interface Timing Sequence (CPOL CPHA
PIC16 with Module PIC17 Interface
MAX1162 compatible with PIC16/PIC17 microcontroller (µC) using synchronous serial-port (SSP) module. establish communication, connect controller shown Figure 12a. Configure PIC16/PIC17 system master, initializing synchronous serial-port control register (SSPCON) synchronous serial-port status register (SSPSTAT) patterns shown Tables mode, PIC16/PIC17 allows bits data synchronously transmitted received simulta-
SCLK DOUT
PIC16/17
MAX1162
Figure 12a. Interface Connection PIC16/PIC17
Table Detailed SSPCON Register Contents
CONTROL WCOL SSPOV SSPEN SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX1162 SETTINGS Synchronous Serial-Port Mode Select Bit. Sets master mode selects fCLK fOSC SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Receive Overflow Detect Synchronous Serial-Port Enable Bit: Disables serial port configures these pins port pins. Enables serial port configures SCK, SDO, pins serial port pins. Clock Polarity Select Bit. master mode selection.
Don't care.
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
Table Detailed SSPSTAT Register Contents
CONTROL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX1162 SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) Data Input Sample Phase. Input data sampled middle data output time. Clock Edge Select Bit. Data transmitted rising edge serial clock. Data Address Stop Start Read/Write Information Update Address Buffer Full Status
Don't care.
BYTE READ SCLK
BYTE READ
DOUT*
*WHEN HIGH, DOUT HIGH-Z
BYTE READ
HIGH-Z TIMING SCALE.
Figure 12b. Interface Timing with PIC16/PIC17 Master Mode (CKE SSPM3 SSPM0 0001)
neously. Three consecutive 8-bit readings (Figure 12b) necessary obtain entire 16-bit result from ADC. DOUT data transitions serial clock's falling edge clocked into SCLK's rising edge. first 8-bit data stream contains zeros. second 8-bit data stream contains through third 8-bit data stream contains bits through
tion, once offset gain errors have been nulled. static linearity parameters MAX1162 measured using endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) difference between actual step width ideal value 1LSB. error specification 1LSB guarantees missing codes monotonic transfer function.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) deviation values actual transfer function from straight line. This straight line either best-fit straight line line drawn between endpoints transfer func14
Aperture Definitions
Aperture jitter (tAJ) sample-to-sample variation time between samples. Aperture delay (tAD) time between falling edge sampling clock instant when actual sample taken.
16-Bit, +5V, 200ksps with 10µA Shutdown
ENOB (SINAD 1.76) 6.02 Figure shows effective number bits function MAX1162's input frequency.
MAX1162
ENOB INPUT FREQUENCY
EFFECTIVE BITS INPUT FREQUENCY (kHz)
Total Harmonic Distortion
Total harmonic distortion (THD) ratio first five harmonics input signal fundamental itself. This expressed
where fundamental amplitude through 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Figure Effective Number Bits Input Frequency
Signal-to-Noise Ratio
waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization noise error only results directly from ADCs resolution bits): (6.02 1.76)dB reality, there other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
Spurious-free dynamic range (SFDR) ratio amplitude fundamental (maximum signal component) value next largest frequency component.
Supplies, Layout, Grounding, Bypassing
boards with separate analog digital ground planes. wire-wrap boards. Connect ground planes together MAX1162 (pin Isolate digital supply from analog with lowvalue resistor (10) ferrite bead when analog digital supplies come from same source (Figure 14).
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) ratio fundamental input frequency's amplitude equivalent other output signals, excluding offset. SignalRMS SINAD(dB) (Noise Distortion)
VREF 4.7µF 0.1µF 0.1µF DVDD AGND DGND AVDD MAX1162 SCLK DOUT SCLK DOUT
Effective Number Bits
Effective number bits (ENOB) indicate global accuracy specific input frequency sampling rate. ideal error consists quantization noise only. With input range equal fullscale range ADC, calculate effective number bits follows:
Figure Powering AVDD DVDD from Single Supply
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
Constraints sequencing power supplies inputs follows: Apply AGND before DGND. Apply after AVDD AGND present. DVDD independent supply sequencing. Ensure that digital return currents pass through analog ground that return-current paths impedance. current flowing through board ground trace impedance only 0.05 creates error voltage about 250µV, 4LSB error with fullscale system. board layout should ensure that digital analog signal lines kept separate. analog digital (especially SCLK DOUT) lines parallel another. must cross another, right angles. ADCs high-speed comparator sensitive highfrequency noise AVDD power supply. Bypass excessively noisy supply analog ground plane with 0.1µF capacitor parallel with 10µF low-ESR capacitor. Keep capacitor leads short best supply-noise rejection.
Functional Diagram
AVDD DVDD
AGND TRACK HOLD 16-BIT OUTPUT BUFFER DOUT
SCLK
CONTROL
MAX1162
DGND
Chip Information
TRANSISTOR COUNT: 12,100 PROCESS: BiCMOS
16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
10LUMAX.EPS
INCHES 0.043 0.006 0.002 0.030 0.037 0.120 0.116 0.118 0.114 0.120 0.116 0.118 0.114 0.199 0.187 0.0157 0.0275 0.037 0.007 0.0106 0.0197 0.0035 0.0078 0.0196
MILLIMETERS 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 0.177 0.270 0.500 0.090 0.200 0.498
0.50±0.1 0.6±0.1
0.6±0.1
VIEW
BOTTOM VIEW
GAGE PLANE
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, uMAX/uSOP
APPROVAL DOCUMENT CONTROL REV.
21-0061
Note: Contact factory package outline.
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

16-Bit, +5V, 200ksps with 10µA Shutdown MAX1162 low-power, 16-bit

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