Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel
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19-2524; 7/02
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
MAX1190 3.3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving ADCs. MAX1190 optimized power, small size, high-dynamic performance applications imaging, instrumentation, digital communications. This operates from single 2.8V 3.6V supply, consuming only 492mW while delivering typical signal-to-noise distortion (SINAD) 57dB input frequency 60MHz sampling rate 120Msps. driven input stages incorporate 400MHz (-3dB) input amplifiers. converters also operated with single-ended inputs. addition operating power, MAX1190 features sleep mode, well power-down mode conserve power during idle periods. internal 2.048V precision bandgap reference sets full-scale range ADC. flexible reference structure allows this internal externally applied reference, desired, applications requiring increased accuracy different input voltage range. MAX1190 features parallel, CMOS-compatible threestate outputs. digital output format two's complement straight offset binary through single control pin. device provides separate output power supply 1.7V 3.6V flexible interfacing with various logic families. MAX1190 available 7mm, 48-pin TQFP-EP package, specified extended industrial (-40°C +85°C) temperature range. Pin-compatible lower speed versions MAX1190 also available. Refer MAX1180-MAX1184 data sheets 105Msps/80Msps/65Msps/40Msps. addition these speed grades, this family includes multiplexed output versions (MAX1185/MAX1186 20Msps/40Msps), which digital data presented time-interleaved single, parallel 10-bit output port. lower speed, pin-compatible, 8-bit versions MAX1190, refer MAX1195-MAX1198 data sheets.
Features
Single 3.3V Operation Excellent Dynamic Performance 57dB SINAD 60MHz 64dBc SFDR 60MHz -71dBc Interchannel Crosstalk 60MHz Power 492mW (Normal Operation) 10mW (Sleep Mode) 3.3µW (Shutdown Mode) 0.08dB Gain 0.8° Phase Matching Wide ±1VP-P Differential Analog Input Voltage Range 400MHz -3dB Input Bandwidth On-Chip 2.048V Precision Bandgap Reference User-Selectable Output Format-Two's Complement Offset Binary Pin-Compatible, Lower-Speed, 10-Bit 8-Bit Versions Available
MAX1190
Ordering Information
PART MAX1190ECM TEMP RANGE -40°C +85°C PIN-PACKAGE TQFP-EP*
Exposed paddle. Functional Diagram appears data sheet.
Configuration
REFN REFP REFIN REFOUT
INA+ INAVDD INBINB+
OGND OVDD OVDD OGND
Applications
Baseband Sampling Multichannel Sampling Ultrasound Medical Imaging Battery-Powered Instrumentation WLAN, WWAN, WLL, MMDS Modems VSAT Terminals Set-Top Boxes
MAX1190
Maxim Integrated Products
SLEEP
TQFP-EP
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD .-0.3V +3.6V OGND GND.-0.3V +0.3V INA+, INA-, INB+, INB- .-0.3V REFIN, REFOUT, REFP, REFN, COM, GND.-0.3V (VDD 0.3V) SLEEP, T/B, D9A-D0A, D9B-D0B OGND .-0.3V (OVDD 0.3V) Continuous Power Dissipation +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).1000mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD 3.3V; OVDD 0.1µF 1.0µF capacitors from REFP, REFN, GND, REFOUT connected REFIN through resistor; VREFIN 2.048V; 2VP-P (differential with respect COM); 10pF digital outputs; fCLK 120MHz; TMIN TMAX, unless otherwise noted; +25°C guaranteed production test, <+25°C guaranteed design characterization; typical values +25°C.)
PARAMETER ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK 120MHz, 4096-point FFT) fINA 20.01MHz -0.5dB +25°C fINA 30.09MHz -0.5dB fINA 59.74MHz -0.5dB fINA 20.01MHz -0.5dB +25°C fINA 30.09MHz -0.5dB fINA 59.74MHz -0.5dB 54.5 58.5 58.2 57.5 fCLK Clock Cycles VDIFF Switched capacitor load Differential single-ended inputs ±1.0 7.47MHz 7.47MHz, missing codes guaranteed ±0.75 ±0.4 +1.5 ±1.8 Bits SYMBOL CONDITIONS UNITS
Signal-to-Noise Ratio
Signal-to-Noise Distortion
SINAD
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V; OVDD 0.1µF 1.0µF capacitors from REFP, REFN, GND, REFOUT connected REFIN through resistor; VREFIN 2.048V; 2VP-P (differential with respect COM); 10pF digital outputs; fCLK 120MHz; TMIN TMAX, unless otherwise noted; +25°C guaranteed production test, <+25°C guaranteed design characterization; typical values +25°C.)
PARAMETER SYMBOL CONDITIONS fINA 20.01MHz -0.5dB +25°C fINA 30.09MHz -0.5dB fINA 59.74MHz -0.5dB Third-Harmonic Distortion fINA 20.01MHz -0.5dB +25°C fINA 30.09MHz -0.5dB fINA 59.74MHz -0.5dB fIN1(A 43.393MHz -6.5dB fIN2(A 48.9017MHz -6.5dB (Note fIN1(A 43.393MHz -6.5dB fIN2(A 48.9017MHz -6.5dB (Note fINA 20.01MHz -0.5dB +25°C fINA 30.09MHz -0.5dB fINA 59.74MHz -0.5dB Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time INTERNAL REFERENCE Reference Output Voltage Load Regulation Reference Temperature Coefficient TCREF VREFOUT 2.048 1.25 mV/mA ppm/°C FPBW full-scale input Input -20dB differential inputs Input -0.5dB differential inputs UNITS
MAX1190
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion (First Five Odd-Order IMDs) Third-Order Intermodulation Distortion
Total Harmonic Distortion (First Four Harmonics)
psRMS
BUFFERED EXTERNAL REFERENCE (VREFIN 2.048V) Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range REFIN Resistance VREFP VREFN VCOM VREF RREFIN (Note (Note (Note VREF VREFP VREFN 0.95 2.162 1.138 1.651 1.024 1.09
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V; OVDD 0.1µF 1.0µF capacitors from REFP, REFN, GND, REFOUT connected REFIN through resistor; VREFIN 2.048V; 2VP-P (differential with respect COM); 10pF digital outputs; fCLK 120MHz; TMIN TMAX, unless otherwise noted; +25°C guaranteed production test, <+25°C guaranteed design characterization; typical values +25°C.)
PARAMETER Maximum REFP, Source Current Maximum REFP, Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN VREF VCOM VREFP VREFN Measured between REFP COM, REFN VREF VREFP VREFN CONDITIONS -250 UNITS
UNBUFFERED EXTERNAL REFERENCE (VREFIN AGND, reference voltage applied REFP, REFN, COM) REFP, REFN Input Resistance Differential Reference Input Voltage Range Input Voltage Range REFP Input Voltage REFN Input Voltage 1.024 VCOM VREF VCOM VREF OVDD OVDD (CLK) OVDD (PD, SLEEP, T/B) ISINK -200µA ISOURCE 200µA OVDD OVDD OVDD
DIGITAL INPUTS (CLK, SLEEP, T/B) Input High Threshold SLEEP, Input Threshold SLEEP, Input Hysteresis Input Leakage VHYST Input Capacitance DIGITAL OUTPUTS (D9A-D0A, D9B-D0B) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range OVDD ILEAK COUT
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V; OVDD 0.1µF 1.0µF capacitors from REFP, REFN, GND, REFOUT connected REFIN through resistor; VREFIN 2.048V; 2VP-P (differential with respect COM); 10pF digital outputs; fCLK 120MHz; TMIN TMAX, unless otherwise noted; +25°C guaranteed production test, <+25°C guaranteed design characterization; typical values +25°C.)
PARAMETER SYMBOL CONDITIONS Operating, fINA 20.01MHz -0.5dB Sleep mode Shutdown, clock idle, OVDD Operating, fINA 20.01MHz -0.5dB Typical Operating Characteristics section, Digital Supply Current Analog Input Frequency Sleep mode Shutdown, clock idle, OVDD Operating, fINA 20.01MHz -0.5dB Sleep mode Shutdown, clock idle, OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS Rise Output Data Valid Time Fall Output Enable Time Rise Output Disable Time Pulse Width High PSRR Offset, Gain, 20pF (Note UNITS
MAX1190
Analog Supply Current
IVDD
Output Supply Current
IOVDD
±3.4 ±0.81
mV/V
Analog Power Dissipation
PDISS
tENABLE tDISABLE
Pulse Width
Wake-Up Time
tWAKE
Clock period: 8.34ns; Typical Operating Characteristics section, Performance Clock Duty Cycle Clock period: 8.34ns; Typical Operating Characteristics section, Performance Clock Duty Cycle Wake from sleep mode (Note Wake from shutdown mode (Note fINA 20.01MHz -0.5dB fINA 20.01MHz -0.5dB (Note fINA 20.01MHz -0.5dB (Note
4.17
4.17 0.65 0.08 ±0.2
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching Degrees
Intermodulation distortion total power intermodulation products relative total input power. REFP, REFN, should bypassed with 0.1µF (min) (typ) capacitor. Digital outputs settle VIH, VIL. Parameter guaranteed design. With REFIN driven externally, REFP, COM, REFN left floating while powered down. Amplitude matching measured applying same signal each channel comparing magnitude fundamental calculated FFT. data from both channels must captured simultaneously during this test. Note Phase matching measured applying same signal each channel comparing phase fundamental calculated FFT. data from both channels must captured simultaneously during this test. Note Note Note Note Note
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
Typical Operating Characteristics
(VDD 3.3V, OVDD 2.5V, VREFIN 2.048V, differential input -0.5dB fCLK 120MHz, 10pF, +25°C, unless otherwise noted.)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1190 toc01a
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1190 toc01b
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
fINA 31.0873MHz fINB 23.9967MHz fCLK 120.0128MHz AINA/AINB -0.52dB
MAX1190 toc02a
AMPLITUDE (dB) fINA
fINA 20.0119MHz fINB 12.9799MHz fCLK 120.0128MHz AINA/AINB -0.52dB
AMPLITUDE (dB) fINB fINA 12.9799MHz fINB 20.0119MHz fCLK 120.0128MHz AINA/AINB -0.52dB
AMPLITUDE (dB)
fINA
-100
-100
-100
-125 ANALOG INPUT FREQUENCY (MHz)
-125 ANALOG INPUT FREQUENCY (MHz)
-125 ANALOG INPUT FREQUENCY (MHz)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1190 toc02b
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1190 toc03a
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
fINA 49.0189MHz fINB 59.7427MHz fCLK 120.0128MHz AINA/AINB -0.52dB fINB
MAX1190 toc03b
fINA 23.9967MHz fINB 31.0873MHz fCLK 120.0128MHz AINA/AINB -0.52dB
fINA 59.7427MHz fINB 49.0189MHz fCLK 120.0128MHz AINA/AINB -0.52dB fINA
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
fINB
-100
-100
-100
-125 ANALOG INPUT FREQUENCY (MHz)
-125 ANALOG INPUT FREQUENCY (MHz)
-125 ANALOG INPUT FREQUENCY (MHz)
TWO-TONE PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1190 toc04
SIGNAL-TO-NOISE RATIO ANALOG INPUT FREQUENCY
MAX1190 toc05
SIGNAL-TO-NOISE DISTORTION ANALOG INPUT FREQUENCY
MAX1190 toc06
AMPLITUDE (dB)
fIN1 43.3933MHz fIN2 48.9017MHz fCLK 120.0128MHz -6.5dB fIN1 fIN2
(dB)
SINAD (dB)
-100
-125 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
Typical Operating Characteristics (continued)
(VDD 3.3V, OVDD 2.5V, VREFIN 2.048V, differential input -0.5dB fCLK 120MHz, 10pF, +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION ANALOG INPUT FREQUENCY
MAX1190 toc07
MAX1190
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT FREQUENCY
MAX1190 toc08
SNR/SINAD, THD/SFDR CLOCK DUTY CYCLE
SFDR SNR/SINAD, THD/SFDR (dB, dBc)
MAX1190 toc09
SFDR (dBc)
(dBc)
SINAD fINA/B 20.02536MHz
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
CLOCK DUTY CYCLE
FULL-POWER INPUT BANDWIDTH ANALOG INPUT FREQUENCY
MAX1190 toc10
SMALL-SIGNAL INPUT BANDWIDTH ANALOG INPUT FREQUENCY
MAX1190 toc11
SIGNAL-TO-NOISE RATIO INPUT POWER (fIN 20.02536MHz)
MAX1190 toc12
GAIN (dB)
GAIN (dB)
(dB) 100mVP-P 1000
1000 ANALOG INPUT FREQUENCY (MHz)
INPUT POWER
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE DISTORTION INPUT POWER (fIN 20.02536MHz)
MAX1190 toc13
TOTAL HARMONIC DISTORTION INPUT POWER (fIN 20.02536MHz)
MAX1190 toc14
SPURIOUS-FREE DYNAMIC RANGE INPUT POWER (fIN 20.02536MHz)
MAX1190 toc15
(dBc)
SFDR (dBc)
SINAD (dB)
INPUT POWER
INPUT POWER
INPUT POWER
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
Typical Operating Characteristics (continued)
(VDD 3.3V, OVDD 2.5V, VREFIN 2.048V, differential input -0.5dB fCLK 120MHz, 10pF, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1190 toc16
DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1190 toc17
GAIN ERROR TEMPERATURE, EXTERNAL REFERENCE
MAX1190 toc18
GAIN ERROR (%FS) (LSB) (LSB)
-0.2
-0.1
-0.1 -0.6 1023 DIGITAL OUTPUT CODE -0.3 1023 DIGITAL OUTPUT CODE -0.3 TEMPERATURE (°C)
OFFSET ERROR TEMPERATURE, EXTERNAL REFERENCE
MAX1190 toc19
ANALOG SUPPLY CURRENT TEMPERATURE
MAX1190 toc20
DIGITAL SUPPLY CURRENT ANALOG INPUT FREQUENCY
MAX1190 toc21
IOVDD (mA)
OFFSET ERROR (%FS)
-0.2
IVDD (mA)
-0.7
-1.2 TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (MHz)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE TEMPERATURE
MAx1190 toc22
INTERNAL REFERENCE VOLTAGE ANALOG SUPPLY VOLTAGE
MAX1190 toc23
2.038 2.034 2.030 VREFOUT 2.026 2.022 2.018 2.014 2.010
2.035
2.030 VREFOUT
2.025
2.020
2.015 2.70 2.85 3.00 3.15 3.30 3.45 3.60 TEMPERATURE (°C)
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
Description
NAME INA+ INAINBINB+ FUNCTION Common-Mode Voltage I/O. Bypass with 0.1µF capacitor. Analog Supply Voltage. Bypass with capacitor combination 2.2µF parallel with 0.1µF. Analog Ground Channel Positive Analog Input. single-ended operation, connect signal source INA+. Channel Negative Analog Input. single-ended operation, connect INA- COM. Channel Negative Analog Input. single-ended operation, connect INB- COM. Channel Positive Analog Input. single-ended operation, connect signal source INB+. Converter Clock Input selects Digital Output Format: High: Two's complement Low: Straight offset binary Sleep-Mode Input: High: Disables both quantizers, leaves reference bias circuit active Low: Normal operation High-Active Power-Down Input: High: Power-down mode Low: Normal operation Low-Active Output Enable Input: High: Digital outputs disabled Low: Digital outputs enabled Three-State Digital Output, (MSB), Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Output Driver Ground Output Driver Supply Voltage. Bypass OGND with capacitor combination 2.2µF parallel with 0.1µF. Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel
MAX1190
SLEEP
OGND OVDD
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
Description (continued)
NAME REFOUT REFIN REFP REFN Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, (MSB), Channel Internal Reference Voltage Output. connected REFIN through resistor resistor-divider. Reference Input. VREFIN (VREFP VREFN). Bypass with >0.1µF capacitor. Positive Reference I/O. Conversion range ±(VREFP VREFN). Bypass with >0.1µF capacitor. Negative Reference I/O. Conversion range ±(VREFP VREFN). Bypass with >0.1µF capacitor. FUNCTION
Detailed Description
MAX1190 uses nine-stage, fully differential, pipelined architecture (Figure that allows highspeed conversion while minimizing power consumption. Samples taken inputs move progressively through pipeline stages every half-clock cycle. Including delay through output latch, total clock-cycle latency five clock cycles. Flash ADCs convert held input voltages into digital code. Internal MDACs convert digitized results back into analog voltages, which then subtracted from original held input signals. resulting error signals then multiplied residues passed along next pipeline stages, where process repeated until signals have been processed nine stages.
Input Track-and-Hold Circuits
Figure displays simplified functional diagram input circuits both track hold mode. track mode, switches S2a, S2b, S4a, S4b, S5a, closed. fully differential circuits sample input signals onto capacitors (C2a C2b) through switches S4b. common mode amplifier input, open simultaneously with sampling input waveform. Switches S4a, S4b, S5a, then opened before switches connect capacitors output amplifier switch closed. resulting differential voltages held capacitors C2b. amplifiers used charge capacitors same values originally held C2b.
2-BIT FLASH STAGE STAGE STAGE STAGE STAGE STAGE STAGE
2-BIT FLASH STAGE
DIGITAL ALIGNMENT LOGIC D9A-D0A
DIGITAL ALIGNMENT LOGIC D9B-D0B
VINA
VINB
VINA INPUT VOLTAGE BETWEEN INA+ INA- (DIFFERENTIAL SINGLE ENDED) VINB INPUT VOLTAGE BETWEEN INB+ INB- (DIFFERENTIAL SINGLE ENDED)
Figure Pipelined Architecture-Stage Blocks
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
INTERNAL BIAS INA+ INTERNAL BIAS HOLD INTERNAL BIAS INB+ INTERNAL BIAS MAX1190 TRACK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS
INA-
INB-
Figure MAX1190 Amplifiers
These values then presented first-stage quantizers isolate pipelines from fast-changing inputs. wide input bandwidth amplifiers allow MAX1190 track sample/hold analog inputs high frequencies (>Nyquist). Both inputs (INA+, INB+,
INA- INB-) driven either differentially single ended. Match impedance INA+ INA-, well INB+ INB-, common-mode voltage midsupply (VDD/2) optimum performance.
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
Analog Inputs Reference Configurations
full-scale range MAX1190 determined internally generated voltage difference between REFP (VDD/2 VREFIN/4) REFN (VDD/2 VREFIN/4). fullscale range both on-chip ADCs adjustable through REFIN pin, which provided this purpose. MAX1190 provides three modes reference operation: Internal reference mode Buffered external reference mode Unbuffered external reference mode internal reference mode, connect internal reference output REFOUT REFIN through resistor (e.g., 10k) resistor-divider, application requires reduced full-scale range. stability noise filtering purposes, bypass REFIN with >10nF capacitor GND. internal reference mode, REFOUT, COM, REFP, REFN become low-impedance outputs. buffered external reference mode, adjust reference voltage levels externally applying stable accurate voltage REFIN. this mode, COM, REFP, REFN outputs. REFOUT left open connected REFIN through >10k resistor. unbuffered external reference mode, connect REFIN GND. This deactivates on-chip reference buffers REFP, COM, REFN. With their buffers shut down, these nodes become high-impedance inputs driven through separate, external reference sources. detailed circuit suggestions drive this dual buffered/unbuffered external reference mode, Applications Information section.
Clock Input (CLK)
MAX1190's input accepts CMOS-compatible clock signal. Since interstage conversion device depends repeatability rising falling edges external clock, clock with jitter fast rise fall times (<2ns). particular, sampling occurs rising edge clock signal, requiring this edge provide lowest possible jitter. significant aperture jitter would limit performance on-chip ADCs follows: where represents analog input frequency time aperture jitter. Clock jitter especially critical undersampling applications. clock input should always considered analog input routed away from analog input other digital signal lines. MAX1190 clock input operates with voltage threshold VDD/2. Clock inputs with duty cycle other than 50%, must meet specifications high periods stated Electrical Characteristics.
5-CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT DATA OUTPUT D9A-D0A
DATA OUTPUT D9B-D0B
Figure System Timing Diagram
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
System Timing Requirements
Figure depicts relationship between clock input, analog input, data output. MAX1190 samples rising edge input clock. Output data channels valid next rising edge input clock. output data internal latency five clock cycles. Figure also determines relationship between input clock parameters valid output data channels
MAX1190
tENABLE OUTPUT D9A-D0A HIGH-Z
tDISABLE HIGH-Z
VALID DATA
Digital Output Data (D0A/B-D9A/B), Output Data Format Selection (T/B), Output Enable (OE)
digital outputs, D0A-D9A (channel D0B-D9B (channel TTL/CMOS-logic compatible. There five-clock-cycle latency between particular sample corresponding output data. output coding chosen either straight offset binary two's complement (Table controlled single (T/B). Pull select offset binary high activate two's complement output coding. capacitive load digital outputs D0A-D9A D0B-D9B should kept possible (<15pF) avoid large digital currents that could feed back into analog portion MAX1190, thereby degrading dynamic performance. Using buffers digital outputs ADCs further isolate digital outputs from heavy capacitive loads. further improve dynamic performance MAX1190, small series resistors (e.g., 100) added digital output paths, close MAX1190. Figure displays timing relationship between output enable data output valid, well powerdown/wakeup data output valid.
OUTPUT D9B-D0B
HIGH-Z
VALID DATA
HIGH-Z
Figure Output Timing Diagram
(both ADCs disabled), current consumption reduced 3mA. enter full power-down mode, pull high. With simultaneously low, outputs latched last value prior power down. Pulling high forces digital outputs into high-impedance state.
Applications Information
Figure depicts typical application circuit containing single-ended differential converters. internal reference provides VDD/2 output voltage levelshifting purposes. input buffered then split voltage follower inverter. lowpass filter amplifier suppresses some wideband noise associated with high-speed operational amplifiers. user select RISO values optimize filter performance suit particular application. application Figure RISO placed before capacitive load prevent ringing oscillation. 22pF capacitor acts small filter capacitor.
Power-Down (PD) Sleep (SLEEP) Modes
MAX1190 offers power-save modes-sleep mode full power-down mode. sleep mode (SLEEP only reference bias circuit active
Table MAX1190 Output Codes Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF 512/512 VREF 1/512 -VREF 1/512 -VREF 511/512 -VREF 512/512 DIFFERENTIAL INPUT +FULL SCALE 1LSB +1LSB Bipolar Zero -1LSB -FULL SCALE 1LSB -FULL SCALE STRAIGHT OFFSET BINARY 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000 TWO'S COMPLEMENT 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000
*VREF VREFP VREFN
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
0.1µF LOWPASS FILTER MAX4108 0.1µF INARIS0 22pF
0.1µF
0.1µF 0.1µF INPUT 0.1µF MAX4108 0.1µF MAX4108 INA+ RIS0 0.1µF 22pF LOWPASS FILTER
MAX1190
0.1µF LOWPASS FILTER MAX4108 0.1µF INBRIS0 22pF
0.1µF
0.1µF INPUT MAX4108 0.1µF 0.1µF
0.1µF MAX4108 RIS0 0.1µF 22pF LOWPASS FILTER INB+
Figure Typical Application Single-Ended Differential Conversion
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
INA+ 22pF 0.1µF N.C. 2.2µF 0.1µF
MINICIRCUITS TT1-6-KK81 INA22pF MAX1190 INB+ 22pF 0.1µF N.C. 2.2µF 0.1µF
MINICIRCUITS TT1-6-KK81 INB22pF
Figure Transformer-Coupled Input Drive
Using Transformer Coupling
transformer (Figure provides excellent solution convert single-ended source signal fully differential signal, required MAX1190 optimum performance. Connecting center transformer provides VDD/2 level shift input. Although transformer shown, step-up transformer selected reduce drive requirements. reduced signal swing from input driver, such amp, also improve overall distortion. general, MAX1190 provides better SFDR with fully differential input signals than singleended drive, especially very high input frequencies. differential input mode, even-order harmonics lower both inputs (INA+, INA- and/or INB+, INB-) balanced, each inputs only requires half signal swing compared single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure shows AC-coupled, single-ended application. Amplifiers like MAX4108 provide high speed, high bandwidth, noise, distortion maintain integrity input signal.
Buffered External Reference Drives Multiple ADCs
Multiple-converter systems based MAX1190 well suited with common reference voltage. REFIN those converters connected directly external reference source. precision bandgap reference like MAX6062 generates external level 2.048V (Figure exhibits noise voltage density 150nV/Hz. output passes through 1-pole lowpass filter (with 10Hz cutoff frequency) MAX4250, which buffers reference before output applied second 10Hz lowpass filter. MAX4250 provides offset voltage (for
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
REFP
MAX4108
0.1µF
RISO INA+ 22pF REFN 0.1µF RISO INACIN 22pF REFP
MAX1190
MAX4108
0.1µF
RISO INB+ 22pF
REFN
0.1µF
RISO INBCIN 22pF
Figure Using Single-Ended, AC-Coupled Input Drive
high-gain accuracy) noise level. passive 10Hz filter following buffer attenuates noise produced voltage reference buffer stages. This filtered noise density, which decreases higher frequencies, meets noise levels specified precision-ADC operation.
Unbuffered External Reference Drives Multiple ADCs
Connecting each REFIN analog ground disables internal reference each device, allowing internal reference ladders driven directly external reference sources. Followed 10Hz lowpass filter precision voltage-divider, MAX6066 generates level 2.500V. buffered outputs this divider 2.0V, 1.5V, 1.0V, with accuracy that depends tolerance divider resistors (Figure
Those three voltages buffered MAX4252, which provides noise offset. individual voltage followers connected 10Hz lowpass filters, which filter both reference voltage amplifier noise level 3nV/Hz. 2.0V 1.0V reference voltages differential full-scale range associated ADCs 2VP-P. 2.0V 1.0V buffers drive ADCs' internal ladder resistances between them. Note that common power supply active components removes concern regarding powersupply sequencing when powering down. With outputs MAX4252 matching better than 0.1%, buffers subsequent lowpass filters replicated support many ADCs. applications that require more than matched ADCs, voltage reference divider string common converters highly recommended.
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
3.3V 0.1µF 0.1µF 0.1µF MAX6062 16.2k MAX4250 10Hz LOWPASS FILTER 100µF 0.1µF 0.1µF 0.1µF 10Hz LOWPASS FILTER 3.3V 2.048V N.C. REFOUT REFIN REFP REFN
MAX1190
NOTE: FRONT-END REFERENCE CIRCUIT DESIGN USED WITH 1000 ADCs.
0.1µF
2.2µF
N.C.
REFOUT REFIN REFP REFN
0.1µF
1000 MAX1190
0.1µF 0.1µF 0.1µF
Figure External Buffered (MAX4250) Reference Drive Using MAX6062 Bandgap Reference
Typical Demodulation Application
frequently used modulation technique digital communications applications quadrature amplitude modulation (QAM). Typically found spread-spectrum-based systems, signal represents carrier frequency modulated both amplitude phase. transmitter, modulating baseband signal with quadrature outputs, local oscillator followed subsequent upconversion generate signal. result in-phase quadrature carrier component, where component phase shifted with respect in-phase component. receiver, signal divided down into components, essentially representing modulation process reversed. Figure displays demodulation process performed analog domain, using dualmatched 3.3V, 10-bit MAX1190 MAX2451 quadrature demodulator recover digitize baseband signals. Before being digitized
MAX1190, mixed-down signal components filtered matched analog filters, such Nyquist pulse-shaping filters, which remove unwanted images from mixing process, thereby enhancing overall performance minimizing intersymbol interference.
Grounding, Bypassing, Board Layout
MAX1190 requires high-speed board layout design techniques. Locate bypass capacitors close device possible, preferably same side ADC, using surface-mount devices minimum inductance. Bypass VDD, REFP, REFN, with parallel 0.1µF ceramic capacitors 2.2µF bipolar capacitor GND. Follow same rules bypass digital supply (OVDD) OGND. Multilayer boards with separated ground power planes produce
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
3.3V 0.1µF 2.0V MAX6066 21.5k MAX4252 21.5k 1.5V MAX4252 21.5k 3.3V 0.1µF 10µF 1.47k 3.3V MAX4252 21.5k MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR CLOSE POSSIBLE AMP. 21.5k 10µF 1.47k 330µF N.C. REFOUT REFIN REFP REFN 1.0V -8mA 330µF 0.1µF 2.2µF 10µF 1.47k 3.3V 1.5V 330µF 0.1µF 0.1µF 0.1µF 3.3V 2.0V N.C.
REFOUT REFIN
REFP REFN
MAX1190
1.0V
MAX1190
NOTE: FRONT-END REFERENCE CIRCUIT DESIGN USED WITH ADCs.
0.1µF 0.1µF 0.1µF
Figure External Unbuffered Reference Drive with MAX4252 MAX6066
MAX2451
INA+ INA0°
MAX1190 INB+ INB-
POSTPROCESSING
DOWNCONVERTER
Figure Typical Application Using MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
highest level signal integrity. Consider split ground plane arranged match physical location analog ground (GND) digital output driver ground (OGND) ADC's package. ground planes should joined single point such that noisy digital ground currents interfere with analog ground plane. ideal location this connection determined experimentally point along between ground planes, which produces optimum results. Make this connection with low-value, surface-mount resistor ferrite bead, direct short. Alternatively, ground pins could share same ground plane ground plane sufficiently isolated from noisy, digital systems ground plane (e.g., downstream output buffer ground plane). Route high-speed digital signal traces away from sensitive analog traces either channel. Make sure isolate analog input lines each respective converter minimize channel-to-channel crosstalk. Keep signal lines short free turns.
Dynamic Parameter Definitions
Aperture Jitter
Figure depicts aperture jitter (tAJ), which sample-to-sample variation aperture delay.
MAX1190
Aperture Delay
Aperture delay (tAD) time defined between falling edge sampling clock instant when actual sample taken (Figure 11).
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution bits): SNRdB[max] 6.02dB 1.76dB reality, there other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity deviation values actual transfer function from straight line. This straight line either best-straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1190 measured using best-straight-line method.
Signal-to-Noise Plus Distortion (SINAD)
SINAD computed taking ratio signal spectral components minus fundamental offset.
Differential Nonlinearity (DNL)
Differential nonlinearity difference between actual step width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
Effective Number Bits (ENOB)
ENOB specifies dynamic performance specific input frequency sampling rate. ideal ADC's error consists quantization noise only. ENOB full-scale sinusoidal input waveform computed from: SINAD 1.76 ENOB 6.02
ANALOG INPUT SAMPLED DATA (T/H)
TRACK
HOLD
TRACK
Figure Aperture Timing
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs MAX1190
Total Harmonic Distortion (THD)
typically ratio first four harmonics input signal fundamental itself. This expressed where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Intermodulation Distortion (IMD)
two-tone ratio expressed decibels either input tone worst 3rd-order higher) intermodulation products. individual input tone levels -6.5dB full scale their envelope -0.5dB full scale.
Chip Information
TRANSISTOR COUNT: 10,811 PROCESS: CMOS
Spurious-Free Dynamic Range (SFDR)
SFDR ratio expressed decibels amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Functional Diagram
INA+ INAADC OUTPUT DRIVERS
OGND OVDD
D9A-D0A
CONTROL
INB+ INBADC
OUTPUT DRIVERS
D9B-D0B
REFERENCE
MAX1190
REFOUT REFN REFP REFIN
SLEEP
Dual 10-Bit, 120Msps, 3.3V, Low-Power with Internal Reference Parallel Outputs
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
48L,TQFP.EPS
MAX1190
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
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