Kbit (32K 5.0V Asynchronous SRAM FEATURES SUMMARY SUPPLY VOLTAGE:
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M68AF031AL M68AF031AM
Kbit (32K 5.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 5.5V bits SRAM with OUTPUT ENABLE EQUAL CYCLE ACCESS TIME: 70ns STANDBY CURRENT DATA RETENTION: TRI-STATE COMMON AUTOMATIC POWER DOWN
SO28 (MS)
Figure Packages
PDIP28
TSOP28 13.4mm
TSOP28 (NS) 13.4 (Reverse)
October 2002
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M68AF031AL, M68AF031AM
TABLE CONTENTS SUMMARY DESCRIPTION Figure Logic Diagram Table Signal Names Figure Connections Figure Connections Figure TSOP Connections (Normal) Figure TSOP Connections (Reverse) Figure Block Diagram MAXIMUM RATING. Table Absolute Maximum Ratings. PARAMETERS. Table Operating Measurement Conditions. Figure Measurement Waveform Figure Measurement Load Circuit Table Capacitance. Table Characteristics. OPERATION Table Operating Modes. Read Mode Figure Address Controlled, Read Mode Waveforms Figure Chip Enable Output Enable Controlled, Read Mode Waveforms. Figure Chip Enable Controlled, Standby Mode Waveforms Table Read Standby Mode Characteristics Write Mode Figure Write Enable Controlled, Write Waveforms Figure Chip Enable Controlled, Write Waveforms. Table Write Mode Characteristics Figure Data Retention Waveforms Table Data Retention Characteristics. PACKAGE MECHANICAL SO28 lead Plastic Small Outline, mils body width, Package Outline SO28 lead Plastic Small Outline, mils body width, Package Mechanical Data PDIP28 Plastic DIP, mils width, Package Outline PDIP28 Plastic DIP, n600 mils width, Package Mechanical Data TSOP28 lead Normal Reverse Pinout Plastic Small Outline, Package Outline TSOP28 lead Normal Reverse Pinout Plastic Small Outline, Package Mechanical Data. PART NUMBERING Table Ordering Information Scheme REVISION HISTORY. Table Document Revision History
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SUMMARY DESCRIPTION M68AF031AL/M Kbit (262,144 bit) CMOS SRAM, organized 32,768 bytes. device features fully static operation requiring external clocks timing strobes, with equal address access cycle times. requires single 5.5V supply. This device automatic power-
down feature, reducing power consumption over when deselected. M68AF031AL/M available SO28 (28-lead Small Outline), PDIP28 (28-pin Plastic Dual-InLine) TSOP28 (28-lead Thin Small Outline, Standard Reverse Pinout) packages.
Figure Logic Diagram
Table Signal Names
A0-A14 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground Connected Internally
DQ0-DQ7
A0-A14
M68AF031AL/M
DQ0-DQ7
AI05920b
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Figure Connections Figure TSOP Connections (Normal)
M68AF031AL/M
AI05921b
M68AF031AL/M (Normal)
AI07200b
Figure Connections
Figure TSOP Connections (Reverse)
M68AF031AL/M
M68AF031AL/M (Reverse)
AI07201b
AI05922b
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Figure Block Diagram
DECODER MEMORY ARRAY
CIRCUITS COLUMN DECODER
AI05919
MAXIMUM RATING Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum Ratings
Symbol TSTG Output Current Power Dissipation Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage Parameter
plied. Exposure Absolute Maximum Rating conditions periods greater than periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Value -0.5 -0.5 +0.5
Unit
Note: output time, exceed second duration. maximum operating 6.0V only.
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PARAMETERS This section summarizes operating measurement conditions, well characteristics device. parameters following Characteristic tables derived from tests performed under Measure-
ment Conditions listed relevant tables. Designers should check that operating conditions their projects match measurement conditions when using quoted parameters.
Table Operating Measurement Conditions
Parameter Supply Voltage Range Ambient Operating Temperature Range Load Capacitance (CL) Output Circuit Protection Resistance Load Resistance (R2) Input Output Timing Ref. Voltages Input Rise Fall Times Input Pulse Voltages Output Transition Timing Ref. Voltages 85°C 100pF 3.0k 3.1k CC/2 1ns/V 0.3VCC; 0.7V M68AF031AL/M 5.5V 70°C
Figure Measurement Waveform
Figure Measurement Load Circuit
Timing Reference Voltage VCC/2 DEVICE UNDER TEST Output Timing Reference Voltage 0.7VCC 0.3VCC
AI05831
includes probe capacitance
AI05932
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Table Capacitance
Symbol Parameter (1,2) Input Capacitance pins (except Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested. 25°C, MHz, 5.0V.
Table Characteristics
Symbol Parameter Test Condition 5.5V, AVAV, IOUT 5.5V, 1MHz, IOUT 5.5V, -0.2V VOUT Range Range -0.3 -1.0mA 2.1mA Unit
ICC1 (1,2) Operating Supply Current ICC2
Note:
Operating Supply Current
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Voltage Output High Voltage Output Voltage
Average current, cycling tAVAV minimum. VIL, VIH. 0.2V, 0.2V -0.2V. Output disabled.
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OPERATION M68AF031AL/M Chip Enable power down feature which invokes automatic standby mode whenever Chip Enable de-asserted High). Output Enable signal provides high speed tri-state control, allowing fast read/ Table Operating Modes
Operation Deselected Read Write Output Disabled
Note: VIL.
write cycles achieved with common data bus. Operational modes determined device control inputs summarized Operating Modes table (see Table
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Read Mode M68AF031AL/M Read mode whenever Write Enable High with Output Enable Low, Chip Enable asserted. This provides access data 262,144 locations static memory array, specified address inputs. Valid data will available eight output pins within tAVQV after last stable
address, providing Low. Chip Enable Output Enable access times met, data access will measured from limiting parameter (tELQV tGLQV) rather than address. Data indeterminate tELQX tGLQX data lines will always valid tAVQV.
Figure Address Controlled, Read Mode Waveforms
tAVAV A0-A14 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05939
Note: Low, Low, High.
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Figure Chip Enable Output Enable Controlled, Read Mode Waveforms.
tAVAV A0-A14 tAVQV tELQV tELQX tGLQV tGLQX DQ0-DQ7 VALID
AI05940
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable High.
Figure Chip Enable Controlled, Standby Mode Waveforms
AI05956
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Table Read Standby Mode Characteristics
M68AF031AL/M Symbol tAVAV tAVQV tAXQX tEHQZ (2,3) tELQV tELQX tGHQZ (2,3) tGLQV tGLQX Read Cycle Time Address Valid Output Valid Data hold from address change Chip Enable High Output Hi-Z Chip Enable Output Valid Chip Enable Output Transition Output Enable High Output Hi-Z Output Enable Output Valid Output Enable Output Transition Chip Enable High Power Down Chip Enable Power Parameter Unit
Note: Test conditions assume transition timing reference level 0.3V 0.7VCC. given temperature voltage condition, tGHQZ less than tGLQX tEHQZ less than tELQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. Tested initially after design process changes that affect these parameters.
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Write Mode M68AF031AL/M Write mode whenever Low. Either Chip Enable input Write Enable input must de-asserted during Address transitions subsequent write cycles. When Low, write cycle begins (E)'s falling edge. Therefore, address setup time referenced Write Enable Chip Enable tAVWL AVEL respectively, determined latter occurring edge.
Write cycle terminated earlier rising edge Output enabled Low, Low), then will return outputs high impedance within tWLQZ falling edge. Care must taken avoid contention this type operation. Data input must valid DVWH before rising edge Write Enable, tDVEH before rising edge whichever occurs first, remain valid tWHDX tEHDX respectively.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVWH tELWH tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA
tWHAX
tWHQX
DATA INPUT tDVWH
DATA
AI05941
Note: During this period DQ0-DQ7 output state input signals should applied.
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Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL tWLEH tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05942
tELEH
tEHAX
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Table Write Mode Characteristics
M68AF031AL/M Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid Chip Enable High Address valid Chip Enable Address Valid Write Enable High Address Valid Write Enable Input Valid Chip Enable High Input Valid Write Enable High Chip Enable High Address Transition Chip enable High Input Transition Chip Enable Chip Enable High Chip Enable Write Enable High Write Enable High Address Transition Write Enable High Input Transition Write Enable High Output Transition Write Enable Chip Enable High Write Enable Output Hi-Z Write Enable Write Enable High Parameter Unit
Note: given temperature voltage condition, tWLQZ less than tWHQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels.
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Figure Data Retention Waveforms
DATA RETENTION MODE 5.5V 4.5V
2.0V tCDR 0.2V
AI05925
Table Data Retention Characteristics
Symbol ICCDR tCDR (1,2) Parameter Supply Current (Data Retention) Chip Deselected Data Retention Time Operation Recovery Time Supply Voltage (Data Retention) -0.2V, Test Conditio 2.0V, -0.2V, tAVAV Unit
Note: other Inputs -0.2V 0.2V. Tested initially after design process changes that affect these parameters. AVAV Read cycle time. input exceed +0.2V.
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PACKAGE MECHANICAL Figure SO28 lead Plastic Small Outline, mils body width, Package Outline
SO-E
Note: Drawing scale.
Table SO28 lead Plastic Small Outline, mils body width, Package Mechanical Data
millimeters Symbol 1.27 7.39 11.68 0.79 2.38 0.05 2.28 0.35 0.20 18.03 2.79 0.35 2.43 0.50 0.30 18.41 0.10 7.62 12.19 1.27 0.050 0.291 0.460 0.031 0.094 0.002 0.090 0.014 0.008 0.710 0.110 0.014 0.096 0.020 0.012 0.725 0.004 0.300 0.480 0.050 inches
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Figure PDIP28 Plastic DIP, mils width, Package Outline
PDIP
Note: Drawing scale.
Table PDIP28 Plastic DIP, n600 mils width, Package Mechanical Data
millimeters Symbol 2.54 14.99 33.02 15.24 1.52 0.38 3.56 0.38 0.20 36.83 13.59 15.24 3.18 1.78 5.08 4.06 0.51 0.30 37.34 13.84 17.78 3.43 2.08 0.100 0.590 1.300 0.600 0.060 0.015 0.140 0.015 0.008 1.450 0.535 0.600 0.125 0.070 0.200 0.160 0.020 0.012 1.470 0.545 0.700 0.135 0.082 inches
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Figure TSOP28 lead Normal Reverse Pinout Plastic Small Outline, Package Outline
TSOP-c
Note: Drawing scale.
Table12. TSOP28- leadNormal andReverse PinoutPlastic Small Outline,PackageMechanicalData
millimeters Symbol 0.550 13.200 11.700 7.900 0.500 0.950 0.170 0.100 1.250 0.200 1.150 0.270 0.210 0.100 13.600 11.900 8.100 0.700 0.0217 0.5197 0.4606 0.3110 0.0197 0.0374 0.0067 0.0039 0.0492 0.0079 0.0453 0.0106 0.0083 0.0039 0.5354 0.4685 0.3189 0.0276 inches
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PART NUMBERING Table Ordering Information Scheme
Example: Device Type Mode Asynchronous Operating Voltage 5.5V Array Organization Kbit (32K Optio Chip Enable Optio L-Die M-Die Speed Class Package SO28 PDIP28 TSOP28 8x13.4mm TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 70°C Shipping Tape Reel Packing M68AF031
list available options (Speed, Package, etc.) further information aspect this device, please contact STMicroelectronics Sales Office nearest you.
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REVISION HISTORY Table Document Revision History
Date January 2002 07-Feb-2002 08-Feb-2002 06-Mar-2002 19-Apr-2002 Version First Issue clarified TSOP28 Package removed Measurement Load Circuit changed (Figure Operating Measurement Conditions clarified (Table Document status changed Data Sheet Absolute Maximum current value added (Table Operating Measurement Conditions clarified (Table Absolute Maximum Ratings Table clarified (Table Operating Measurement Conditions Table clarified (Table Characteristics Table clarified (Table Write Mode Characteristics Table clarified (Table Data Retention Waveforms clarified (Figure Data Retention Characteristics Table clarified (Table Characteristics Table clarified (Table Data Retention Characteristics Table clarified (Table TSOP28 8x13.4mm Standard Reverse pinout added (Figure Table Revision numbering modified: minor revision will indicated incrementing digit after dot, major revision, incrementing digit before (revision version equals 8.0). part number added. Revision Details
26-Apr-2002
20-May-2002 29-May-2002
02-Oct-2002
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners. 2002 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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