3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

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3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

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IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Drive Features ALVCHR16260: Balanced Output Drivers: ±12mA switching noise
IDT74ALVCHR16260
applications which separate data paths must multiplexed onto, demultiplexed from, single data path. Typical applications include multiplexing and/or demultiplexing address data information microprocessor bus-interface applications. This device also useful memory interleaving applications. Three 12-bit ports (A1-A12, 1B1-1B12, 2B1-2B12) available address and/or data transfer. output-enable (OE1B, OE2B, OEA) inputs control transceiver functions. OE1B OE2B control signals also allow bank control Ato-B direction. Address and/or data information stored using internal storage latches. latch-enable (LE1B, LE2B, LEA1B, LEA2B) inputs used control data storage. When latchenable input high, latch transparent. When latch-enable input goes low, data present inputs latched remains latched until latch-enable input returned high. ALVCHR16260 series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. ALVCHR16260 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
DESCRIPTION:
This 12-bit 24-bit multiplexed D-type latch built using advanced dual metal technology. ALVCHR16260 used
Functional Block Diagram
LEA1B
A-1B LATC
1:12
LE1B
1B-A LATC
1:12
LE2B
2B-A LATC
LEA2B
A-2B LATC
1:12
1999 Integrated Device Technology, Inc.
JULY 1999
DSC-5167/1
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
CONFIGURATION
LE1B
ABSOLUTE MAXIMUM RATING
OE2B LEA2B
Unit
NEW16link
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. ±100
SO56-1 SO56-2 SO56-3
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
NOTE: applicable device type.
LE2B
LEA1B OE1B
SSOP/ TSSOP/TVSOP VIEW
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
DESCRIPTION
Names Ax(1:12)
1Bx(1:12) 2Bx(1:12)
Description Bidirectional Data Port Usually connected CPU's Address/Data bus. Bidirectional Data Port Connected even path even bank memory. Bidirectional Data Port Connected path bank memory. Latch Enable Input A-1B latch. latch open when LEA1B HIGH. Data from port latched HIGH transition LEA1B. Latch Enable Input A-2B latch. latch open when LEA2B HIGH. Data from port latched HIGH transition LEA2B. Latch Enable Input 1B-A latch. latch open when LE1B HIGH. Data from port latched HIGH transition LE1B. Latch Enable Input 2B-A latch. latch open when LE2B HIGH. Data from port latched HIGH transition LE2B. Path Selection. When HIGH, enables data transfer from port port. When LOW, enables data transfer from port port. Output Enable port (Active LOW) Output Enable port (Active LOW) Output Enable port (Active LOW)
LEA1B LEA2B LE1B LE2B OE1B OE2B
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
FUNCTION TABLES (OEB
Inputs
(OEB
Outputs LE2B A0(2) A0(2)
Inputs LEA1B LEA2B OE1B OE2B
Outputs
LE1B
2B0(2) 2B0(2)
2B0(2)
1B0(2)
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance Output level before indicated steady-state input conditions were established.
Active Active
Active Active
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
NEW16link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Propagation Delay LEXB Propagation Delay LEA1B LEA2B Propagation Delay Output Enable Time OE1B 1BX, OE2B Output Disable Time OE1B 1BX, OE2B Setup Time, data before LE1B, LE2B, LEA1B, LEA2B Hold Time, data after LE1B, LE2B, LEA1B, LEA2B Pulse Width, LE1B, LE2B, LEA1B, LEA2B HIGH Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
PHAS INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORM ALLY CLOSE tPZH OUTPUT ITCH NORM ALLY OPEN HIGH LOAD tPLZ DISABLE LOAD
ALVC Link
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
Open
OUTPUT SKEW INPUT
tPLH1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2
PLH2
Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCHR16260 3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH
ORDERING INFORMATION
ALVC evice Type Package ange Bus-H
Shrink Outline Package O56-1) Thin Shrink Outline Package 56-2) Thin Very Outline Package (SO56-3) 12-Bit 24-Bit ultiplexed -Type Latch 3-State Outputs ouble-D ensity esistors, ±12m
Bus-H -40°C +85°C
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3.3V CMOS 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

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