3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD

Datasheet Thumbnail

Top Searches for this datasheet

IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 1.27mm pitch SOIC, 0.65mm pitch SSOP, 0.635mm pitch QSOP, 0.65mm TSSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V ±0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin
IDT74ALVCH373 ADVANCE INFORMATION
DESCRIPTION:
This octal transparent D-type latch built using advanced dual metal CMOS technology. ALVCH373 device particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. While latch-enable (LE) input high, outputs follow data inputs. When taken low, outputs latched logic levels inputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) highimpedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without interface pullup components. ALVCH373 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH373 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features ALVCH373: High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
Functional Block Diagram
SEVEN OTHER CHANNELS
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4474/-
IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
CONFIGURATION
ABSOLUTE MAXIMUM RATING(1)
SO20-2 SO20-7 SO20-8 SO20-9
Symbol VTERM(2) VTERM(3)
TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. -0.5 ±100
Unit
ALVC Link
SSOP/ TVSOP/ TSSOP/ QSOP VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25°C, 1.0MHz) DESCRIPTION
Names Description Output Enable Input (Active LOW) Latch Enable Input (Active HIGH) Data Inputs(1) 3-State Outputs
Symbol COUT CI/O
Parameter(1) Input Capacitance Output Capacitance Port Capacitance
Conditions VOUT
Typ.
Max.
Unit
ALVC Link
NOTE: applicable device type.
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLE
Inputs
Output
NOTE: HIGH Voltage Level Voltage Level Don't Care High Impedance Level before indicated steady-state input conditions were established.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
ALVC Link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
ALVC Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
ALVC Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V ±0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V±0.3V Typical Unit
SWITCHING CHARACTERISTICS
2.5V±0.2V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Output Enable Time Output Disable Time Pulse Duration, HIGH Setup Time, data before Hold Time, data after Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V±0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
ALVC Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2
ALVC Link
D.U.T.
ALVC Link
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM
ALVC Link
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
ALVC Link
OUTPUT SKEW INPUT tPLH1
tPHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2 tPHL2
tPLH2 tPLH1 PHL2 tPHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
ALVC Link
IDT74ALVCH373 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
ALVC Device Type Package Temp. Range Bus-Hold
Small Outline (SO20-2) Shrink Small Outline Package (SO20-7) Quarter-size Small Outline Package (SO20-8) Thin Shrink Small Outline Package (SO20-9) Octal Transparent D-Type Latch with 3-State Outputs
Bus-Hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com*
search sales office near you, please click sales button found home page dial 800# above press logo registered trademark Integrated Device Technology, Inc.

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD

Top Searches for this datasheet

Other recent searches