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Intel® Embedded Flash Memory
Architecture High-density symmetrical 128-Kbyte blocks -128 Mbit (128 blocks) Mbit blocks) Mbit blocks) Performance Initial Access Speed (128/64/32 -Mbit densities) 8-word 4-word Asynchronous page-mode reads 32-Byte Write buffer Byte Effective programming time System Voltage Power VCCQ
Security Enhanced security options code protection 128-bit Protection Register -64-bit Unique device identifier -64-bit User-programmable cells Absolute protection with VPEN Individual block locking Block erase/program lockout during power transitions Software Program erase suspend support Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Quality Reliability Operating temperature: 100K Minimum erase cycles block 0.13 ETOXVIII Process Packaging 56-Lead TSOP package 64-Ball Intel® Easy package
Intel® Embedded Flash Memory Version provides improved mainstream performance with enhanced security features, taking advantage high quality reliability NOR-based Intel 0.13 ETOXVIII process technology. Offered 128-Mbit (16-Mbyte), 64-Mbit, 32-Mbit densities, device brings reliable, low-voltage capability read, program, erase) with high speed, low-power operation. device takes advantage proven manufacturing experience ideal code data applications where high density cost required, such networking, telecommunications, digital boxes, audio recording, digital imaging. Intel Flash Memory components also deliver generation forward-compatible software support. using Common Flash Interface (CFI) Scalable Command (SCS), customers take advantage density upgrades optimized write capabilities future Intel® Flash Memory devices.
Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
308551- Feburary 2006
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Contents
Introduction
Nomenclature Acronyms.6 Conventions.6 Block Diagram Memory Map. 56-Lead TSOP Package. Easy Package Easy Ballout (32/64/128 Mbit) 56-Lead TSOP Package Pinout (32/64/128 Mbit) Signal Descriptions Absolute Maximum Ratings Operating Conditions. Power Up/Down.20 5.3.1 Power-Up/Down Characteristics. 5.3.2 Power Supply Decoupling. Reset Current Specifications Voltage specifications. Capacitance.23 Read Specifications Write Specifications Program, Erase, Block-Lock Specifications. Reset Specifications Test Conditions. Reads 8.1.1 Asynchronous Page Mode Read 8.1.1.1 Enhanced Configuration Register (ECR).34 8.1.2 Output Disable Writes Standby.36 8.3.1 Reset/Power-Down. Device Commands
Functional Overview
Package Information
Ballouts Signal Descriptions
Maximum Ratings Operating Conditions.
Electrical Characteristics
Characteristics
Interface
Flash Operations
Status Register 9.1.1 Clearing Status Register. Read Operations 9.2.1 Read Array 9.2.2 Read Status Register 9.2.3 Read Device Information 9.2.4 Query Programming Operations 9.3.1 Single-Word/Byte Programming 9.3.2 Buffered Programming Block Erase Operations. Suspend Resume Status Signal (STS) Security Protection 9.7.1 Normal Block Locking. 9.7.2 Configurable Block Locking 9.7.3 Protection Registers. 9.7.4 Reading Protection Register 9.7.5 Programming Protection Register 9.7.6 Locking Protection Register 9.7.7 VPP/ VPEN Protection
Appendix Appendix Appendix
Device Command Codes Codes Flow Charts
Write Buffer.53 Status Register Byte/Word Programming Program Suspend/Resume Block Erase.57 Block Erase Suspend/Resume Block Locking.59 Unlock Block Protection Register Programming Query Structure Overview Block Status Register Query Identification String.64 System Interface Information.65 Device Geometry Definition.66 Primary-Vendor Specific Extended Query Table
Appendix
Common Flash Interface
Appendix Appendix
Additional Information Ordering Information.
Revision History
Date Revision July 2005 Version Initial release Marketing name changed from 28FxxxJ3 Table "Command Operations page updated September 2005 Section 9.2.2, "Read Status Register" page Section 9.3.2, "Buffered Programming" page Table "Valid Commands During Suspend" page Table "STS Configuration Register" page added Section 5.3.1, "Power-Up/Down Characteristics" page modified Notes Table Voltage Characteristics" page were updated February 2006 Table "Read Operations" page updated with Value Table "Configuration Performance" page updated Note Table "STS Configuration Coding Definitions" page updated Description
Introduction
This document contains information pertaining Intel® Embedded Flash Memory device features, operation, specifications.
Nomenclature
AMIN: AMAX: Densities Densities Mbit Mbit Mbit Block: Clear: Program: Set: VPEN: VPEN: AMIN AMIN AMAX AMAX AMAX
group flash cells that share common erase circuitry erase simultaneously Indicates logic zero write data flash array Indicates logic Refers signal package connection name Refers timing voltage levels
Acronyms
CUI: OTP: PLR: PRD: RFU: SRD: WSM: ECR: Command User Interface Time Programmable Protection Lock Register Protection Register Protection Register Data Reserved Future Status Register Status Register Data Write State Machine Enhanced Configuration Register
Conventions
(noun): (noun): Nibble Byte: Hexadecimal Affix 1,000 1,000,000 bits bits
Word: Kword: Brackets: 00FFh: 00FF 00FFh: DQ[15:0]:
bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will used designate group membership define group signals with similar function (i.e. A[21:1], SR[4,1] D[15:0]). Denotes 16-bit hexadecimal numbers Denotes 32-bit hexadecimal numbers Data signals
Functional Overview
Product Description
Intel® Embedded Flash Memory family contains high-density memory organized following configurations:
Mbytes Mword (128-Mbit), organized one-hundred-twenty-eight 128-Kbyte
(131,072 bytes) erase blocks
Mbytes Mword (64-Mbit), organized sixty-four 128-Kbyte erase blocks Mbytes Mword (32-Mbit), organized thirty-two 128-Kbyte erase blocks
These devices accessed 16-bit words. Figure Memory Block Diagram" page further details. 128-bit Protection Register multiple uses, including unique flash device identification. Intel® Embedded Flash Memory device includes security features that were available (previous) 0.25m 0.18m versions family. These security features prevent altering code through different protection schemes that implemented, based user requirements. device optimized architecture interface dramatically increases read performance supporting page-mode reads. This read mode ideal non-clock memory systems. Common Flash Interface (CFI) permits software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward- backwardcompatible software support specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. Scalable Command (SCS) allows single, simple software driver host systems work with SCS-compliant flash memory devices, independent system-level packaging (e.g., memory card, SIMM, direct-to-board placement). Additionally, provides highest system/device data transfer rates minimizes device system-level implementation costs. Command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence written initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. block erase operation erases device's 128-Kbyte blocks typically within second, independent other blocks. Each block independently erased 100,000 times. Block erase suspend mode allows system software suspend block erase read program data from other block. Similarly, program suspend allows system software suspend programming (byte/ word program write-to-buffer operations) read data execute code from other block that being suspended. Each device incorporates Write Buffer bytes words) allow optimum programming performance. using Write Buffer, data programmed buffer increments.
Blocks selectively individually lockable in-system. Individual block locking uses block lock-bits lock unlock blocks. Block lock-bits gate block erase program operations. Lock-bit configuration operations clear lock-bits (using Block Lock-Bit Clear Block Lock-Bits commands). Status Register indicates when WSM's block erase, program, lock-bit configuration operation finished. (STATUS) output gives additional indicator activity providing both hardware signal status (versus software polling) status masking (interrupt masking background block erase, example). Status indication using minimizes both overhead system power consumption. When configured level mode (default mode), acts signal. When low, indicates that performing block erase, program, lockbit configuration. STS-high indicates that ready command, block erase suspended (and programming inactive), program suspended, device reset/powerdown mode. Additionally, configuration command allows signal configured pulse completion programming and/or block erases. Three signals used enable disable device. unique logic design (see Table "Chip Enable Truth Table" page reduces decoder logic typically required multi-chip designs. External logic required when designing single chip, dual chip, 4chip miniature card SIMM module. BYTE# signal allows either read/writes device:
BYTE#-low enables 8-bit mode; address selects between byte high byte. BYTE#-high enables16-bit operation; address becomes lowest order address
address used (don't care). Figure Memory Block Diagram" page shows device block diagram. When device disabled (see Table "Chip Enable Truth Table" page 33), with VIH, standby mode enabled. When VIL, further power-down mode enabled which minimizes power consumption provides write protection during reset. reset time (tPHQV) required from going high until data outputs valid. Likewise, device wake time (tPHWL) from RP#-high until writes recognized. With VIL, reset Status Register cleared.
Block Diagram
Figure Memory Block Diagram
DQ15
VCCQ
Output Buffer
Input Buffer
Output tch/Multi exer
Query Write Buffe Identifier Register Status Register Data Registe
Logic Logic
BYTE#
Command User Interface
Data Comparator
Multiplexer
32-Mbit: 64-Mbit: 128-Mbit:
Input Buffer
Y-Decoder
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty -eight Write State Machine Program/Erase Voltage Switch
Address Latch Address Counter
X-Decoder
128-Kbyte Blocks
Memory
Figure Memory
[23-0]:128 Mbit [22-0]: Mbit [21-0]: Mbit
0FFFFFF 0FE0000
[23-1]: Mbit [22-1]: Mbit [21-1]: Mbit
7FFFFF 7F0000
128-Kbyte Block
64-Kword Block
07FFFFF 07E0000
128-Kbyte Block
3FFFFF 3F0000
64-Kword Block
03E0000
128-Kbyte Block
1F0000
64-Kword Block
003FFFF 0020000 001FFFF 0000000
128-Kbyte Block 128-Kbyte Block
01FFFF 010000 00FFFF 000000
64-Kword Block 64-Kword Block
Byte-Wide (x8) Mode
Word Wide (x16) Mode
32-Mbit
64-Mbit
03FFFFF
1FFFFF
128-Mbit
Package Information
56-Lead TSOP Package
Figure 56-Lead TSOP Package Mechanical
Notes
Note
Detail
Seating Plane
Detail
Detail Detail
Table
56-Lead TSOP Dimension Table (Sheet
Millimeters 1.200 0.050 0.965 0.100 0.100 18.200 13.800 19.800 0.500 0.995 0.150 0.150 18.400 14.000 0.500 20.00 0.600 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 0.795 0.028 0.040 0.008 0.008 0.732 0.559 Inches 0.047
Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Length Lead Count
Table
56-Lead TSOP Dimension Table (Sheet
Millimeters 0.100 0.150 0.250 0.350 0.006 0.010 Inches 0.004 0.014
Lead Angle Seating Plane Coplanarity Lead Package Offset
Easy Package
Figure Easy Mechanical Specifications
Ball Corner Ball Corner
View Ball side down
Bottom View Ball Side
Seating Plane
Note: Drawing scale
Table
Easy Package Dimensions Table
Millimeters
Symbol 1.200 0.250 0.780 0.330 9.900 12.900 0.430 10.000 13.000 1.000 0.100 1.400 2.900 1.500 3.000 1.600 3.100 0.0551 0.1142 0.0591 0.1181 0.530 10.100 13.100 0.0130 0.3898 0.5079 0.0098 0.0307 0.0169 0.3937 0.5118 0.0394 0.0039 0.0630 0.1220 0.0209 0.3976 0.5157 Notes
Inches
0.0472
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along (32/64/128 Corner Ball Distance Along (32/64/128
NOTES: Daisy Chain Evaluation Unit information refer Intel Flash Memory Packaging Technology page Packaging Shipping Media information refer Intel Flash Memory Packaging Technology page www.intel.com/ design/packtech/index.htm
Ballouts Signal Descriptions
Intel® Embedded Flash Memory available package types. Each density supported both 64-ball Easy 56-lead Thin Small Outline Package (TSOP) packages. Figure Figure show pinouts.
Easy Ballout (32/64/128 Mbit)
Figure Easy Ballout (32/64/128 Mbit)
VPEN
VPEN
CE0# CE1# CE1# CE0#
BYTE# BYTE#
VCCQ VCCQ
CE2# CE2# Intel® Embedded Flash Memory (28FXXXJ3D) Easy View- Ball side down 32/64/128 Mbit Intel® Embedded Flash Memory (28FXXXJ3D) Easy Bottom View- Ball side 32/64/128 Mbit
NOTES: Address only valid 64-Mbit densities above, otherwise, connect (NC). Address only valid 128-Mbit densities above, otherwise, connect (NC).
56-Lead TSOP Package Pinout (32/64/128 Mbit)
Figure 56-Lead TSOP Package Pinout (32/64/128 Mbit)
VPEN DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 BYTE#
Intel® Embedded Flash Memory (28FXXXJ3D) 56-Lead TSOP Standard Pinout View
32/64/128 Mbit
NOTES: exists 128- densities. 32-Mbit density this signal no-connect (NC). exists 128-Mbit densities. 64-Mbit densities this signal no-connect (NC)
Signal Descriptions
Table lists active signals used provides description each.
Table
Symbol
Signal Descriptions (Sheet
Type Name Function BYTE-SELECT ADDRESS: Selects between high byte when device mode. This address latched during program cycle. used mode (i.e., input buffer turned when BYTE# high). ADDRESS INPUTS: Inputs addresses during read program operations. Addresses internally latched during program cycle:
Input
A[MAX:1]
Input
32-Mbit A[21:1] 64-Mbit A[22:1] 128-Mbit A[23:1]
LOW-BYTE DATA BUS: Inputs data during buffer writes programming, inputs commands during writes. Outputs array, CFI, identifier, status data appropriate read mode. Data internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during buffer writes programming operations. Outputs array, CFI, identifier data appropriate read mode; used Status Register reads. Data internally latched during write operations mode. D[15-8] float mode CHIP ENABLES: Activate 32-, Mbit devices' control logic, input buffers, decoders, sense amplifiers. When device de-selected (see Table "Chip Enable Truth Table" page 33), power reduces standby levels.
D[7:0]
Input/Output
D[15:8]
Input/Output
CE[2:0]
Input
timing specifications same these three signals. Device selection occurs with first edge CE0#, CE1#, CE2# that enables device. Device deselection occurs with first edge CE0#, CE1#, CE2# that disables device (see Table "Chip Enable Truth Table" page 33).
RESET: RP#-low resets internal automation puts device power-down mode. RP#-high enables normal operation. Exit from reset sets device read array mode. When driven low, inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates device's outputs through data buffers during read cycle. active low. WRITE ENABLE: Controls writes CUI, Write Buffer, array blocks. active low. Addresses data latched rising edge WE#. STATUS: Indicates status internal state machine. When configured level mode (default), acts RY/BY# signal. When configured pulse modes, pulse indicate program and/or erase completion. alternate configurations STATUS signal, Configurations command Section 9.6, "Status Signal (STS)" page tied VCCQ with pull-up resistor. BYTE ENABLE: BYTE#-low places device mode; data input output D[7:0], while D[15:8] placed High-Z. Address selects between high byte. BYTE#-high places device mode, turns input buffer. Address becomes lowest-order address bit. ERASE PROGRAM BLOCK LOCK ENABLE: erasing array blocks, programming data, configuring lock-bits. With VPEN VPENLK, memory contents cannot altered. CORE Power Supply: Core (logic) source voltage. Writes flash array inhibited when VLKO. Caution: Device operation invalid voltages should attempted. Power Supply: Power supply Input/Output buffers.This ball tied directly VCC.
Input Input Input
Open Drain Output
BYTE#
Input
VPEN
Input
VCCQ
Power Power
Table
Symbol
Signal Descriptions (Sheet
Type Name Function Ground: Ground reference device logic voltages. Connect system ground. Connect: Lead internally connected; driven floated. Reserved Future Use: Balls designated reserved Intel future device functionality enhancement.
Supply
Warning:
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only.
NOTICE: This document contains information available time release. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Table
Absolute Maximum Ratings
Parameter Unit Notes
Temperature under Bias Expanded (TA, Ambient) Storage Temperature Voltage VCCQ Voltage input/output signal (except VCC, VCCQ) Output Short Circuit Current
-2.0 -2.0 -2.0
+125 +5.6 +5.6 VCCQ (max)
NOTES: Voltage referenced VSS. During infrequent non-periodic transitions, voltage potential between input/output pins undershoot -2.0 periods overshoot VCCQ (max) periods During infrequent non-periodic transitions, voltage potential between supplies undershoot periods VSUPPLY (max) periods Output shorted more than second. more than output shorted time
Warning:
Operating Conditions
Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability
Table
Symbol
Temperature Operating Condition
Parameter Unit Test Condition
VCCQ Supply Voltage VCCQ Supply Voltage
-40.0 2.70 2.70
Ambient Temperature
Power Up/Down
This section provides overview system level considerations with regards flash device. includes brief description power-up, power-down decoupling design considerations.
5.3.1
Power-Up/Down Characteristics
prevent conditions that could result spurious program erase operations, power-up/ power-down sequence shown Table recommended. voltage characteristics refer Table Note that each power supply must reach minimum voltage range before applying/ removing next supply voltage.
Table
Power-Up/Down Sequence
Power Supply Voltage Power-UpSequence Power-Down Sequence
VCC(min) VCCQ(min) VPEN(min)
Sequencing required
Sequencing required
Power supplies connected sequenced together. Device inputs must driven until supply voltages reach their minimum range. should during power transitions.
5.3.2
Power Supply Decoupling
When device enabled, many internal conditions change. Circuits energized, charge pumps switched internal voltage nodes ramped. this internal activities produce transient signals. magnitude transient signals depends device system loading. minimize effect these transient signals, ceramic capacitor required across each VCC/VSS VCCQ signal. Capacitors should placed close possible device connections. Additionally, every eight flash devices, electrolytic capacitor should placed between power supply connection. This capacitor should help overcome voltage slumps caused (printed circuit board) trace inductance.
Reset
holding flash device reset during power-up power-down transitions, invalid conditions masked. flash device enters reset mode when driven low. reset, internal flash circuitry disabled outputs placed high-impedance state. After return from reset, certain amount time required before flash device able perform normal operations. After return from reset, flash device defaults asynchronous page mode. driven during program erase operation, program erase operation will aborted memory contents aborted block address longer valid. Figure Waveform Reset Operation" page detailed information regarding reset timings.
Table
Electrical Characteristics
Current Specifications
Current Characteristics (Sheet
VCCQ 3.6V 3.6V Unit Test Conditions Notes
Symbol
Parameter
Input VPEN Load Current Output Leakage Current
Max; VCCQ VCCQ VCCQ VCC= Max; VCCQ VCCQ VCCQ CMOS Inputs, Max; Vccq VccqMax Device disabled (see Table "Chip Enable Truth Table" page 33), VCCQ Inputs, Max, Vccq VccqMax Device disabled (see Table "Chip Enable Truth Table" page 33), IOUT (STS) CMOS Inputs, Max, VCCQ VCCQ
ICCS Standby Current 0.71
1,2,3
ICCD
Power-Down Current
4Word Page
Device enabled (see Table "Chip Enable Truth Table" page MHz, IOUT CMOS Inputs,VCC Max, VCCQ VCCQ Device enabled (see Table "Chip Enable Truth Table" page MHz, IOUT CMOS Inputs, Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table "Chip Enable Truth Table" page MHz, IOUT CMOS Inputs,VCC Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table "Chip Enable Truth Table" page MHz, IOUT Density: 128-, 64-, Mbit CMOS Inputs, VPEN Inputs, VPEN
ICCR Page Mode Read Current 8Word Page
ICCW
Program Lock-Bit Current
Table
Current Characteristics (Sheet
VCCQ 3.6V 3.6V Unit Test Conditions Notes
Symbol
Parameter
ICCE ICCWS ICCES
Block Erase Clear Block Lock-Bits Current Program Suspend Block Erase Suspend Current
CMOS Inputs, VPEN Inputs, VPEN Device enabled (see Table "Chip Enable Truth Table" page
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Contact Intel's Application Support Hotline your local sales office information about typical specifications. Includes STS. CMOS inputs either inputs either VIH. Sampled, 100% tested. ICCWS ICCES specified with device selected. device read written while erase suspend mode, device's current draw ICCR ICCWS
Table
Voltage specifications
Voltage Characteristics (Sheet
VCCQ Unit Test Conditions Notes
Symbol
Parameter
Input Voltage Input High Voltage
-0.5
VCCQ 0.5V
VCCMin VCCQ VCCQ VCCMin VCCQ VCCQ VCCMIN VCCQ VCCQ -2.5 VCCMIN VCCQ VCCQ -100
Output Voltage
0.85 VCCQ Output High Voltage VCCQ VPEN Lockout during Program, Erase Lock-Bit Operations
VPENLK
Table
Voltage Characteristics (Sheet
VCCQ Unit Test Conditions Notes
Symbol
Parameter
VPEN VLKO
VPEN during Block Erase, Program, Lock-Bit Operations Lockout Voltage
NOTES: Includes STS. Sampled, 100% tested. Block erases, programming, lock-bit configurations inhibited when VPEN VPENLK, guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Block erases, programming, lock-bit configurations inhibited when VLKO, guaranteed range between VLKO (min) (min), above (max). Includes operational modes device including standby power-up sequences Input/Output signals undershoot -1.0v referenced overshoot VCCQ 1.0v duration less, VCCQ valid range referenced VSS.
Capacitance
Table
Symbol
Capacitance
Parameter1 Type Unit Condition2
COUT
Input Capacitance Output Capacitance
VOUT
NOTES: sampled. 100% tested.
Characteristics
Timing symbols used timing diagrams within this document conform following convention:
Source Signal Source State
Signal
Target State Target Signal
Code
State
Code
Address Data Read Data Write Chip Enable (CE#) Output Enable (OE#) Write Enable (WE#) Address Valid (ADV#) Reset (RST#) Clock (CLK) WAIT
High High-Z Low-Z Valid Invalid
Note:
Exceptions this convention include tACC tAPA. tACC generic timing symbol that refers aggregate initial-access delay determined tAVQV, tELQV, tGLQV (whichever satisfied last) flash device. tAPA specified flash device's data sheet, address-to-data delay subsequent page-mode reads.
Read Specifications
Table Read Operations
Asynchronous Specifications V-3.6 VCCQ V-3.6 V(3) Parameter Density Unit Notes
Mbit tAVAV Read/Write Cycle Time Mbit Mbit Mbit tAVQV Address Output Delay Mbit Mbit Mbit tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tELFL/ tELFH tFLQV/ tFHQV tFLQZ tEHEL tAPA tGLQV Output Delay Mbit Mbit Non-Array Output Delay Mbit High Output Delay Mbit Mbit Output Output High Output High High Output High Output Hold from Address, CEX, Change, Whichever Occurs First BYTE# High BYTE# Output Delay BYTE# Output High High Page Address Access Time Array Output Delay
NOTES:
1,2,4 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page
Input/Output Reference Waveforms maximum allowable input slew rate.
delayed tELQV-tGLQV after first edge CE0, CE1, that enables device (see Table "Chip Enable Truth Table" page without impact tELQV. Figure Input/Output Reference Waveform" page Figure "Transient Equivalent Testing Load Circuit" page testing characteristics. Sampled, 100% tested. devices configured standard word/byte read mode, (tAPA) will equal (tAVQV).
Figure Single Word Asynchronous Read Waveform
Address Data [D/Q] BYTE#[F]
NOTES: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page 33). When reading flash array faster tGLQV (R16) applies. non-array reads, applies (i.e., Status Register reads, query reads, device identifier reads).
Figure 4-Word Asynchronous Page Mode Read Waveform
A[MAX:3] A[2:1] D[15:0]
NOTE: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page 33).
Figure 8-Word Asynchronous Page Mode Read
A[MAX:4] A[3:1] D[15:0] BYTE#
NOTES: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page 33). this diagram, BYTE# asserted high
Write Specifications
Table Write Operations
Valid Speeds
Symbol
Parameter
Density
Unit
Notes
Mbit tPHWL (tPHEL) tELWL (tWLEL) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL High Recovery (CEX) Going (WE#) (CEX) Going Write Pulse Width Data Setup (CEX) Going High Address Setup (CEX) Going High (WE#) Hold from (CEX) High Data Hold from (CEX) High Address Hold from (CEX) High Write Pulse Width High VPEN Setup (CEX) Going High Write Recovery before Read (CEX) High Going VPEN Hold from Valid SRD, Going High Mbit Mbit
NOTES:
1,2,3
1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 1,2,8 1,2,3,8,9
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page
Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Refer Table "Enhanced Configuration Register" page valid block erase, program, lock-bit configuration. Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY# default mode. VPEN should held VPENH until determination block erase, program, lock-bit configuration success (SR[1,3,4,5]
Figure Asynchronous Write Waveform
ADDRESS (WE#) (W)] (CEx) (E)] DATA [D/Q] STS[R] VPEN
Figure Asynchronous Write Read Waveform
Address Data [D/Q] VPEN
Program, Erase, Block-Lock Specifications
Table Configuration Performance
Symbol Parameter Max(8) Unit Notes
tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH tSTS
Write Buffer Byte Program Time (Time Program bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write Buffer Command)
0.53
0.70
1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,9 1,2,3,9 1,2,3,9
Block Erase Time Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time Read Erase Suspend Latency Time Read Pulse Width Time
NOTES: Typical values measured nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. These performance numbers valid speed versions. Sampled 100% tested. Excludes system-level overhead. These values valid when buffer full, start address aligned 32-byte boundary. Effective per-byte program time (tWHQV1, tEHQV1) 4s/byte (typical). Effective per-word program time (tWHQV2, tEHQV2) 8s/word (typical). values measured worst case temperature, data pattern corner after 100k cycles (except noted). values expressed °C/-40
Reset Specifications
Figure Waveform Reset Operation
NOTE: shown default mode (RY/BY#)
Table Reset Specifications
Symbol Parameter Unit Notes
tPLPH tPHRH tVCCPH
Pulse Time tied VCC, this specification applicable) High Reset during Block Erase, Program, Lock-Bit Configuration Power Valid de-assertion (high)
NOTES: These specifications valid product versions (packages speeds). asserted while block erase, program, lock-bit configuration operation executing then minimum required Pulse Time reset time, tPHQV, required from latter RY/BY# mode) going high until outputs valid.
Test Conditions
Figure Input/Output Reference Waveform
VCCQ Input VCCQ/2
NOTE: test inputs driven VCCQ Logic Logic "0." Input timing begins, output timing ends, VCCQ/2 (50% VCCQ). Input rise fall times (10% 90%)
Test Points
VCCQ/2
Output
Figure Transient Equivalent Testing Load Circuit
Device Under Test
NOTE: Includes Capacitance Test Configuration (pF)
VCCQ VCCQMIN
Interface
This section provides overview operations. Basically, there three operations with flash memory: Read, Program (Write), Erase.The on-chip Write State Machine (WSM) manages erase program algorithms. system provides control in-system read, write, erase operations through system bus. cycles from flash memory conform standard microprocessor cycles. Table summarizes necessary states each control signal different modes operations.
Table Operations
Mode Async., Status, Query Identifier Reads Output Disable Standby Reset/Power-down Command Writes Array Writes
CEx(1) Enabled Enabled Disabled Enabled Enabled
OE#(2)
VPEN VPENH
DQ15:0(3) DOUT High High High
(Default Mode) High High High High High
Notes
NOTES: Table valid Configurations. should never asserted simultaneously. done overrides WE#. refers DQ[7:0} when BYTE# DQ[15:0] BYTE# high. Refer characteristics. When VPEN VPENLK, memory contents read altered. should control pins VPENLK VPENH VPEN. outputs, should VOH. default mode, when executing internal block erase, program, lock-bit configuration algorithm. (pulled external pull resistance 10k) when busy, block erase suspend mode (with programming inactive), program suspend mode, reset powerdown mode. Table "Command Operations page valid (user commands) during Write operation Array writes either program erase operations.
Table Chip Enable Truth Table
DEVICE
Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: single-chip applications, connected GND.
next sections detail each basic flash operations some advanced features available flash memory.
Reads
Reading from flash memory outputs stored information processor chipset, does change contents. Reading performed unlimited number times. Besides array data, other types data such device information device status available from flash. perform read operation, (refer Table page must asserted. device-select control; when active, enables flash memory device. dataoutput control; when active, addressed flash memory data driven onto bus. read states, must de-asserted. Section 9.2, "Read Operations" page
8.1.1
Asynchronous Page Mode Read
There Asynchronous Page mode configurations available depending system design requirements:
Four-Word Page mode: This default mode power-up reset. Array data
sensed four words Bytes) time.
Eight-Word Page mode: Array data sensed eight words Bytes) time. This
mode must enabled power-up reset using command sequence described Table page Address bits A[3:1] determine which word output during read operation, A[3:0] determine which byte output width.
After initial access delay, first word page buffer corresponds initial address. Four-Word Page mode, address bits A[2:1] determine which word output from page buffer width, A[2:0] determine which byte output from page buffer width. Subsequent reads from device come from page buffer. These reads output D[15:0] width D[7:0] width after minimum delay long A[2:0] (Four-Word Page mode) A[3:0] (Eight-Word Page mode). Data read from page buffer multiple times, order. Four-Word Page mode, address bits A[MAX:3] (A[MAX:4] Eight-Word Page Mode) change time, toggled, device will sense load data into page buffer. Asynchronous Page mode default read mode power-up reset. perform Page mode read after other operation, Read Array command must issued read from flash array. Asynchronous Page mode reads permitted blocks used access register information. During register access, only word loaded into page buffer.
8.1.1.1
Enhanced Configuration Register (ECR)
Enhanced Configuration Register (ECR) volatile storage register that when addressed Enhanced Configuration Register command select between Four-Word Page mode Eight-Word Page mode. volatile; bits will reset default values when deasserted power removed from device. modify settings, Enhanced Configuration Register command. Enhanced Configuration Register command written along with configuration register value, which placed lower bits address A[15:0]. This followed second write that confirms operation again presents Enhanced Configuration Register data address bus. After executing this command, device returns Read Array mode. shown Table 8-word page mode Command Bus-Cycle captured Table
Note:
forward compatibility reasons, 8-word Asynchronous Page mode used Clear Status Register command must executed after issuing Enhanced Configuration Register command. Table further details.
Table Enhanced Configuration Register
Reserved Page Length Reserved
BITS
DESCRIPTION
NOTES
ECR[15:14] ECR[13] ECR[12:0]
Word Page mode Word Page mode
bits should
bits should
Table Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command Cycles Required First Cycle Oper Addr(1) Data Oper Second Cycle Addr(1) Data
Enhanced Configuration Register (Set ECR)
Write
0060h
Write
0004h
valid address within device. Enhanced Configuration Register Data
8.1.2
Output Disable
With asserted, logic-high level (VIH), device outputs disabled. Output signals D[15:0] placed high-impedance state.
Writes
Writing Programming device, where host writes information data into flash device non-volatile storage. When flash device programmed, `ones' changed `zeros'. `Zeros' cannot programed back `ones'. erase operation must performed. Writing commands Command User Interface (CUI) enables various modes operation, including following:
Reading array data Common Flash Interface (CFI) data Identifier codes, inspection, clearing Status Register Block Erasure, Program, Lock-bit Configuration (when VPEN VPENH)
Erasing performed block basis flash cells within block erased together. information data previously stored block will lost. Erasing typically done prior programming. Block Erase command requires appropriate command data address within block erased. Byte/Word Program command requires command
address location written. Block Lock-Bit commands require command block within device locked. Clear Block Lock-Bits command requires command address within device cleared. does occupy addressable memory location. written when device enabled active. address data needed execute command latched rising edge first edge CE0, CE1, that disables device (see Table page 33). Standard microprocessor write timings used.
Standby
CE0, CE1, disable device (see Table page place standby mode. This manipulation substantially reduces device power consumption. D[15:0] outputs placed high-impedance state independent OE#. deselected during block erase, program, lock-bit configuration, continues functioning, consuming active power until operation completes.
8.3.1
Reset/Power-Down
initiates reset/power-down mode. read modes, RP#-low deselects memory, places output drivers high-impedance state, turns numerous internal circuits. must held minimum tPLPH. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wakeup interval, normal operation restored. reset read array mode Status Register 0080h. During Block Erase, Program, Lock-Bit Configuration modes, RP#-low will abort operation. default mode, transitions remains maximum time tPLPH tPHRH until reset operation complete. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lock-bit configuration. Time tPHWL required after goes logic-high (VIH) before another command written. with automated device, important assert during system reset. When system comes reset, expects read from flash memory. Automated flash memories provide status information when accessed during Block Erase, Program, Lock-Bit Configuration modes. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel® Flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
Device Commands
When VPEN voltage VPENLK, only read operations from Status Register, CFI, identifier codes, blocks enabled. Placing VPENH VPEN additionally enables block erase, program, lock-bit configuration operations. Device operations selected writing specific commands Command User Interface (CUI). does occupy addressable memory location. mechanism through which flash device controlled.
command sequence issued consecutive write cycles Setup command followed Confirm command. However, some commands single-cycle commands consisting setup command only. Generally, commands that alter contents flash device, such Program Erase, require least write cycles guard against inadvertent changes flash device. Flash commands fall into categories: Basic Commands Extended Commands. Basic commands recognized Intel® Flash devices, used perform common flash operations such selecting read mode, programming array, erasing blocks. Extended commands product-dependant; they used perform additional features such software block locking. Table describes applicable commands Intel® Embedded Flash Memory Table Command Operations
Setup Write Cycle Command Address Data Address Data Confirm Write Cycle
Program Enhanced Configuration Register
Registers
Register Data Device Address Device Address Device Address Device Address Device Address Device Address Device Address Device Address Word Address Device Address Device Address Device Address Block Address Block Address
0060h 00C0h 0050h 00BS8h 00FFh 0070h 0090h 0098h 0040h/ 0010h 00E8h 0020h 00B0h 00D0h 0060h 0060h
Register Data Register Offset -Device Address -Device Address Device Address Block Address -Block Address Block Address
0004h Register Data -Register Data -Array Data 00D0h 00D0h -0001h 00D0h
Program Register Clear Status Register Program Configuration Register Read Array Read Status Register Read Identifier Codes (Read Device Information) Query Word/Byte Program Buffered Program Block Erase Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block
Security
Program Erase
Read Modes
Flash Operations
This section describes operational features flash memory. Operations command-based, wherein command codes first issued device, then device performs desired operation. command codes issued device using bus-write cycles (see Chapter 8.0, "Bus Interface"). complete list available command codes found Appendix "Device Command Codes".
Status Register
Status Register (SR) 8-bit, read-only register that indicates device status operation errors. read Status Register, issue Read Status Register command. Subsequent reads output Status Register information DQ[7:0], DQ[15:8]. status bits cleared device. error bits device, must cleared using Clear Status Register command. Upon power-up exit from reset, Status Register defaults 80h. Page-mode reads supported this read mode. Status Register contents latched falling edge first edge that enables device. must toggle device must disabled before further reads update Status Register latch. Read Status Register command functions independently VPEN voltage. Table shows Status Register definitions. Table Status Register Definitions Status Register (SR)
Ready Status Erase Suspend Status Name Erase Error Program Error Program /Erase Voltage Error Program Suspend Status Description Default Value BlockLocked Error
Reserved
Ready Status Erase Suspend Status Erase Error Program Error VPEN Error Program Suspend Status Block-Locked Error Reserved
Device busy; SR[6:0] invalid (Not driven); Device ready; SR[6:0] valid. Erase suspend effect. Erase suspend effect. Program erase operation successful. Program error operation aborted. Erase error operation aborted. Command sequence error command aborted. VPEN within acceptable limits during program erase operation. VPEN within acceptable limits during program erase operation. Operation aborted. Program suspend effect. Program suspend effect. Block locked during program erase operation successful. Block locked during program erase operation aborted. used Reserved future use.
Command Sequence Error
9.1.1
Clearing Status Register
Status Register (SR) contain status error bits which device. status bits cleared device, however error bits cleared issuing Clear Status Register command (see Table 20). Resetting device also clears Status Register. Table Clear Status Register Command Bus-Cycle
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Clear Status Register
Device Address
0050h
Issuing Clear Status Register command places device Read Status Register mode. Note: Care should taken avoid Status Register ambiguity. command sequence error occurs while Erase Suspend condition, Status Register will indicate Command Sequence error setting SR5. When erase operation resumed (and finishes), errors that have occurred during erase operation will masked Command Sequence error. avoid this situation, clear Status Register prior resuming suspended erase operation. Clear Status Register command functions independent voltage level VPEN.
Read Operations
Four types data read from device: array data, device information, data, device status. Upon power-up return from reset, device defaults Read Array mode. change device's read mode, appropriate command must issued device. Table shows command codes used configure device desired read mode. following sections describe each read mode.
Table Read Mode Command Bus-Cycles
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Read Array Read Status Register Read Device Information Query
Device Address Device Address Device Address Device Address
00FFh 0070h 0090h 0098h
9.2.1
Read Array
Upon power-up return from reset, device defaults Read Array mode. Issuing Read Array command places device Read Array mode. Subsequent reads output array data DQ[15:0]. device remains Read Array mode until different read command issued, program erase operation performed, which case, read mode automatically changed Read Status.
change device Read Array mode while programming erasing, first issue Suspend command. After operation been suspended, issue Read Array command. When program erase operation subsequently resumed, device will automatically revert back Read Status mode. Note: Issuing Read Array command device while actively programming erasing causes subsequent reads from device output invalid data. Valid array data output only after program erase operation finished. Read Array command functions independent voltage level VPEN.
9.2.2
Read Status Register
Issuing Read Status Register command places device Read Status Register mode. Subsequent reads output Status Register information DQ[7:0], DQ[15:8]. device remains Read Status Register mode until different read-mode command issued. Performing program, erase, block-lock operation also changes device's read mode Read Status Register mode. Status Register updated falling edge CE#, when low. Status Register contents valid only when When active, indicates WSM's state SR[6:0] hig-Z state. Read Status Register command functions independent voltage level VPEN.
9.2.3
Read Device Information
Issuing Read Device Information command places device Read Device Information mode. Subsequent reads output device information DQ[15:0] (see Table 22).
Table Device Information Summary
Device Information Word Address DQ[15:0]
Device Manufacturer Code (Intel) Device Code Block Lock Status Lock Register Register Factory Segment Register User-Programmable Segment
Device Base Address Device Base Address Block Base Address Device Base Address Device Base Address Device Base Address
0089h (See Appendix Codes") Unlocked Locked DQ[15:1] Lock Register Data Factory-Programmed Data User Data
device remains Read Device Information mode until different read command issued. Also, performing program, erase, block-lock operation changes device Read Status Register mode. Read Device Information command functions independent voltage level VPEN.
9.2.4
Query
query table contains assortment flash product information such block size, density, allowable command sets, electrical specifications, other product information. data contained this table conforms Common Flash Interface (CFI) protocol. Issuing Query command places device Query mode. Subsequent reads output information DQ[15:0] (see Appendix "Common Flash Interface"). device remains Query mode until different read command issued, program erase operation performed, which changes read mode Read Status Register mode. Query command functions independent voltage level VPEN.
Programming Operations
Programming flash array changes `ones' `zeros'. change zeros ones, erase operation must performed (see Section 9.4, "Block Erase Operations"). Only programming operation occur time. Programming permitted during erase suspend. Information programmed into flash array issuing appropriate command. supports different programming methods: Byte/Word Write-to-Buffer. Table shows two-cycle command sequences used each method.
Table Program Command Bus-Cycles
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Single-Word/Byte Program Buffered Program
Device Address Device Address
0040h/0010h 00E8h
Device Address Device Address
Array Data 00D0h
Note:
programming operations require addressed block unlocked, valid VPEN voltage applied throughout programming operation. Otherwise, programming operation will abort, setting appropriate Status Register error bit(s). following sections describe each programming method.
9.3.1
Single-Word/Byte Programming
Array programming performed first issuing Single-Word/Byte Program command. This followed writing desired data desired array address. read mode device automatically changed Read Status Register mode, which remains effect until another readmode command issued. During programming, Status Register indicate busy status (SR7 Upon completion, Status Register indicate ready status (SR7 Status Register should checked errors (SR4), then cleared.
Note:
Issuing Read Array command device while actively programming causes subsequent reads from device output invalid data. Valid array data output only after program operation finished. Standby power levels realized until programming operation finished. Also, asserting aborts programming operation, array contents addressed location indeterminate. addressed block should erased, data re-programmed. SingleWord/Byte program attempted when corresponding block lock-bit set, will set.
9.3.2
Buffered Programming
Buffered programming operations simultaneous program multiple words into flash memory array, significantly reducing effective word-write times. User-data first written write buffer, then programmed into flash memory array buffer-size increments. Appendix "Flow Charts" contains flow chart buffered-programming operation. Note: Optimal performance power consumption realized only aligning start address 32word boundaries (i.e., A[4:0] 0b00000). Crossing 32-word boundary during buffered programming operation cause programming time double. perform buffered programming operation, first issue Buffered Program setup command desired starting address. read mode device/addressed partition automatically changed Read Status Register mode. Polling determines write-buffer availability available, available). write buffer available, re-issue setup command check SR7; repeat until Next, issue word count desired starting address. word count represents total number words written into write buffer, minus one. This value range from (one word) maximum words). Exceeding allowable range causes abort. Following word count, write buffer filled with user-data. Subsequent bus-write cycles provide addresses data, word count. user-data addresses must between <starting address> <starting address word count>, otherwise continues normal but, user advertently change content unexpected address locations. Note: User-data programmed into flash array address issued when filling write buffer. After user-data written into write buffer, issue confirm command. command other than confirm command issued device, command sequence error occurs operation aborts. After issuing confirm command, write-buffer contents programmed into flash memory array. Status Register indicates busy status (SR7 during array programming. Note: Issuing Read Array command device while actively programming erasing causes subsequent reads from device output invalid data. Valid array data output only after program erase operation finished. Upon completion array programming, Status Register indicates ready (SR7 full Status Register check should performed check programming errors, then cleared using Clear Status Register command.
Additional buffered programming operations initiated issuing another setup command, repeating buffered programming bus-cycle sequence. However, errors Status Register must first cleared before another buffered programming operation initiated.
Block Erase Operations
Erasing block changes `zeros' `ones'. change ones zeros, program operation must performed (see Section 9.3, "Programming Operations"). Erasing performed block basis entire block erased each time erase command sequence issued. Once block fully erased, addressable locations within that block read logical ones (FFFFh). Only blockerase operation occur time, permitted during program suspend. perform block-erase operation, issue Block Erase command sequence desired block address. Table shows two-cycle Block Erase command sequence.
Table Block-Erase Command Bus-Cycle
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Block Erase
Device Address
0020h
Block Address
00D0h
Note:
block-erase operation requires addressed block unlocked, valid voltage applied VPEN throughout block-erase operation. Otherwise, operation will abort, setting appropriate Status Register error bit(s). Erase Confirm command latches address block erased. addressed block preconditioned (programmed zeros), erased, then verified. read mode device automatically changed Read Status Register mode, remains effect until another read-mode command issued. During block-erase operation, Status Register indicates busy status (SR7 Upon completion, Status Register indicates ready status (SR7 Status Register should checked errors, then cleared. errors occur, subsequent erase commands device ignored unless Status Register cleared. only valid commands during block erase operation Read Array, Read Device Information, Query, Erase Suspend. After block-erase operation completed, valid command issued.
Note:
Issuing Read Array command device while actively erasing causes subsequent reads from device output invalid data. Valid array data output only after block-erase operation finished. Standby power levels realized until block-erase operation finished. Also, asserting aborts block-erase operation, array contents addressed location indeterminate. addressed block should erased before programming within block attempted.
Suspend Resume
erase programming operation suspended perform other operations, then subsequently resumed. Table shows Suspend Resume command bus-cycles. Note: erase programming operations require addressed block remain unlocked with valid voltage applied VPEN throughout suspend operation. Otherwise, block-erase programming operation will abort, setting appropriate Status Register error bit(s). Also, asserting aborts suspended block-erase programming operations, rendering array contents addressed location(s) indeterminate.
Table Suspend Resume Command Bus-Cycles
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Suspend Resume
Device Address Device Address
00B0h 00D0h
suspend on-going erase program operation, issue Suspend command device address. program erase operation suspends pre-determined points during operation after delay tSUSP. Suspend achieved when RY/BY# mode) goes high, SR[7,6] (erase-suspend) SR[7,2] (program-suspend). Note: Issuing Suspend command does change read mode device. device will Read Status Register mode from when erase program command first issued, unless read mode changed prior issuing Suspend command. commands allowed when device suspended. Table shows which device commands allowed during Program Suspend Erase Suspend. Table Valid Commands During Suspend (Sheet
Device Command Program Suspend Erase Suspend
Configuration Read Array Read Status Register Clear Status Register Read Device Information Query Word Program Buffered Program Block Erase Program Suspend Erase Suspend Program/Erase Resume
Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed
Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed
Table Valid Commands During Suspend (Sheet
Device Command Program Suspend Erase Suspend
Lock Block Unlock Block Program Register
Allowed Allowed Allowed
Allowed Allowed Allowed
During Suspend, array-read operations allowed blocks being erased programmed. block-erase under program-suspend allowed. However, word-program under erasesuspend allowed, suspended. This results simultaneous erase-suspend/ programsuspend condition, indicated SR[7,6,2] resume suspended program erase operation, issue Resume command device address. read mode device automatically changed Read Status Register. operation continues where left off, RY/BY# mode) goes low, respective Status Register bits cleared. When Resume command issued during simultaneous erase-suspend/ program-suspend condition, programming operation resumed first. Upon completion programming operation, Status Register should checked errors, cleared. resume command must issued again complete erase operation. Upon completion erase operation, Status Register should checked errors, cleared.
Status Signal (STS)
STATUS (STS) signal configured different states using Configuration command. Once signal been configured, remains that configuration until another Configuration command issued asserted low. Initially, signal defaults operation where RY/BY# indicates that busy. RY/BY# high indicates that state machine ready operation suspended. Table displays possible configurations.
Table Configuration Register
Setup Write Cycle Command Address Data
Confirm Write Cycle Address Data
Configuration
Device Address
00B8h
Device Address
Register Data
NOTES: case device (2x128), command sequence must repeated each base address case device (2x128), keep second cycle same address. (ie. toggle second cycle)
reconfigure STATUS (STS) signal other modes, Configuration command given followed desired configuration code. three alternate configurations pulse mode system interrupt described following paragraphs. these configurations, controls Erase Complete interrupt pulse, controls Program Complete interrupt pulse. Supplying 0x00 configuration code with Configuration command resets signal
default RY/BY# level mode. Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result SR.4 SR.5 being set. Note: Pulse mode supported Clear Lock Bits Lock commands
Table Configuration Coding Definitions
Pulse Program Complete Notes
Controls HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. Generates system interrupt pulse when flash device array completed block erase. Helpful reformatting blocks after file system free space reclamation "cleanup." supported this device. Generates system interrupts trigger servicing flash arrays when either erase program operations completed, when common interrupt service routine desired.
Pulse Erase Complete
Reserved
D[1:0] Configuration Codes
default, level mode; device ready indication pulse Erase Complete pulse Program Complete pulse Erase Program Complete
NOTES: When configured pulse modes, pulses with typical pulse width invalid configuration code will result both being set. Reserved bits invalid should ignored.
Security Protection
Intel® Embedded Flash Memory device offer both hardware software security features. Block lock operations, VPEN allow users implement various levels data protection.
9.7.1
Normal Block Locking
unique capability Flexible Block Locking (locked blocks remain locked upon reset power cycle): blocks unlocked factory. Blocks locked individually issuing Block Lock command sequence address within block. Once locked, blocks remain locked when power removed, when device reset.
locked blocks unlocked simultaneously issuing Clear Block Lock Bits command sequence device address. Locked blocks cannot erased programmed. Table summarizes command bus-cycles. Table Block Locking Command Bus-Cycles
Command Setup Write Cycle Address Data Confirm Write Cycle Address Data
Block Lock Clear Block Lock Bits
Block Address Device Address
0060h 0060h
Block Address Device Address
0001h 00D0h
After issuing Block Lock setup command Clear Block Lock Bits setup command, device's read mode automatically changed Read Status Register mode. After issuing confirm command, completion operation indicated RY/BY# mode) going high Blocks cannot locked unlocked while programming erasing, while device suspended. Reliable block lock unlock operations occur only when VPEN valid. When VPEN VPENLK, block lock-bits cannot changed. When lock-bit operation complete, should checked error. When clear lock-bit operation complete, should checked error. Errors bits must cleared using Clear Status Register command. Block lock-bit status determined first issuing Read Device Information command, then reading from <block base address> 02h. indicates lock status addressed block unlocked, locked).
9.7.2
Configurable Block Locking
unique features non-existent previous generations this product family, ability protect and/or secure user's system offering multiple level securities: Non-Volatile Temporary; Non-Volatile Semi-Permanently Non-Volatile Permanently. additional information collateral request, please contact your filed representative.
9.7.3
Protection Registers
includes 128-bit Protection Register (PR) that used increase security system design. example, number contained used "match" flash component with other system components such ASIC, hence preventing device substitution. 128-bits divided into 64-bit segments:
segment programmed Intel factory with unique unalterable 64-bit number. other segment left blank customer designers program desired. Once
customer segment programmed, locked prevent further programming.
9.7.4
Reading Protection Register
Protection Register read Identification Read mode. device switched this mode issuing Read Identifier command (0090h). Once this mode, read cycles from addresses shown Table Table retrieve specified information. return Read Array mode, write Read Array command (00FFh).
9.7.5
Programming Protection Register
Protection Register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide configuration eight bits time byte-wide configuration. First write Protection Program Setup command, 00C0h. next write device will latch address data program specified location. allowable addresses shown Table "Word-Wide Protection Register Addressing" page Table "Byte-Wide Protection Register Addressing" page Figure "Protection Register Programming Flowchart" page attempt address Protection Program commands outside defined address space will result Status Register error (SR.4 will set). Attempting program locked segment will result Status Register error (SR.4 SR.1 will set).
9.7.6
Locking Protection Register
user-programmable segment Protection Register lockable programming Protection Lock Register (PLR) this location programmed Intel factory protect unique device number. using Protection Program command program "0xFFFD" PLR. After these bits have been programmed, further changes made values stored Protection Register. Protection Program commands locked section will result Status Register error (SR.4 SR.1 will set). lockout state reversible.
Figure Protection Register Memory
Word Address
0x88 0x85 0x84 0x81
A[24:1]: Mbit A[23:1]: Mbit
A[22:1]: Mbit A[21:1]: Mbit
64-bit Segment (User-Programmable) 128-Bit Protection Register 64-bit Segment (Factory-Programmed) Lock Register
0x80
NOTE: used mode when accessing protection register map. Table addressing. mode used, Table addressing.
Table Word-Wide Protection Register Addressing
Word
LOCK
Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register (i.e., A[MAX:9]
Table Byte-Wide Protection Register Addressing
Byte
LOCK LOCK
Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A[MAX:9]
9.7.7
VPP/ VPEN Protection
When it's necessary protect entire array, global protection achieved using hardware mechanism. using VPEN. Whenever valid voltage present VPEN, blocks within main flash array erased programmed. grounding VPEN, blocks within main array cannot altered attempts program erase blocks will fail resulting setting appropriate error Status Register. holding VPEN low, absolute write protection blocks array achieved.
Appendix Device Command Codes
complete definition device operations refer Section 8.4, "Device Commands" page list applicable commands included here more time conveninece. Table Command Operations
Setup Write Cycle Command Address Data Address Data Confirm Write Cycle
Program Enhanced Configuration Register
Registers
Register Data Device Address Device Address Device Address Device Address Device Address Device Address Device Address Device Address Word Address Device Address Device Address Device Address Block Address Block Address
0060h 00C0h 0050h 00B8h 00FFh 0070h 0090h 0098h 0040h/ 0010h 00E8h 0020h 00B0h 00D0h 0060h 0060h
Register Data Register Offset -Device Address Device Address Block Address -Block Address Block Address
0004h Register Data -Array Data 00D0h 00D0h -0001h 00D0h
Program Register Clear Status Register Program Configuration Register Read Array Read Status Register Read Identifier Codes (Read Device Information) Query Word/Byte Program Buffered Program Block Erase Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block
Security
Program Erase
Read Modes
Appendix Codes
Table Read Identifier Codes
Code Address Data
32-Mbit Device Code 64-Mbit 128-Mbit
00001 00001 00001
0016 0017 0018
Appendix Flow Charts
Write Buffer
Figure Write Buffer Flowchart
Start
Setup Write 0xE8 Block Address
Check Buffer Status Perform read operation Read Ready Status signal
Word Count Address block address Data word count minus (Valid range 0x00 to0x1F)
Load Buffer Fill write buffer word count Address within buffer range Data user data
Confirm Write 0xD0 Block address
Read Status Register (SR)
Full Status Register Check desired)
Status Register
Figure Status Register Flowchart
Start
Command Cycle Issue Status Register Command Address address Data 0x70
Data Cycle Read Status Register SR[7:0]
Set/Reset
Erase Suspend Suspend/Resume Flowchart
Program Suspend Suspend/Resume Flowchart
Error Command Sequence
Error Erase Failure
Error Program Failure
Reset user Clear Status Register Command
Error PENLK
Error Block Locked
Byte/Word Programming
Figure Byte/Word Program Flowchart
Start Write 40H, Address Write Data Address Read Status Register Full Status Check Desired Byte/Word Program Complete
Operation Write Write Read (Note Standby
Command Setup Byte/ Word Program Byte/Word Program
Comments Data Addr Location Programmed Data Data Programmed Addr Location Programmed Status Register Data Check SR.7 Ready Busy
SR.7
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program operation, after sequence programming operations. Write after last program operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4 Byte/Word Program Successful Programming Error Device Protect Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Detect Block Lock-Bit Only required systems implemeting lock-bit configuration. Check SR.4 Programming Error
Voltage Range Error
Standby
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Suspend/Resume
Figure Program Suspend/Resume Flowchart
Start Operation Write Write Read Command Program Suspend Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Programming Suspended Programming Completed Read Array Data Addr Read array locations other than that being programmed. Program Resume Data Addr
Read Status Register
Standby
SR.7
Standby
Write SR.2 Write Programming Completed Write Read
Read Data Array
Done Reading Write Write
Programming Resumed
Read Array Data
Block Erase
Figure Block Erase Flowchart
Start Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note Command Erase Block Erase Confirm Comments Data Addr Block Address Data Addr Block Address Status register data With device enabled, updates Addr Check SR.7 Ready Busy
Read
Write Confirm Block Address
Standby
Erase Confirm byte must follow Erase Setup. This device does support erase queuing. Please Application note AP-646 software erase queuing compatibility. Full status check done after erase write sequences complete. Write after last operation reset device read array mode. Suspend Erase Loop
Read Status Register
SR.7
Suspend Erase
Full Status Check Desired
Erase Flash Block(s) Complete
Block Erase Suspend/Resume
Figure Block Erase Suspend/Resume Flowchart
Start Operation Write Write Read
Command Erase Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Read Status Register
Standby
SR.7
Standby
Write SR.6 Read Read Program? Read Array Data Done? Write Write Program Loop Program Block Erase Completed
Erase Resume
Data Addr
Block Erase Resumed
Read Array Data
Block Locking
Figure Block Lock-Bit Flowchart
Start Write 60H, Block Address Write 01H, Block Address Read Status Register
Operation Write
Command Block Lock-Bit Setup Block Lock-Bit Confirm
Comments Data Addr =Block Address Data Addr Block Address Status Register Data Check SR.7 Ready Busy
Write
Read
Standby
SR.7 Full Status Check Desired Lock-Bit Complete
Repeat subsequent lock-bit operations. Full status check done after each lock-bit operation after sequence lock-bit operations. Write after last lock-bit operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.4 Lock-Bit Successful Lock-Bit Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.4 Lock-Bit Error
Command Sequence Error
Standby
SR.5, SR.4 SR.3 only cleared Clear Status Register command, cases where multiple lock-bits before full status checked. error detected, clear status register before attempting retry other error recovery.
Unlock Block
Figure Clear Lock-Bit Flowchart
Start
Operation Write
Command Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Comments Data Addr Data Addr Status Register Data Check SR.7 Ready Busy
Write
Write
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired Clear Block Lock-Bits Complete
Write after clear lock-bits operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Command Sequence Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.5 Clear Block Lock-Bits Error
Standby
SR.5, SR.4, SR.3 only cleared Clear Status Register command. error detected, clear status register before attempting retry other error recovery.
Protection Register Programming
Figure Protection Register Programming Flowchart
Start Write (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Read
Standby
SR.7 Full Status Check Desired Program Complete
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 SR.1, SR.4 VPEN Range Error
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.1, SR.4
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine. SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
Appendix Common Flash Interface
Common Flash Interface(CFI) specification outlines device host system software interrogation handshake which allows specific vendor-specified software algorithms used entire families devices. This allows device independent, JEDEC ID-independent, forwardand backward-compatible software support specified flash device families. allows flash vendors standardize their existing interfaces long-term compatibility. This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (D[7:0]) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (D[7:0]) high byte (D[15:8]). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
Table Summary Query Structure Output Function Device Mode
Device Type/ Mode Query start location maximum device width addresses Query data with maximum device width addressing Offset Code ASCII Value Query data with byte addressing Offset Code ASCII Value
device mode device mode
0051 0052 0059 N/A(1)
N/A(1)
"Null"
NOTE: system must drive lowest order addresses access device's array data when device configured mode. Therefore, word addressing, where these lower addresses toggled system, "Not Applicable" x8-configured devices.
Table Example Query Structure Output x16- x8-Capable Device
Word Addressing Offset A15-A0 Code D15-D0 Value Offset A7-A0 Byte Addressing Code D7-D0 Value
0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h
0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI
PrVendor PrVendor TblAdr AltVendor
P_IDLO P_IDLO P_IDHI
PrVendor
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. AP-646 Common Flash Interface (CFI) Command Sets (order number 292204) full description CFI. following sections describe Query structure sub-sections detail.
Table Query Structure
Offset Sub-Section Name Description Notes
(BA+2)h(2) 04-0Fh
P(3)
Manufacturer Code Device Code Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Block-Specific Information Reserved Vendor-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
Block Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations.
Table Block Status Register
Offset Length Description Address Value
(BA+2)h
BA+2: (bit 1-15): NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode).
Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked 1-15: Reserved Future
BA+2: BA+2:
(bit
Query Identification String
Query Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table Identification (Sheet
Offset Length Description Add. Code Value
Query-unique ASCII string "QRY" Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code.
Table Identification (Sheet
Offset Length Description Add. Code Value
0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
System Interface Information
following device information optimize system interface software.
Table System Interface Information
Offset Length Description Add. Code Value
logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
1024
Device Geometry Definition
This field provides critical details flash device geometry.
Table Device Geometry Definition
Offset Length Description Code Table Below
such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes
Device Geometry Definition
Address Mbit Mbit Mbit
Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
Table Primary Vendor-Specific Extended Query
Offset(1) Length Description (Optional Flash Features Commands) Add. Code Value
(P+0)h (P+1)h (P+2)h (P+3)h (P+4)h
Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant Individual block locking supported Protection bits supported Page-mode read supported Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block Status Register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts
(P+5)h (P+6)h (P+7)h (P+8)h
1(1)
Yes(1)
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
NOTE: Future devices support described "Legacy Lock/Unlock" function. Thus would have value "0."
Table Protection Register Information
Offset(1) Length Description (Optional Flash Features Commands) Add. Code Value
(P+E)h
(P+F)h (P+10)h (P+11)h (P+12)h
Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) protection register bytes. Some pre-programmed with device-unique serial numbers. Others userprogrammable. Bits 0-15 point protection register lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes
8bytes 8bytes
NOTE: variable pointer which defined offset 15h.
Table Burst Read Information
Offset(1) Length Description (Optional Flash Features Commands) Add. Code Value
(P+13)h
(P+14)h
(P+15)h NOTE: variable pointer which defined offset 15h.
Page Mode Read capability bits such that value represents number read-page bytes. offset device word width determine page-mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability. Reserved future
byte
Appendix Additional Information
Order Number
Document/Tool Intel® StrataFlashMemory (J3); 28F128J3, 28F640J3, 28F320J3 Specification Update Intel® Persistent Storage Manager (IPSM) User's Guide Software Manual Intel® Flash Data Integrator (FDI) User's Guide Software Manual Volt Intel® StrataFlashMemoryI28F320J5 28F640J5 datasheet AP-646 Common Flash Interface (CFI) Command Sets Intel® Wireless Communications Computing Package User's Guide
298130 298136 297833 290606 292204 253418
Call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel home page http://www.intel.com technical documentation tools. most current information Intel® Embedded Flash Memory visit http://
Appendix Ordering Information
Figure Decoder:Intel® Embedded Flash Memory Family
Package
56-Lead TSOP (J3C, 803) Pb-Free 56-TSOP 64-Ball Easy 64-Ball Pb-Free Easy
Access Speed Intel® 0.13 micron lithography Voltage (Vcc/VPEN) Product Family Intel® Embedded Flash Memory
Product line designator Intel® Flash Products
Device Density x8/x16 (128 Mbit) x8/x16 Mbit) x8/x16 Mbit)
Table Order Information: Intel® Embedded Flash Memory Family
56-Lead TSOP 64-Ball Easy
TE28F128J3D-75 TE28F640J3D-75 TE28F320J3D-75 JS28F128J3D-75 JS28F640J3D-75 JS28F320J3D-75
RC28F128J3D-75 RC28F640J3D-75 RC28F320J3D-75 PC28F128J3D-75 PC28F640J3D-75 PC28F320J3D-75
Introduction
Nomenclature Acronyms Conventions
Functional Overview
Block Diagram Memory
Package Information
56-Lead TSOP Package Easy Package.
Ballouts Signal Descriptions.15
Easy Ballout (32/64/128 Mbit). 56-Lead TSOP Package Pinout (32/64/128 Mbit) Signal Descriptions.
Maximum Ratings Operating Conditions
Absolute Maximum Ratings. Operating Conditions. Power Up/Down 5.3.1 Power-Up/Down Characteristics 5.3.2 Power Supply Decoupling Reset
Electrical Characteristics
Current Specifications Voltage specifications Capacitance
Characteristics
Read Specifications. Write Specifications. Program, Erase, Block-Lock Specifications Reset Specifications. Test Conditions
Interface
Reads. 8.1.1 Asynchronous Page Mode Read. 8.1.1.1 Enhanced Configuration Register (ECR) 8.1.2 Output Disable. Writes Standby 8.3.1 Reset/Power-Down Device Commands
Flash Operations
Status Register. 9.1.1 Clearing Status Register
Read Operations 9.2.1 Read Array 9.2.2 Read Status Register 9.2.3 Read Device Information.40 9.2.4 Query.41 Programming Operations 9.3.1 Single-Word/Byte Programming.41 9.3.2 Buffered Programming Block Erase Operations Suspend Resume.44 Status Signal (STS).45 Security Protection 9.7.1 Normal Block Locking 9.7.2 Configurable Block Locking.47 9.7.3 Protection Registers 9.7.4 Reading Protection Register 9.7.5 Programming Protection Register.48 9.7.6 Locking Protection Register.48 9.7.7 VPP/ VPEN Protection
Appendix Appendix Appendix
Device Command Codes Codes Flow Charts
Write Buffer Status Register.54 Byte/Word Programming Program Suspend/Resume.56 Block Erase Block Erase Suspend/Resume Block Locking Unlock Block Protection Register Programming.61 Query Structure Overview Block Status Register Query Identification String System Interface Information Device Geometry Definition Primary-Vendor Specific Extended Query Table
Appendix
Common Flash Interface
Appendix Appendix
Additional Information Ordering Information.
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