Video Encoder with Adaptive Flicker Filtering HDTV Output Conexan
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CX25870/871
Video Encoder with Adaptive Flicker Filtering HDTV Output
Conexant's CX25870/871 specifically designed meet system requirements next-generation desktop PCs, notebook PCs, game consoles set-top boxes. With software-forward compatibility Bt868/869, manufacturers quickly bring market solutions that support adaptive flicker filtering, ATSC High-Definition Television (HDTV) output, resolutions from (minimum) 1024 (maximum). Adaptive flicker filtering Conexant technology which encoder looks characteristics video content pixel-by-pixel basis automatically determines optimal amount flicker filtering required. end-user wants work spreadsheet while watching movie window, both text-intensive application requiring flicker filtering movie requiring very little flicker filtering look their best. amount flicker filtering overscan compensation entirely flexible. CX25870/871 also provides 3-wire analog YPRPB HDTV output. While encoder HDTV output mode, device will automatically insert horizontal tri-level synchronization pulses vertical synchronization broad pulses. CX25870/871 compliant with EIA770-3, SMPTE 274M/293M/296M standards supports ATSC HDTV resolutions including 480p, 720p, 1080i. worldwide standard definition outputs supported, including NTSC-M America, Taiwan), NTSC-J (Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60 (China) SECAM. CX25870 CX25871 functionally identical, except CX25871 output standard definition video with Macrovision Level 7.1.L1 copy protection capability.
Distinguishing Features
HDTV Output Mode (patents pending) Compliant with EIA770-3 SMPTE274M/293M/296M standards Automatic tri-level sync generation Component (YPRPB) HDTV outputs Direct YPRPB output from progressive graphics video 1080i, 720p, 480p ATSC resolutions Software register forward-compatibility with Bt868/869 Ability accept many different input data formats: 15/16/24-bit multiplexed nonmultiplexed 16-bit 4:2:2 24-bit 4:4:4 YCrCb multiplexed nonmultiplexed Flexible pixel ordering with various alternate formats Worldwide video output support: NTSC-M, 4.43, PAL-B, SECAM Interlaced noninterlaced outputs S-Video output (simultaneous with composite NTSC, PAL, SECAM) SCART output Europe composite video EN50-049 933-1 compliant 5-Line vertical filtering scaling overscan compensation flicker reduction Adaptive Flicker Filtering enhanced image peaking filters text sharpness (patents pending) CCIR601/ITU-RBT.601 (i.e., 480i) CCIR656 compatible input modes Luma chroma comb filtering 10-bit DACs Programmable power management Master, pseudo-master slave timing operation Auto detection autoconfiguration modes Wide-Screen Signaling (WSS) support variable clock rates Adheres EIAJ CPR-1024 ITU-R TST.1119-1 standards Full register readback capability operation with scalable voltage graphic controller interface from Buffered crystal clock output Component analog output Colorstream (EIA 770.2) Super Colorstream component video outputs Macrovision 7.1.L1 copy protection (CX25871) Compact 80-pin PQFP package
Functional Block Diagram
Color Space Conversion
P[23:0]
Input DEMUX
Flicker Filter/ Scaler
FIFO
FSADJUST
HSYNC* VSYNC* BLANK* FIELD ALTADDR
Timing Internal Reference Serial Interface Video Encoder Color Space Conversion Internal Clocks 10-Bit 10-Bit 10-Bit 10-Bit COMP VREF DACA DACB DACC DACD VBIAS Clock Generation BIAS CLKO CLKI
RESET* SLEEP SLAVE
XTALIN XTALOUT XTAL
XTL_BFO
Data Sheet
100381B September 2001
100381B
Conexant
Ordering Information
Model Number CX25870 CX25871(1)
NOTE(S):
Package 80-pin PQFP 80-pin PQFP
Ambient Temperature Range
Macrovision 7.1.L1 compliant (customer must possess Macrovision license purchase CX25871).
2001, Conexant Systems, Inc. Rights Reserved.
Information this document provided connection with Conexant Systems, Inc. ("Conexant") products. These materials provided Conexant service customers used informational purposes only. Conexant assumes responsibility errors omissions these materials. Conexant make changes specifications product descriptions time, without notice. Conexant makes commitment update information shall have responsibility whatsoever conflicts incompatibilities arising from future changes specifications product descriptions. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Conexant's Terms Conditions Sale such products, Conexant assumes liability whatsoever. THESE MATERIALS PROVIDED WITHOUT WARRANTY KIND, EITHER EXPRESS IMPLIED, RELATING SALE AND/OR CONEXANT PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, CONSEQUENTIAL INCIDENTAL DAMAGES, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES WARRANT ACCURACY COMPLETENESS INFORMATION, TEXT, GRAPHICS OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL LIABLE SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES LOST PROFITS, WHICH RESULT FROM THESE MATERIALS. Conexant products intended medical, lifesaving life sustaining applications. Conexant customers using selling Conexant products such applications their risk agree fully indemnify Conexant damages resulting from such improper sale. following trademarks Conexant Systems, Inc.: ConexantTM, Conexant symbol, "What's Next Communications Technologies"TM. Product names services listed this publication identification purposes only, trademarks third parties. Third-party brands names property their respective owners. additional disclaimer information, please consult Conexant's Legal Information posted www.conexant.com, which incorporated reference. Reader Response: Conexant strives produce quality documentation welcomes your feedback. Please send comments suggestions tech.pubs@conexant.com. technical questions, contact your local Conexant sales office field applications engineer.
100381B
Conexant
100381B
Conexant
Table Contents
List Figures List Tables. Functional Description
Descriptions Controller Programmability Frequency Requirement Device Description 1-10 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 Overview 1-10 Serial Interface 1-10 Voltage Graphics Interface 1-11 Reset 1-11 Device Initialization 1-12 Clocking Timing Generation 1-13 1.3.6.1 Clocking Mode 1-14 Master, Pseudo-Master, Slave Interfaces. 1-17 1.3.7.1 Master Interface 1-17 1.3.7.2 Reason BLANK* 1-18 1.3.7.3 Pseudo-Master Interface 1-18 1.3.7.4 Slave Interface 1-19 1.3.7.5 Slave Interface Without Crystal 1-20 Autoconfiguration Interface Bits 1-21 Adaptations Clock-Limited Master Devices 1-25 Input Formats 1-26 Input Pixel Timing 1-27 YCrCb Inputs (For Standard Outputs) 1-27 Inputs (For Standard Outputs) 1-29 Input Pixel Horizontal Sync 1-29 Input Pixel Vertical Sync 1-30 Input Pixel Blanking 1-30 Overscan Compensation 1-31 Standard Flicker Filtering 1-35 Adaptive Flicker Filter 1-36 Registers Involved Process 1-39 Output Modes 1-40
1.3.8 1.3.9 1.3.10 1.3.11 1.3.12 1.3.13 1.3.14 1.3.15 1.3.16 1.3.17 1.3.18 1.3.19 1.3.20 1.3.21
100381B
Conexant
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology 1.3.22 1.3.23 1.3.24 1.3.25 1.3.26 1.3.27 1.3.28 1.3.29 1.3.30 1.3.31 1.3.32 1.3.33 1.3.34 1.3.35 1.3.36 1.3.37 1.3.38 1.3.39 Analog Horizontal Sync 1-40 Analog Vertical Sync. 1-41 Analog Video Blanking 1-41 Video Output Standards Supported 1-41 Subcarrier Generation 1-51 Subcarrier Phase Reset/Offset 1-51 Burst Generation 1-52 Video Amplitude Scaling SINX/X Compensation 1-52 Chrominance Disable 1-52 FIELD Output 1-53 Buffered Crystal Clock Output 1-55 Noninterlaced Output 1-55 Closed Captioning (CC) 1-56 Wide Screen Signaling (WSS) 1-57 Chrominance Luminance Processing 1-58 Color Blue Field Generation 1-61 CCIR656 Mode Operation 1-63 CCIR601 Mode Operation Playback 1-65 1.3.39.1 CCIR601 Data In/NTSC 1-65 1.3.39.2 CCIR601 Data In/PAL 1-66 1.3.39.3 VGA- Compatible Data In/NTSC 1-66 SECAM Output 1-68 Macrovision Copy Protection 1-74 HDTV Output Mode 1-75 SCART Output 1-75 Interlaced Standard Definition Analog Component Video Outputs 1-79 VGA(RGB)-DAC Output Operation 1-84 Auto-Detection Procedures 1-87 Sleep/Power Management 1-89
1.3.40 1.3.41 1.3.42 1.3.43 1.3.44 1.3.45 1.3.46 1.3.47
Internal Registers
Essential Registers Device Address Writing Registers Reading Registers
Board Considerations
Component Placement Power Ground Planes Recommended Schematics Layout CX25870/871 Decoupling 3.4.1 3.4.2 3.4.3 Device Decoupling Power Supply Decoupling COMP Decoupling
Conexant
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology 3.4.4 3.4.5 3.5.1 3.5.2 3.6.1 VREF Decoupling VBIAS Decoupling Digital Signal Interconnect 3-10 Analog Signal Interconnect 3-10 Changes Required Accommodate CX25870/871 Bt868/869-Designs 3-11 3.6.1.1 Software 3-11 3.6.1.2 Hardware 3-12 Programmable Video Adjustment Controls 3-15 3.6.2.1 Contrast 3-15 3.6.2.2 Saturation 3-16 3.6.2.3 Brightness 3-16 3.6.2.4 3-17 3.6.2.5 Sharpness 3-17 3.6.2.6 Crawl 3-17 3.6.2.7 Standard Adaptive Flicker Filter 3-18 3.6.2.8 Position 3-20 3.6.2.9 Size 3-21 System Block Diagrams 3-26 Electrostatic Discharge Latchup Considerations 3-27 Clock Subcarrier Stability 3-28 Filtering Radio Frequency Modulator Connection 3-29
Signal Interconnect 3-10
Applications Information 3-11
3.6.2
3.6.3 3.6.4 3.6.5 3.6.6
CX870EVK Evaluation Kit. 3-31 Serial Interface 3-33 3.8.1 Data Transfer Serial Interface 3-33
Parametric Information
Electrical Parameters Electrical Parameters Mechanical Drawing 80-Pin PQFP 4-17
Appendix Scaling Timing Register Calculations Appendix Approved Crystal Vendors Appendix Autoconfiguration Mode Register Values Details Appendix Closed Caption Pseudo Code Appendix CX25870/871 HDTV Output Mode
Introduction E.1.1 E.1.2 Allowable Interfaces HDTV Output Mode Interface Functionality HDTV Output Mode
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology E.1.3 E.1.4 E.1.5 E.1.6 E.1.7 E.1.8 E.1.9 E.1.10 Interface Timing Between HDTV Source Device (Master) CX25870/ CX25871 (Timing Slave) Automatic Trilevel Sync Generation Allowable Resolutions 720p Support with Character Clock Based Data Masters Automatic Insertion Broad Pulses HDTV Output Mode Register Definitions Color Space Conversion Functionality Support Analog YPBPR Component Video Outputs E-11 Timing Diagrams HDTV Output Mode E-11
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
List Figures
List Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 1-21. Figure 1-22. Figure 1-23. Figure 1-24. Figure 1-25. Figure 1-26. Figure 1-27. Figure 1-28. Figure 1-29. Figure 1-30. Figure 1-31. Figure 1-32. Figure 1-33. Figure 1-34. Figure 1-35. Figure 1-36. Pinout Diagram CX25870/871 Flicker Filter Control Diagram CX25870/871 Encoder Core Block Diagram Allowable Overscan Compensation Ratios Dual Display, 800x600 Input/NTSC Output 1-15 Operating CX25870/871 Master Interface 1-17 Operating CX25870/871 Pseudo-Master Interface 1-18 Operating CX25870/871 Slave Interface 1-19 Decimation Filter Fs=27 MHz. 1-28 Windows Desktop Image From Encoder Without Overscan Compensation. 1-33 Windows Desktop Image From CX25870 With Overscan Compensation 1-34 Interlaced 525-Line (NTSC) Video Timing 1-43 Interlaced 525-Line (PAL-M) Video Timing 1-44 Interlaced 625-Line (PAL-B, Video Timing (Fields 1-4) 1-45 Interlaced 625-Line (PAL-B, Video Timing (Fields 5-8) 1-46 Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4) 1-47 Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8) 1-48 Noninterlaced 262-Line (NTSC) Video Timing. 1-49 Noninterlaced 262-Line (PAL-M) Video Timing 1-49 Noninterlaced 312-Line (PAL-B, Video Timing. 1-49 Interlaced 625-Line (SECAM-B, Video Timing (Fields 1-4) 1-50 FIELD Output Timing Diagram (NTSC-M, 4.43). 1-53 FIELD Output Timing Diagram (PAL-B, 1-54 Typical Analog Waveform (NTSC). 1-57 Luminance Upsampling Filter 1-59 Text Sharpness (Luminance Upsampling) Filter with Peaking Options 1-59 Close-Up Text Sharpness (Luminance Upsampling )Filter with Peaking Reduction Options 1-59 Text Sharpness (Luminance Peaking) Filter Options 1-60 Chrominance Filter (CHROMA_BW default 1-60 Chrominance Wide Bandwidth Filter (CHROMA_BW 1-60 SECAM High Frequency Pre-emphasis Filter 1-61 Composite S-Video Format (Internal Colorbars). 1-62 CX25870/871 Connection CCIR656-Compatible Master Device 1-63 Playback Utilizing Graphics Controller Color-Space Progressive Scan Conversion 1-67 CX25870 Driving Type SCART Connector 50-049 933-1 Compliant) 1-78 CX25870 Driving Type SCART Connector (Y/C SCART Compliant). 1-79 Component Video Signals using 100/0/100/0 Color Bars Digital Input Signal (Courtesy- EIA-770.2-A standard, page EIA-770.1 standard) 1-81
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List Figures
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-37. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure A-1. Figure A-2. Figure A-3. Figure A-4.
Filterless Outputs (RGB)-DAC Output Operation 1-86 Power Plane Illustration Connection Diagram Output Filters Other Passive Components/Standard Definition Only Connection Diagram Output Filters Other Passive Components/Standard HDTV CX25870/871 Recommended Layout Connection with Master Device Standard Definition Only CX25870/871 V/1.8 Recommended Layout Connection with Master Device Standard Definition Only Conexant Recommended CX25870/871 3-15 CX25870/871 Autoconfiguration Modes 640x480 NTSC Desktop Resolutions 3-22 CX25870/871 Autoconfiguration Modes 40x480 PAL-BDGHI Desktop Resolutions 3-22 CX25870/871 Autoconfiguration Modes NTSC Desktop Resolutions 3-23 CX25870/871 Autoconfiguration Modes PAL-BDGHI Desktop Resolutions 3-23 CX25870/871 Autoconfiguration Modes 1024 NTSC Desktop Resolutions 3-24 CX25870/871 Autoconfiguration Modes 1024 PAL-BDGHI Desktop Resolutions 3-24 Direction-less Size Control 3-25 System Block Diagram Desktop/Portable with 3-26 System Block Diagram Graphics Card with 3-27 SID/SIC Diagram 3-34 Timing Details Interfaces Master Interface Timing Relationship/Noninterlaced RGB/YCrCb Input Pseudo-Master Interface Timing Relationship Active Line/Noninterlaced Input Pseudo-Master Timing Relationship Blank Line/Noninterlaced RGB/YCrCb Input. 4-10 Slave Interface Timing Relationship/Noninterlaced RGB/YCrCb Input 4-11 Slave Interface Timing Relationship/Interlaced Nonmultiplexed Input (FLD_MODE Default) 4-12 Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE 4-13 Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE 4-14 HDTV Output Horizontal Timing Details: 1080i 4-15 HDTV Output Horizontal Timing Details: 720p. 4-16 80-Pin PQFP Package Diagram 4-17 Allowable Overscan Compensation Ratios Dual Display, 640x480 Input, NTSC Output with Clock HBlank Period Allowable Overscan Compensation Ratios Dual Display, 640x480 Input, PAL-BDGHI Output with Clock HBlank Period Allowable Overscan Compensation Ratios Dual Display, 800x600 Input, NTSC Output Allowable Overscan Compensation Ratios Dual Display, 800x600 Input, PAL-BDGHI Output, Standard Clocking Mode
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology Figure A-5. Figure A-6. Figure A-7. Figure A-8. Figure E-1. Figure E-2. Figure E-3. Figure E-4.
List Figures
Figure E-5.
Figure E-6. Figure E-7. Figure E-8.
Allowable Overscan Compensation Ratios Dual Display, 800x600 Input, NTSC Output Clocking Mode Allowable Overscan Compensation Ratios Dual Display, 800x600 Input, PAL-BDGHI Output Clocking Mode Allowable Overscan Compensation Ratios Dual Display, 1024x768 Input, NTSC Output A-10 Allowable Overscan Compensation Ratios Dual Display, 1024x768 Input, PAL-BDGHI Output A-11 CX25870/871's Pseudo-Master Interface with Graphics Controller Timing Master CX25870/871's Slave Interface with Graphics Controller Timing Master Typical Trilevel Sync Provided CX25870/871 Proper Interface Timing Between HDTV Source Device (Master) CX25870/871 (Timing Slave): Active Line 1080i 720p ATSC Format (RASTER_SEL[1:0] 10), Analog Outputs E-12 Proper Interface Timing Between HDTV Source Device (Master) CX25870/871 (Timing Slave): Active Line 1080i 720p ATSC Format (RASTER_SEL[1:0] Analog Outputs E-13 Proper Interface Timing Between HDTV Source Device (Master) CX25870/871 (Timing Slave): Broad Pulse Line 1080i ATSC Format (RASTER_SEL[1:0] Field E-14 Proper Interface Timing Between HDTV Source Device (Master) CX25870/871 (Timing Slave): Successive Active Fields 1080i ATSC Format (RASTER_SEL[1:0] E-15 Proper Interface Timing Between HDTV Source Device (Master) CX25870/871 (Timing Slave): Broad Pulse Line 720p ATSC Format (RASTER_SEL[1:0] E-16
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List Figures
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
List Tables
List Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Table 1-10. Table 1-11. Table 1-12. Table 1-13. Table 1-14. Table 1-15. Table 1-16. Table 1-17. Table 1-18. Table 1-19. Table 1-20. Table 1-21. Table 1-22. Table 1-23. Table 1-24. Table 1-25. Table 1-26. Table 1-27. Table 1-28. Table 1-29. Table 1-30. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. Assignments Data Assignments Multiplexed Input Formats Data Assignments Nonmultiplexed Input Formats Maximum Programmability Frequency Requirements Autoconfiguration Solutions that Utilize Clocking Mode 1-16 Master Interface without BLANK* Signal (Default Immediately after Autoconfiguration Command) 1-21 Master Interface with BLANK* Input CX25870/871 1-22 Pseudo-Master Interface without BLANK* Signal. 1-22 Pseudo-Master Interface with BLANK* Input CX25870/871. 1-23 Slave Interface without BLANK* Signal 1-23 Slave Interface with BLANK* Input CX25870/871 1-24 Adjustment CX25870/871 Registers. 1-25 Adjustment PLL_INT PLL_FRACT Registers 1-26 Summary Allowable BLANK* Signal Directions Interface. 1-31 Optimal Adaptive Standard Flicker Filter Settings Common Applications. 1-38 VGA/CRTC Registers Involved Process 1-39 Important Settings Various Video Outputs 1-42 Composite Luminance Amplitude. 1-62 Composite Chrominance Magnitude. 1-63 Register Values 640x480 800x600 1024x768 SECAM-L 1-69 Vital SECAM Bitsettings-Register 0xA2 1-72 SECAM Specific Registers. 1-74 Serial Writes Required Switch CX25870/871 into SCART Output Operation 1-76 Default SCART Outgoing Signal Assignments 1-77 CX25870 SCART Outputs Different SCART Standards. 1-78 Common Registers Required Switch CX25870/25871 into EIA-770.2-A- EIA-770.1-Compliant Component Video Outputs 1-82 Unique Registers Required Switch CX25870/25871 into EIA-770.2-A- Compliant Component Video Outputs 1-82 Serial Writes Required Switch CX25870/871 into VGA/DAC Output Operation 1-84 Serial Writes Required Remove Bilevel Syncs from VGA/DAC Outputs 1-85 ESTATUS[1:0] Read-back Map. 1-88 Register Indicates Read-Only Register) Serial Address Configuration. Read-Only Registers Data Details Defined Read-Only Registers Programming Detail Typical Parts List Passive Components.
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List Tables
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 3-2. Table 3-3. Table 3-4. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table A-15. Table A-16. Table A-17. Table A-18. Table A-19. Table A-20. Table A-21. Table A-22. Table A-23.
Relative Register CX25870/871 3-11 Hardware Modifications Bt868/869-based Required Accommodate CX25870/871 3-12 CX25870 Optimal Adaptive Flicker Filter Settings 3-19 Recommended Operating Condition Absolute Maximum Rating Characteristics CX25870/871. Characteristics CX25870/871 Target Video Parameters Standard Definition Output Formats Parameters Supported Standard Definition Video Output Formats Constant Values Dependent Encoding Mode Overscan Values, NTSC, Pixel-Based Controller, 1-Pixel Resolution, HBlank. A-12 Overscan Values, NTSC, Character Clock-Based Controller, 8-Pixel Resolution, HBlank A-14 Overscan Values, NTSC, Character Clock-Based Controller, 9-Pixel Resolution, HBlank A-15 Overscan Values, PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, HBlank A-16 Overscan Values, PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, HBlank A-19 Overscan Values, PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, HBlank A-20 Overscan Values, NTSC, Pixel-Based Controller, 1-Pixel Resolution. A-21 Overscan Values, NTSC, Character Clock-Based Controller, 8-Pixel Resolution, 0-1.5 HBlank A-25 Overscan Values, NTSC, Character Clock-Based Controller, 9-Pixel Resolution, 0-3.0 HBlank A-26 Overscan Values NTSC, Pixel-Based Controller, 1-Pixel Resolution, Clocking Mode A-27 Overscan Values NTSC, Character Clocked-Based Controller, 8-Pixel Resolution, Clocking Mode A-31 Overscan Values NTSC, Character Clocked-Based Controller, 9-Pixel Resolution, Clocking Mode A-32 Overscan Values, PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >2.5 HBlank A-34 Overscan Values, PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution A-36 Overscan Values, PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution A-37 Overscan Values PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, Clocking Mode A-38 Overscan Values PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, Clocking Mode A-41 Overscan Values PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, Clocking Mode A-41 Overscan Values 1024 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 Hblank A-42 Overscan Values 1024 NTSC, Character Clock-Based Controller, 8Pixel Resolution, >1.50
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
List Tables
Table A-24. Table A-25. Table A-26. Table A-27. Table C-1. Table C-2. Table C-3. Table C-4. Table C-5. Table C-6. Table C-7. Table C-8. Table C-9. Table E-1. Table E-2. Table E-3. Table E-4. Table E-5. Table E-6.
HBlank A-46 Overscan Values 1024 NTSC, Character Clock-Based Controller, 9-Pixel Resolution A-47 Overscan Values 1024 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, Hblank A-49 1024 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution Hblank A-52 Overscan Values 1024 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution A-52 CX25870/871 Register Values Autoconfiguration Modes CX25870/871 Register Values Autoconfiguration Modes 5-10 CX25870/871 Register Values Autoconfiguration Modes 11-15 CX25870/871 Register Values Autoconfiguration Modes 16-21 CX25870/871 Register Values Autoconfiguration Modes 22-26 C-10 CX25870/871 Register Values Autoconfiguration Modes 27-30 C-12 CX25870/871 Register Values Autoconfiguration Modes 31-36 C-14 CX25870/871 Register Values Autoconfiguration Modes 37-42 C-16 CX25870/871 Register Values Autoconfiguration Modes 43-47 C-18 CX25870 Register Settings 24-Bit Multiplexed Y/PR/PB HDTV Out. Default State CX25870/871 Immediately After Switch into HDTV Output Mode CX25870/871 RASTER_SEL[1:0] functionality. CX25870/871 HDTV Supported Formats. Register HDTV-specific registers CX25870/871 Registers 0x2E 0x32 HDTV Output Mode Descriptions E-10
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List Tables
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Conexant
100381B
Functional Description
Descriptions
pinout diagram illustrated Figure 1-1. names, input/output assignments, numbers, descriptions listed Tables 1-1, 1-2, 1-3.
Figure 1-1. Pinout Diagram CX25870/871
VAA_X XTALOUT XTALIN VSS_X AGND_DAC DACD VAA_DACD DACA VAA_DACA DACB VAA_DACB DACC VAA_DACC AGND_DAC COMP VREF VBIAS FSADJUST AGND VAA_VREF
VAA_PLL AGND_PLL VDD_CO CLKO VSS_CO CLKI RESET* SLEEP SLAVE VDD_VREF ALTADDR VDD_SI VDD_SO VSS_SO VSS_SI
CX25870/871 80-pin PQFP
VDDL VSS/TEST BLANK* FIELD VSYNC* HSYNC* P[23] P[22] P[21] P[20] P[19] P[18] P[17] P[16] P[15] P[14]
XTL_BFO P[0] P[1] P[2] P[3] P[4] P[5] P[6] P[7] P[8] P[9] P[10] P[11] P[12] P[13]
100381_002
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Conexant
Functional Description
Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Aside from pins which connects within Bt868/869, CX25870/871 completely pin-to-pin compatible with Conexant's first generation encoder.
Table 1-1. Assignments Name
VAA_VREF AGND FSADJUST VBIAS
Description
Analog power. pins must connected together same plane prevent latchup. Analog ground. AGND pins must connected together same plane prevent latchup. Full-scale adjust control pin. resistor (RSET) connected between this controls full-scale output current analog outputs. bias voltage. ceramic capacitor must used bypass this GND. capacitor must close device possible keep lead lengths absolute minimum. Voltage reference pin. ceramic capacitor must used decouple this GND. decoupling capacitor must close device possible keep lead lengths absolute minimum. Compensation pin. ceramic capacitor must used bypass this VAA. capacitor must close device possible keep lead lengths absolute minimum. DACC Analog power. pins must connected together same plane prevent latchup. DACC Analog output. DACB Analog power. pins must connected together same plane prevent latchup. DACB Analog output. DACA Analog power. pins must connected together same plane prevent latchup. DACA Analog output. DACD analog power. pins must connected together same plane prevent latchup. DACD analog output. unused, DACD should left connect. Common Analog ground return. AGND pins must connected together same plane prevent latchup. Crystal oscillator ground pin. This should tied ground plane. crystal connected these pins. pixel clock output (CLKO) derived from these pins with PLL. XTALIN driven CMOS input pin. Internally, this CMOS inverter tying XTALOUT XTALIN. XTALOUT unused, should left connect. Crystal oscillator supply pin. This should tied power supply. Analog power PLL. pins must connected together same plane prevent latchup. Analog ground PLL. AGND pins must connected together same plane prevent latchup.
VREF
COMP
VAA_DACC DACC VAA_DACB DACB VAA_DACA DACA VAA_DACD DACD AGND_DAC VSS_X XTALIN XTALOUT
VDD_X VAA_PLL AGND_PLL
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-1. Assignments Name
VDD_CO CLKO VSS_CO CLKI
Functional Description
Descriptions
Description
Clock output supply pin. This should tied power supply. voltage infacing this should tied voltage supply. Pixel clock output (TTL compatible). This three-state CLKI provides encoder clock. Clock output ground pin. This should tied ground plane. Pixel clock input (TTL compatible). This used either encoder clock delayed version CLKO synchronized with pixel data input. Reset control input (TTL compatible). logical applied minimum CLKI clock cycles resets disables video timing (horizontal, vertical, subcarrier counters) start VSYNC first field resets serial interface registers. RESET* must logical 1(3.3 normal operation. Power-down control input (TTL compatible). logical configures device power-down mode. logical configures device normal operation. Slave/master mode select input (TTL compatible). logical configures device slave video timing operation. logical configures device master video timing operation. PAL/NTSC mode select input (TTL compatible). logical configures device video format Autoconfiguration Mode logical configures device NTSC video format Autoconfiguration Mode Input threshold adjustment. This should tied input swings VDDL/2 voltage input swings. Alternate slave address input (TTL compatible). logical configures device respond serial write address 0x88. logical configures device respond serial write address 0x8A. addition, serial reads address 0x89 (ALTADDR 0x8B (ALTADDR possible with this pin. Serial interface input supply pin. This should tied (3.3 Serial interface output supply pin. This should tied (3.3 Serial interface clock input (TTL compatible). Serial interface data input/output (TTL compatible). Data written read from device this serial bus. Serial interface input ground pin. This should tied ground plane. Serial interface input ground pin. This should tied ground plane. Digital power voltage interface. pins must connected together same plane prevent latchup. voltage interface, this should tied voltage supply. Test pin. Should tied normal operation. Composite blanking control (TTL compatible). This generated encoder supplied from graphics controller. internal blanking used, this used indicate control character clock edge. unused, BLANK* should tied high through pullup resistor.
RESET*
SLEEP SLAVE
VDD_VREF ALTADDR
VDD_SI VDD_SO VSS_SO VSS_SI VDDL
VSS/TEST BLANK*
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Conexant
Functional Description
Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-1. Assignments Name
FIELD
Description
Field control output (TTL compatible). FIELD transitions after rising edge CLK, clock cycles following falling HSYNC*. logical during fields logical during even fields. unused, FIELD should left connect. Vertical sync input/output (TTL compatible). output (timing master operation), VSYNC* output following rising edge CLK. input (timing slave operation), VSYNC* clocked rising edge CLK. Horizontal sync input/output (TTL compatible). output (timing master operation), HSYNC* output following rising edge CLK. input (timing slave operation), HSYNC* clocked rising edge CLK. Pixel inputs. Table 1-2. input data sampled both rising falling edge multiplexed modes, rising edge nonmultiplexed modes. higher index corresponds greater significance. Digital ground core logic. AGND pins must connected together same plane prevent latchup. Buffered crystal clock output. power-up, encoder will transmit signal frequency equal frequency crystal found between XTALIN/XTALOUT ports. Normally XTL_BFO output rate 13.500 MHz. unused, XTL_BFO should left connect. Digital power core logic. pins must connected together same plane prevent latchup.
VSYNC*
HSYNC*
P[23:21] P[20:14] P[13:0] XTL_BFO
34-32 29-23 18-5
Conexant
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-2. Data Assignments Multiplexed Input Formats Falling Edge CLKI IN_MODE[3:0] 0000 0010/0001 0101 16-bit YCrCb Mode
Functional Description
Descriptions
0100 24-bit YCrCb Mode
1000 Alternate 24-bit Mode
0110 Alternate 16-bit YCrCb Mode
1100 Alternate 24-bit YCrCb Mode
24-bit Mode
15/16-bit Mode
G5(1)
P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
Rising Edge CLKI
P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
NOTE(S):
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
ignored 15-bit Multiplexed Input Mode.
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Functional Description
Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-3. Data Assignments Nonmultiplexed Input Formats IN_MODE[3:0] 1010 1110 16-bit nonmux YCrCb
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
0011
0111 24-bit nonmux YCrCb
1011 Alternate 16-bit nonmux
1111 Alternate 24-bit nonmux YCrCb
16-bit nonmux
24-bit nonmux
P[23] P[22] P[21] P[20] P[19] P[18] P[17] P[16] P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
Conexant
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CX25870/871
Functional Description
Flicker-Free Video Encoder with Ultrascale Technology Controller Programmability Frequency Requirement
Controller Programmability Frequency Requirement
Programmability frequency requirements Graphics Controller/Data Master device defined Table most common input resolutions.
Table 1-4. Maximum Programmability Frequency Requirements Maximum Total Desktop Input Mode Pixels/HTOTAL
(3:2 mode) 1024 (3:2 mode) 1075 1075 1625 1625
Maximum Active Vsync Lines
Maximum Frequencies
Lines/VTOTAL
1068
Line (kHz)
39.860 49.450 49.630 63.776
Pixel (MHz)
31.563 39.997 59.063 75.750
Table contains maximum values dual display solutions that provide percent percent horizontal vertical overscan compensation. larger overscan compensation percentages, values would larger. maximum pixel frequency supported 53.333 standard clocking mode 80.000 clocking mode.
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Figure 1-2. Flicker Filter Control Diagram
Color Space Converter Flicker Filter/Scaler FIFO
ADPT_FF F_SELY[2:0] DIS_GMSHY DIS_GMUSHY DIS_YFLPF YCORING[2:0] Bypass Gain 15/16 Gain Gain Gain Gain Gain Gain Gain YLPF[1:0] YATTENUATE[2:0] Line Line Line Line Alt. Line Alt. Line Alt. Line Alt. Line ADPT_FF F_SELC[2:0] Line CLPF[1:0] Bypass Reserved Line Line Line Alt. Line Alt. Line Alt. Line Alt. Line Gain 15/16 Gain Gain Gain Gain Gain Gain Gain CATTENUATE[2:0] Luma, Horizontal LPF3 Enable Chroma Psuedo Gamma Removal Enable Chroma Anti-Psuedo Gamma Removal DIS_GMSHC DIS_GMUSHC Enable Luma Psuedo Gamma Removal Enable Luma Anti-Pseudo Gamma Removal Enable Initial Luma Horizontal Pass Filter Bypass Luma, Horizontal LPF1 Luma, Horizontal LPF2 1/128 Range 1/64 Range 1/32 Range 1/16 Range Range Range Reserved CCORING[2:0] ADPT_FF Y_ATLFF[1:0] Line Line Line Line ADPT_FF C_ATLFF[1:0] Line Line Line Line Chroma, Horizontal LPF2 Chroma, Horizontal LPF3 Bypass +/-1/256 Range 1/128 Range 1/64 Range 1/32 Range 1/16 Range Range Reserved
Input
IN_MODE[3:0]
Functional Description
0000 24-bit
0001 16-bit
0010 15-bit
0011 24-bit Non-Mux
0100 24-bit YCrCb
0101 16-bit YCrCb
0110 Alternate 16-bit YCrCb
Controller Programmability Frequency Requirement Flicker-Free Video Encoder with Ultrascale Technology
Conexant
0111 24-bit YCrCb Non-Mux
1000 Alternate 24-bit
1001 Reserved
1010 16-bit Non-Mux
1011 Alternate 24-bit Non-Mux
1100 Alternate 24-bit YCrCb
1101 Reserved
1110 16-bit YCrCb Non-Mux
CX25870/871
1111 Alternate 24-bit Non-Mux
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VREF SYNC_AMP
CX25870/871
RESET*
Video Timing Control, Registers
Sync Processor
Internal Voltage Reference
COMP
Y[9:0]
VBIAS
Closed Captioning, Macrovision
CGMS
Luma Delay
Figure 1-3. CX25870/871 Encoder Core Block Diagram
CVBS
CVBS
Mode
DACA DACB DACC
Flicker-Free Video Encoder with Ultrascale Technology Controller Programmability Frequency Requirement
Conexant
Luminance Upsample Cross Color Peaking Filt.
Color Space Convert
CRCB[9:0]
Upsample/ Matrix Multiplication
Modulator, Mixer SECAM Filt.
DACD
Burst Processor
HUE_OFF
BST_AMP
RGB/ YCRCB/ YPRPB
HSYNC* VSYNC*
HDTV Sync Gen.
Functional Description
100381_004
Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Device Description
1.3.1 Overview
CX25870/871 video encoder designed output interlaced noninterlaced graphics data. Common applications requiring flicker-filtered output include: desktop/portable with high definition players boxes graphic cards with game consoles set-top boxes
incorporates normal adaptive filtering technology flicker removal flexible amounts overscan compensation high-quality display noninterlaced images interlaced CX25870/871 accomplishes this minimizing flicker controlling amount overscan that entire image viewable. CX25870/871 consists Color Space Converter/Flicker Filter engine followed digital video encoder. Color Space Converter/Flicker Filter contains: timing converter Various horizontal video processing functions Flicker filter vertical scaler overscan compensation
output this engine feeds into FIFO synchronization with digital video encoder. CX25870/871 provides Composite, S-Video, 3-signal analog YPBPR HDTV output. While encoder HDTV output mode, device will automatically insert trilevel synchronization pulses (when necessary) vertical synchronizing "broad pulses." CX25870/871 compliant with EIA770-3, SMPTE 274M/293M/296M supports ATSC HDTV resolutions including 480p, 720p, 1080i.
1.3.2 Serial Interface
device includes 2-wire read write serial interface programming registers device. interface designed operate with levels. ensure that valid serial data received transmitted, make sure VDD_SI connected stable supply. Review Chapter 2.2, Chapter Chapter more details encoder's serial interface.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.3 Voltage Graphics Interface
CX25870/871 receive transmit signals from/to graphics controller five different voltage levels. allowable voltage levels Default input/output voltage amplitude interface signals (defined P[23:0], HSYNC*, VSYNC*, CLKI, CLKO, BLANK*, FIELD) matches Bt868/869 ensure backwards compatibility. digital interface, special configuration steps necessary. Simply follow "Recommended Layout Connection with Master Device" Chapter power-up, encoder will automatically expect signal transitions. lower digital interface, several special configuration steps necessary. First, layout must adhere Chapter 3.3's "3.3 V/1.8 Recommended Layout Connection with Master Device." Second, program DRVS[1:0] field (bits[6:5] register (0x32)) 01(or alternate value interface). This forces encoder increase drive strength each interface signal used output interface. Third, connect VDDL (pin VDD_CO (pin power supply pins correct lower supply voltage (1.8 other). Fourth, using voltage divider circuit some other method, CX25870/871's VDD_VREF input (pin level equal (VDDL/ Make sure this voltage source stable since VDDL controls output signal levels. VDD_VREF dictates encoder threshold voltage received appropriate input signals. third fourth steps illustrated Figure 3-5. Make sure graphics controller configured send accept signals lower supply voltage. Adjusting VDD_CO, VDDL VDD_VREF appropriately controls input voltage levels digital input pins P[23:0], CLKI, HSYNC*/VSYNC*/BLANK* slave interface; EN_BLANKO Using DRVS[1:0] bits control output voltage levels digital output pins CLKO, FIELD, HSYNC*/VSYNC*/BLANK* master pseudo-master interface; EN_BLANKO this way, digital input pins operate different input voltage levels than digital output voltage levels.
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Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-5. Digital Pins that Comprise Voltage Graphics Interface
Name
Pixel[0] Pixel[1] Pixel[2] Pixel[3] Pixel[4] Pixel[5] Pixel[6] Pixel[7] Pixel[8] Pixel[9] Pixel[10] Pixel[11] Pixel[12] Pixel[13] Pixel[14] Pixel[15] Pixel[16] Pixel[17] Pixel[18] Pixel[19] Pixel[20] Pixel[21] Pixel[22] Pixel[23] HSYNC* VSYNC* FIELD BLANK* CLKI CLKO Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input
Direction
Input Output Input Output Output Input Output Input Output
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.4 Reset
RESET* held (between -0.5 minimum clock cycles, timing reset software reset performed serial interface held reset condition. timing reset, which generated setting TIMING_RST register bit, will subcarrier phase zero, configure horizontal vertical counters beginning VSYNC* Field (both counters equal zero). CX25870/871 master interface (i.e., CX25870 sends syncs data master) then after power-on reset encoder flicker filter starts line pixel their respective timing generation. encoder this means field always first field after power-on reset, reset, timing reset. timing slave interface (CX25870 either pseudo-master pure slave), even though input receiving progressive frames that have field associated with input timing generator keeps track frames received. result, after every second frame received, frame sync sent encoder section that input encoder remain synchronized. frame sync forces encoder beginning field. Conexant recommends that after every overscan compensation video output type change, TIMING_RST enabled. setting TIMING_RST should occur after waiting minimum between last CX25870 register write overscan compensation ratio. TIMING_RST register clears itself reinitializes internal timing generators. software reset, which generated setting SRESET register bit, initializes serial interface registers their default state. result, digital output control pins three-stated. Registers 0x38 0x76 0xB4 inclusive then initialized auto-configuration mode (see Auto Configuration section values) mode depending state pin. EN_OUT must enable digital outputs. power-on reset, reset, timing reset (register 0x6C, causes input timing generator send encoder frame synchronization pulse setting encoder beginning field. first HSYNC*/VSYNC* combination then corresponds encoder even field then second HSYNC*/VSYNC* combination again causes frame synchronization pulse encoder will start field, forth. power-on reset generated power-up. power-on reset generates same type reset RESET* pin. time delay circuit triggered after supply voltage reaches value sufficiently high enough circuit operate then generate power-on reset. such, device initialize default state unless power supply ramp rate sufficiently fast enough. hardware/pin reset recommended default state required.
1.3.5 Device Initialization
After reset condition, device must programmed through serial interface activate video output enable CLKO, HSYNC*, VSYNC*, FIELD outputs. easiest method accomplishing initialization phase auto configuration modes Appendix program interface bits appropriately. (Refer Section 1.3.8.)
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.6 Clocking Timing Generation
timing generators control operation encoder. output encoder timing block generates signals proper encoding video into NTSC, PAL, SECAM extracts processed input pixels from internal FIFO. encoding timing generator receive clock from either external crystal oscillator internal (master pseudo-master interface), from CLKI (slave interface). Conexant recommends that encoding clock generated PLL. Register EX_XCLK selects clock source. EN_XCLK logical internal clock source selected crystal attached XTALIN/XTALOUT. When EN_XCLK set, clock source received CLKI utilized main pixel/encoder clock. Conexant recommends that encoding clock generated PLL. crystal must present between XTALIN XTALOUT pins internal clock source selected. this case, CX25870/871's frequency synthesized such that pixel clock frequency equals DIV10=0: Fclk Fxtal {PLL_INT(5:0) [PLL_FRACT(15:0)/216]}/6 DIV10=1: Fclk Fxtal {PLL INT(5:0) [PLL FRACT(15:0)/216]}/10 where: Fclk CLKO Output Frequency CLKI Input Frequency
NOTE:
some special modes, CLKO Fclk
crystal must chosen that precise line rate video standards required achieved. This done maintain subcarrier relationship line rate thereby achieve precise subcarrier frequency required. crystal oscillator designed oscillate from through MHz. 13.5000 crystal meets requirements NTSC, PAL, SECAM video standards. crystal must within maximum desired clock rate NTSC operation, SECAM operation, across temperature range CX25870/871 provide video outputs selectable through software, customer must crystal with maximum tolerance across temperature range ppm. Appendix contains list previously tested recommended crystal vendors. crystal oscillator disabled XTAL _PAD_DIS register bit. Sufficient time must allowed after coming sleep mode allow oscillator stabilize. PLL_LOCK when stable. addition, PLL_INPUT register logical CLKI selected reference PLL. this special mode (slave interface with PLL_32CLK high), above Fclk formulas replace Fxtal with FCLKI/2 (i.e., input clock frequency divided external clock source selected (EN_XCLK=1), clock signal desired pixel clock rate must present CLKI pin. CLKO three-stated, crystal oscillator disabled. clock must meet same requirements above. highly recommended that internal clock used order ensure output video remains within specifications defined relevant video standard. aberration source clock reflected color subcarrier frequency output video detracts from quality image television.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
BY_PLL bypasses PLL, encoder clock will crystal frequency. This takes precedence over EN_XCLK bit. second timing generator controls generation HSYNC*, VSYNC*, BLANK* signals, pixel input clocking. This normally same clock encoding clock. EN_ASYNC register bit, set, allows this clock driven directly CLKI pin. DIV2 register set, this internal clock divided before driving second timing generator. This required interlaced input interlaced output mode (i.e., CCIR601/DVD CCIR656 applications). CLKI clock used synchronizing pixel inputs (P[23:0]) with timing input signals (HSYNC*, VSYNC*, BLANK*) normally delayed version CLKO pin. directly connected CLKO desired. Data registered with this input re-synchronized internal clock. multiplexed input mode, both edges CLKI input used. MODE2X register set, internal clock divided two, allowing external clock, data provided rising edge only. 1.3.6.1 Clocking Mode graphics controllers require some finite time resetting their internal counters zero, clearing register flags, other event that needs performed line-by-line basis. time these incidents take graphics controller's Horizontal Blanking Time. amount Horizontal Blanking time varies from master device another never less than usually does exceed digital line.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure illustrates higher resolutions (i.e., 800x600 greater), some data master devices that require more Horizontal Blanking Time than CX25870/871 provides standard clocking mode, dual display certain overscan compensation percentage pairs. example, graphics controller require minimum total 1.25 Horizontal Blanking time line while clocking frame with active resolution 800x600 encoder. this were case, entire overscan compensation solutions charted diagonal plot line (denoted with dot-dash-dot) below made unavailable designer. result more limited overscan pairs choose from, correspondingly less size control picture when displayed television.
Figure 1-4. Allowable Overscan Compensation Ratios Dual Display, 800x600 Input/NTSC Output
Overscan Compensation Percentage Pairs 800x600 NTSC
Horizontal Overscan Compensation Percentage
Horizontal Blanking
Legend: Pixel Clock Solution 8-Cycle Character Clock Solution 9-Cycle Character Clock Solution
Vertical Overscan Compensation Percentage
NOTE(S): this chart allowable overscan ratios
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
Since CX25870/871 contains this Clocking Mode, designer does face this constraint longer. choosing appropriate autoconfiguration mode, setting PLL_32CLK altering values various timing registers within controller encoder (e.g., H_CLKI HTOTAL, VLINES_I VTOTAL, H_BLANKI, V_BLANKI, etc.), encoder switches into Clock mode. While this operational state, additional solutions overscan-compensation-pairs domain higher resolutions exist. addition, encoder allows data master (e.g., graphics controller) send digital data faster rate than clocked encoder. Specifically, CX25870/871 begins transfer pixels rate [2/3] that CLKI input frequency. other words, pixel input frequency clocks data ratio [3:2] times faster than CX25870/871 outputs analog pixel data. this mode, encoder's expansive on-chip FIFO bridges frequency difference that exists between digital-timing input mixed-signal encoder output blocks CX25870/871. result much closer match available overscan percentages horizontal vertical direction higher resolutions. This ensures picture appears more orthogonal where amount blanking nearly equal sides image. Since Horizontal Blanking Time only becomes critical issue higher resolutions, user should Clocking Mode only when necessary 800x600, always 1024x768. software programming ease, some autoconfiguration modes 800x600 1024x768 resolution solutions already. specific modes that clock feature contained Appendix summarized Table below.
Table 1-6. Autoconfiguration Solutions that Utilize Clocking Mode Autoconfiguration Mode
Active Resolution
1024x768 1024x768 1024x768 1024x768 800x600 800x600 1024x768 1024x768 800x600 800x600 1024x768 1024x768
Type Digital Input
YCrCb YCrCb YCrCb YCrCb
Overscan Ratio
Standard Standard Standard Standard Lower Lower Lower Lower Higher Alternate Higher Higher
Video Output Type
NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL-BDGHI
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
desired overscan ratio available particular autoconfiguration mode, should derive another Solution Super Cockpit (i.e., CX25870 register programming tool), contact your local directly. done correctly, this CX25870/871 register will have PLL_32CLK (bit register 0x38) adjust timing registers appropriately.
1.3.7 Master, Pseudo-Master, Slave Interfaces
Like predecessor, Bt868/869, CX25870/871 encoder operated three possible interfaces. These connection types named master, pseudo-master, slave. clocking ability master device direction timing signals dictate what particular interface used between Conexant encoder graphics controller/data master device. 1.3.7.1 Master Interface master interface, CLKO, HSYNC*, VSYNC*, BLANK*, generated encoder outputs. These signals' leading edges denote when clock period, line, frame starts respectively. Because encoder transmits clock timing signals, this interface also referred clocking master/timing master. illustration master interface shown below using graphics controller master device S-Video Composite ports video outputs.
Figure 1-5. Operating CX25870/871 Master Interface
Clock
Clock Delay Graphics Controller YCrCb HSYNC* VSYNC* BLANK*
CLKI
CLKO
Composite Luma Chroma Composite S-Video
CX25870/ CX25871
100381_054
minimum inputs (CLKI lines pixel data- P[7:0]) outputs (HSYNC*, VSYNC*, CLKO) required this configuration. amount inputs could grow high 24-bit nonmultiplexed mode chosen Input Pixel Mode (i.e., IN_MODE[3:0] 0011) designer. Master interface only exist graphics controller accept encoder's reference clock send back version that clock same frequency with pixel data transitions synchronized CLKI's rising falling edges. This accomplished encoder's clock output (CLKO) clock input (CLKI) ports.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.7.2 Reason BLANK*
graphics controller possesses pixel-based resolution (i.e., pixels only single pixel clock wide) then encoder does have transmit receive BLANK* signal. However, graphics controllers that character clock based, BLANK* signal necessary. BLANK line necessary because character clock actually pixel clocks duration. This causes several pixel clocks elapse, resulting erroneous delay prior next HSYNC* being observed encoder next line starting. only method compensating this delay character clock based controllers BLANK* signal. This signal required physical interface indicate exact location first active pixel each line. pseudo-master interface, CX25870/871 generates clock reference signal, CLKO output. This signal's purpose inform graphics controller exact frequency which data must sent encoder. Timing signals, HSYNC*, VSYNC*, BLANK*, received encoder inputs. leading edges these signals denote when clock period, line, frame starts, respectively. Because this connection scheme shares mastering responsibilities, interface also named clocking master/timing slave. illustration pseudo-master interface illustrated below using graphics controller timing master device.
1.3.7.3 Pseudo-Master Interface
Figure 1-6. Operating CX25870/871 Pseudo-Master Interface
Clock
Clock Delay Graphics Controller YCrCb HSYNC* VSYNC* BLANK*
CLKI
CLKO
Composite Luma Chroma Composite
CX25870/ CX25871
100381_055
minimum inputs (CLKI, HSYNC*, VSYNC*, lines pixel data- P[7:0]) output (CLKO) required this configuration. amount inputs could grow high 24-bit nonmultiplexed mode chosen Input Pixel Mode (i.e., IN_MODE[3:0] 0111) designer. Pseudo-Master interface only exist graphics controller accept encoder's reference clock send back version that clock same frequency with pixel data transitions synchronized CLKI's rising falling edges. This accomplished encoder's clock output (CLKO) clock input (CLKI) ports.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.7.4 Slave Interface
slave interface, output signals generated encoder. CX25870/871 relies strictly graphics controller send clock timing signals trigger when clock period, line, frame starts. Because frequency reference signal used (CLKO), master device must pre-program encoder with appropriate register CX25870/871 expects data specific digital pixel rate prior actually receiving data. addition, timing signals must shaped they adhere appropriate slave interface timing diagrams illustrated Chapter 4.0. added complexity this interface, Conexant recommends only final option. slave interface illustrated Figure below using graphics controller master device S-Video Composite ports video outputs.
Figure 1-7. Operating CX25870/871 Slave Interface
Clock Graphics Controller YCrCb HSYNC* VSYNC* BLANK*
CLKI Cx25870/ CX25871
Composite Luma Chroma Composite
100381_056
minimum inputs (CLKI, HSYNC*, VSYNC*, P[7:0]) required this configuration. amount inputs will increase (without BLANK*) (with BLANK*) 24-bit multiplexed mode chosen Input Pixel Mode (i.e., IN_MODE[3:0] 0000) designer. highly recommended that device operate master pseudo-master interface ensure that input output video streams remain synchronized. either master device, supplying HSYNC* VSYNC* inputs, encoder, which receives data, correctly programmed, output image will lose lock with input. running CX25870/871 either clock master interface, timing errors that occur absorbed some extent expansive on-board FIFO.
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Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.7.5 Slave Interface Without Crystal
price-sensitive applications, possible remove crystal found between XTALIN XTALOUT ports strictly utilize incoming CLKI signal both data transfer mechanism internal main clock source encoder. complete this architecture, data master must also program CX25870's EN_XCLK This will trigger CLKI used operations requiring clock source force encoder ignore oscillations received XTALIN XTALOUT pins. flicker filter timing blocks will utilize this asynchronous clock input side data processing, encoder will combine internal CLKI conjunction with DACs transmit video from device. Since CLKI will only incoming frequency reference, encoder uses this signal internal derivation video color subcarrier (Fsc). Since SECAM televisions lenient accepting color subcarrier frequencies with more than error (i.e., Hz), critical data master maintain very high level accuracy incoming clock. numerical terms, this means that incoming clock should always remain within window {ideal CLKI} ppm. example, autoconfiguration mode CLKI would have reside range [29.499270 ideal CLKI 29.500008 29.500746 MHz.] Tight control incoming digital clock ensures that CX25870 generates analog 4.433618 PAL-BGHI 4.250000 4.406250 SECAM. Actual testing found that excursions outside this range result loss color SECAM televisions sometimes affect NTSC sets same manner. When CX25870 receiving external clock, serial also dependent this incoming signal. result, data master should never disable input clock. this happens, even momentarily, only encoder recover data master RESET* CX25870. encoder will then re-enabled timing master respond again serial commands transmitted data master. Several other registers must reprogrammed make this special type interface work properly. Consult your local Conexant representative technical assistance.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.8 Autoconfiguration Interface Bits
default operation CX25870/871 tied into autoconfiguration modes. Autoconfiguring device occurs when bits CONFIG[5:3] CONFIG[2:0] register 0xB8 programmed state from 000000 101111. conclusion this serial write, default values copied from CX25870/871's internal into most important timing registers that have indices 0x38 0x76 0xB4, inclusive. other registers changed conclusion autoconfiguration mode. After autoconfiguration command, CX25870/871 device remains same interface before command execution. Depending which autoconfiguration mode# initiated, CX25870/871 will expect receive either 320x200, 320x240, 640x400, 640x480, 720x400, 720x480, 720x576, 800x600, 1024x768 active digital input frame output NTSC composite and/or S-video signal. Table this data sheet description CONFIG[5:0] Appendix more detail each autoconfiguration mode. Using autoconfiguration mode easiest method bringing most popular desktop, game/Direct boot-up screen, resolutions with encoder both timing clock master. This true even graphics controller cannot utilize CX25870/871 master mode must pseudo-master mode. turn direction SYNCs around they transmitted graphics controller received CX25870/871 simply requires reprogramming encoder several serial writes. Interface bits that need changed SLAVER, EN_BLANKO, EN_DOT, EN_OUT. Since abilities graphics controllers vary greatly, Tables through 1-12 have been compiled below explain relationship between Interface bits actual interface itself. Even more permutations following interfaces below possible Tables 1-12 capture most popular architectures.
Table 1-7. Master Interface without BLANK* Signal (Default Immediately after Autoconfiguration Command) Interfaced Used
MASTER (default) BLANK* output from CX25870/871 BLANK* included part interface.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
SLAVE tied GND, state SLAVER dictates whether CX25870/871 timing master timing slave controlling direction HSYNC* VSYNC* ports. other words, SLAVER will determine whether overall interface master pseudo-master. SLAVER allows graphics controller vendor switch between master video timing slave video timing through software long SLAVE (#51) low. EN_BLANKO high (=1), signifying CX25870/871's BLANK* port output that BLANK* signal used part system. EN_DOT telling CX25870/871 internal counters determine active versus blanking regions. EN_OUT ensures there clock output (CLKO) from CX25870/871 also enables HSYNC* VSYNC* outputs.
Table 1-8. Master Interface with BLANK* Input CX25870/871 Interfaced Used
MASTER BLANK* SIGNAL transmitted CX25870/871 received input.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
SLAVE tied GND, state SLAVER dictates whether CX25870/871 timing master timing slave controlling direction HSYNC* VSYNC* ports. other words, SLAVER determines whether overall interface master pseudo-master. SLAVER allows graphics controller vendor switch between master video timing slave video timing through software long SLAVE (#51) low. EN_BLANKO signifying CX25870/871's BLANK* port input. EN_DOT telling CX25870/871 BLANK* signal receiving determine where active video starts (rising edge BLANK*) uses HACTIVE register determine start blanking region. EN_OUT ensures there clock output (CLKO) from CX25870/871 also enables HSYNC* VSYNC* outputs.
Table 1-9. Pseudo-Master Interface without BLANK* Signal Interfaced Used
PSEUDO MASTER BLANK* included part interface.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
SLAVER CX25870/871 video timing slave. expects receive syncs from graphics controller. EN_BLANKO high(=1), signifying CX25870/871's BLANK* port output that BLANK* signal used part system. EN_DOT telling CX25870/871 internal counters determine active versus blanking regions. EN_OUT ensures there clock output (CLKO) from CX25870/871.
Table 1-10. Pseudo-Master Interface with BLANK* Input CX25870/871 Interfaced Used
PSEUDO MASTER BLANK* SIGNAL transmitted CX25870/871 received input.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
SLAVER CX25870/871 video timing slave. expects receive syncs from graphics controller. EN_BLANKO signifying CX25870/871's BLANK* port input. EN_DOT telling CX25870/871 BLANK* signal receiving determine where active video starts (rising edge BLANK*) where blanking region starts (falling edge). EN_OUT ensures there clock output (CLKO) from CX25870/871.
Table 1-11. Slave Interface without BLANK* Signal Interfaced Used
SLAVE BLANK* included part interface.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
EN_XCLK (MSb Register 0xA0)
After autoconfiguration command, CX25870/871 expects active VSYNC* HSYNC* signals from controller. format pixels input encoder needs 24-bit multiplexed unless modifications made IN_MODE[3:0] 4-bit sequence. addition Table 1-11, another must programmed manually with this interface. most significant CX25870/871 register 0xA0 must set. This guarantees that EN_XCLK high (=1) which will allow CX25870/871 accept CLKI pixel clock source.
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100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
SLAVER CX25870/871 video timing slave. expects receive syncs from graphics controller. Since CX25870 slave mode, HSYNC* VSYNC* outputs will three-stated CX25870/871 will receive these timing signals from graphics controller. EN_BLANKO high (=1), signifying CX25870/871's BLANK* port output that BLANK* signal used part system. EN_DOT telling CX25870/871 internal counters determine active versus blanking regions. EN_OUT This ensures clock output port (CLKO) three-stated from encoder.
Table 1-12. Slave Interface with BLANK* Input CX25870/871 Interfaced Used
SLAVE BLANK* SIGNAL transmitted CX25870/871 received input.
SLAVER (Bit 0xBA) ORed with Slave
EN_BLANKO (MSb Register 0xC6)
EN_DOT (Bit Register 0xC6)
EN_OUT (LSb Register 0xC4)
EN_XCLK (MSb Register 0xA0)
NOTE:
After autoconfiguration command, CX25870/871 expects active VSYNC* HSYNC* signals from controller. format pixels input encoder needs 24-bit multiplexed unless modifications made IN_MODE[3:0] 4-bit sequence. addition Table 1-11, another must programmed manually with this interface. most significant CX25870/871 register 0xA0 must set. This guarantees that EN_XCLK will high (=1) which will allow CX25870/871 accept CLKI pixel clock source. SLAVER CX25870/871 video timing slave. will expect receive syncs from graphics controller. Since CX25870 slave mode, then HSYNC* VSYNC* outputs will three-stated CX25870/871 will receive these timing signals from graphics controller. EN_BLANKO signifying CX25870/871's BLANK* port input. EN_DOT telling CX25870/871 BLANK* signal receiving determine where active video starts (rising edge BLANK*) HACTIVE register denote where blanking region starts. EN_OUT This will ensure clock output port (CLKO) three-stated from encoder. Autoconfiguration Mode NTSC Playback place encoder into slave interface where expects BLANK* input (Table 1-11).
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Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.9 Adaptations Clock-Limited Master Devices
Ideally, graphics controller proprietary ASIC, combination with CX25870/871, operates either master pseudo-master interface. Occasionally, using either clock master configurations possible because master device does have capabilities receiving clock from encoder synchronize digital data with this clock return. either limitation exists, only slave interface used system configuration. Often, within slave interface, data master only generate certain discrete clock frequencies. This means encoder make extra accommodations normal occur. Fortunately, encoder does have flexibility adapt almost incoming clock frequency range from MHz. that required follow procedure Table 1-13 which forces encoder accept frequency through CLKI that does match CX25870/871 autoconfiguration frequency. Once CX25870/871's 4-byte wide register reprogrammed accordingly, result generation correct color subcarrier frequency NTSC corresponding proper S-Video Composite output. Table 1-13 Table 1-14 contain procedures required encoder accept frequency through CLKI that equal close chosen CX25870/871 autoconfiguration mode clock frequency. Completion steps contained tables will modify register PLL_INT PLL_FRACT registers correctly thus produce accurate NTSC analog output.
Table 1-13. Adjustment CX25870/871 Registers
What input frequency CX25870/871's CLKI input from data master? Depending answer step find autoconfiguration mode that frequency close incoming input frequency (within preferred). Look clock frequency chosen autoconfiguration mode Appendix CX25870/871 data sheet. Determine scaling factor where input frequency CLKI input (usually from data master) autoconfiguration mode frequency specified Appendix
Determine autoconfiguration mode's MSC[31:0] value reading back CX25870/871's registers; 0xB4(=MSB), 0xB2, 0xB0, 0xAE(=LSB). These register values also found looking them Register values determined will have cascaded together. Convert MSC[31:0] 4-byte hexadecimal value decimal. Divide total found from step scaling factor found from step Convert answer from step hexadecimal format. This value should comprised total bytes. most significant byte will likely change from previous value register MSC[31:24]. Other values change either least significant bytes should have definitely been modified. Program bytes determined from step into CX25870/871's MSC[31:0] registers. Write these bytes order registers 0xB4 (most significant byte MSC[31:24]), 0xB2, 0xB0, 0xAE (least significant byte MSC[7:0]).
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-14. Adjustment PLL_INT PLL_FRACT Registers
Functional Description
Device Description
What input frequency CX25870/871's CLKI input from data master? Depending answer step find autoconfiguration mode that clock frequency close incoming CLKI frequency (within preferred). Look desired clock frequency chosen autoconfiguration mode Appendix CX25870/871 data sheet. Determine scaling factor where:
input frequency CLKI input (usually from data master) autoconfiguration mode frequency specified Appendix
Determine PLL_INT value reading back CX25870/871's register 0xA0 that autoconfiguration mode. This register value also found looking Appendix Convert PLL_INT register value decimal. Multiply answer found step 65536. Determine PLL_FRACT value reading back CX25870/871's register 0x9E 0x9C. These registers cascade form PLL_FRACT[15:0] 2-byte value. These register values also found looking them Appendix Convert 2-byte PLL_FRACT register value decimal. From steps PLL_INT PLL_FRACT decimal values. Multiply total found from step scaling factor found from step Convert answer from step hexadecimal format. value should comprised total three bytes. most significant byte will likely original PLL_INT[7:0] byte from step Program bytes determined from step into CX25870/871's PLL_INT[7:0] PLL_FRACT[15:0] registers. most significant byte from step PLL_INT value. Write this register 0xA0. least significant bytes from step PLL_FRACT value. Write these bytes order registers 0xBE 0xBC respectively.
1.3.10 Input Formats
device convert wide range input formats analog standard HDTV television video formats. input either noninterlaced interlaced digital data from maximum 1024 pixels frame standard outputs. While generating HDTV outputs device accept greater than 1024 input frames. Many other nonstandard input formats encoded well. detailed information CCIR601 mode, please refer Movie Playback Architecture Solutions Application Note. This application note obtained from your local Conexant Systems sales office. instructions display nonstandard resolutions request "Supporting with Non-Standard Graphics Input Resolutions" Application Note from your local Conexant Systems sales office.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.11 Input Pixel Timing
device accept input data either YCrCb color spaces. Data input either full pixel time clocked rising edge CLKI only, various multiplexed modes, using both edges CLKI. YCrCb format, either 24-bit 4:4:4 data 16-bit 4:2:2 data input. format, either 15-bit 5:5:5, 5:6:5, 24-bit input. 16-bit 4:2:2 YCrCb input format, multiplexed data input through P[11:4] P[7:0]input pins. data input falling edge CLKI. Cr/Cb data input rising edge CLKI. Cb/Y/Cr/Y sequence begins first active pixel. additional 4:2:2 YCrCb input format maps P[19:12] Cr/Cb multiplexed P[11:4]. 24-bit 4:4:4 YCrCb input format, multiplexed data input through P[11:0] inputs. Both rising falling edge CLKI sample input data. input format, input data sampled bits time 24-bit format bits time 15/16 format both rising falling edge CLKI. Table shows data assignments available multiplexed input formats. addition, 24-bit formats, 16-bit format, 16-bit YCrCb format utilize nonmultiplexed clocking method. Table these pin-to-bit assignments.
1.3.12 YCrCb Inputs (For Standard Outputs)
nominal range 16-235; have nominal range 16-240, with hex) equal zero. Values interpreted 254, respectively. values 1-15 236-254, CrCb values 1-15 241-254, interpreted valid linear values.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
Figure illustrates frequency response sub-sampling process. 4:4:4 data input, subsampled 4:2:2 prior overscan compensation flicker filtering.
Figure 1-8. Decimation Filter Fs=27
Chroma Decimation Filter
Decibels (dB)
Frequency MHz)
100381_005
resulting 4:2:2 output must then converted values then scaled output range DACs. MCR, registers must programmed perform this conversion. scaling equations follows: (int) [V100/(219.0 VFS) 0.5] (int)[(128.0/127.0) V100 0.877/(224.0 0.713 sinx) 0.5] (int)[(128.0/127.0)* V100 0.493/(224.0 0.564 sinx) 0.5] where:V100 100% white voltage (0.661 NTSC, PAL/SECAM) Full scale output voltage (1.28 color subcarrier frequency (see Table A-2) Fclk Analog pixel rate Sinx
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.13 Inputs (For Standard Outputs)
With IN_MODE[3:0] mode, encoder must receive digital gamma-corrected data input. this occurs, data will converted Y/R-Y/B-Y follows: Y[9:0] [INT(0.299 210) R[7:0]} INT(0.587 G[7:0] INT(0.114 210) B[7:0] Y[9:0] 1024 input formats, individual values left justified eight numbers. After initial conversion, Y/R-Y/B-Y values sub-sampled 4:2:2 data prior overscan compensation flicker filtering. resulting 4:2:2 output must then converted values then scaled output range DACs. MCR, registers must programmed perform this conversion. scaling equations are: (int)[V100/(255 VFS)*26 0.5] (int)[(128.0/127.0) V100 0.877/(127 sinx) 0.5] (int)[(128.0/127.0) V100 0.493/(127 sinx) 0.5] where:V100 100% white voltage (0.661 NTSC, PAL) Full scale output voltage (1.28 color subcarrier frequency (see Table A-2) Fclk CLKI input frequency Sinx FSC/FCLK)/(2 FSC/FCLK)] SECAM formulas SECAM section.
1.3.14 Input Pixel Horizontal Sync
HSYNC* provides line synchronization pixel input data. output master interface input slave pseudo-master interface. master interface, pulse CLKI cycles duration whose leading edge indicates beginning line pixel data. period between consecutive HSYNC* pulses H_CLKI cycles. first active pixel should presented device H_BLANKI minus internal pipelined clock cycles) after leading edge HSYNC*. next H_ACTIVE pixels accepted active pixels used construction output video. slave interface exact number clocks line (H_CLKI) must provided calculated desired overscan ratio. Only leading edge HSYNC* used, times must least CLKI cycles duration. HSYNC* clocked into encoder rising edge CLKI. polarity HSYNC* signal changed HSYNCI register bit. default convention active low.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.15 Input Pixel Vertical Sync
VSYNC* provides field synchronization pixel input data. output master interface, input slave pseudo-master interface. noninterlaced input timing master interface, VSYNC* pulse horizontal line time duration whose leading edge indicates beginning frame input pixel data. leading edge coincides with leading edge HSYNC*. period pulses V_LINESI horizontal lines. first line active data should presented device V_BLANKI lines after leading edge VSYNC*. next V_ACTIVEI lines accepted active lines used construction output video. CX25870/871 disregards lines after leading edge VSYNC* before VSYNC* V_BLANKI lines encoding them. slave interface, period must exactly frame rate desired video format. Only leading edge used, high duration must least CLKI cycles. beginning frame data indicated next leading edge HSYNC* coincident with after leading edge VSYNC*. interlaced input timing, only slave interface supported. period must exactly frame rate desired video format. leading edge HSYNC* VSYNC* coincident, that indicates input field, internal line counter reset line leading edge VSYNC*. leading edges HSYNC* VSYNC* coincident, separated minimum CLKI cycles, this indicates input even field. this case, internal line counter reset line beginning next line. Only leading edge VSYNC* used, high VSYNC* width must least CLKI cycles. VSYNC* clocked rising edge CLKI. polarity VSYNC* input output programmed VSYNCI register bit. default convention active low. FLD_MODE bits allow further flexibility HSYNC* VSYNC* timing relationship.
1.3.16 Input Pixel Blanking
Input pixel blanking controlled either BLANK* internal registers. Blanking programmed independently master slave interface using EN_BLANKO register bit. output (EN_BLANKO pixel blanking generated based active area defined H_BLANKI, H_ACTIVE, V_BLANKI, V_ACTIVEI registers. With EN_BLANKO BLANK* output proper relationship syncs indicate location active pixels. input (EN_BLANKO when BLANK* goes high, indicates start active pixels pixel input pins. addition, H_BLANKI register must programmed properly. duration active data still determined H_ACTIVE register. BLANK* clocked rising edge CLKI. additional function BLANK* used EN_DOT register set. EN_DOT BLANK* becomes input whose rising edge defines graphics controller character clock boundary. This used internally encoder keep track exact pixel count controllers that cannot operate pixel clock rates instead operate character clock rates. polarity BLANK* input/output programmed BLANKI register bit. default convention active low.
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Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-15 summarizes direction BLANK* encoder each interface. more information refer Section 1.3.8.
Table 1-15. Summary Allowable BLANK* Signal Directions Interface Interface
Master Pseudo-master Slave
Allowable Direction BLANK*
Input Output Input Input
1.3.17 Overscan Compensation
Overscan compensation process which encoder converts digital input lines appropriate number output lines producing full-screen image television receiver. This conversion done accordance with Vertical Scaling Ratio (VSR). ratio number input lines received number output lines generated CX25870 (i.e., 262.5 lines/field NTSC 312.5 lines/field PAL-BDGHI SECAM). Using correct amount compensation both horizontal vertical dimensions least percent) will ensure that entire digital image normally seen monitor satisfactorily mapped analog television without pixels lines hidden unviewable areas. Increasing Horizontal Overscan Compensation (HOC) percentage while keeping Vertical Overscan Compensation (VOC) percentage same will have several effects Encoder. First, number output clocks line (H_CLKO) will increase. Correspondingly, clock frequencies shared between data master CX25870 (i.e., CLKO CLKI) will increase. Therefore, original number active pixels will squeezed into smaller analog video display region because frequency which input data clocked into CX25870 increased. Since CX25870 processes active data faster rate than CCIR601-only compatible encoders, graphics controller will need transmit more blank pixels line (i.e., HTOTAL must increase match CX25870's H_CLKI) make difference. Increasing (VOC) percentage while keeping Horizontal Overscan Compensation percentage same will have several different effects Encoder. First, H_CLKO total will stay same will pixel rate (i.e., CLKI CLKO). These parameters dictated value only. Second, number total vertical input lines (V_LINESI data master's VTOTAL) will increase, which will increase internal VSR. result that more active pixels more active lines will used generate each output line. only graphics controller transmit these additional input lines with same clock frequency before decrease amount blanked pixels line.
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100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
support custom overscan ratio, entire overscan compensation calculations required. This results many register values CX25870. ease use, these equations embedded into Conexant's programming application called Super Cockpit. Each computation somewhat interdependent others basic overscan equations follows: (V_LINESI) total output lines field) (**) Blanked Pixels {[H_CLKO VSR] H_ACTIVE} illustrative purposes, calculations used generate 13.785 percent percentage Autoconfiguration Mode 0-640x480 H_CLKO 1792, NTSC output, shown below: From Appendix (CX25870/871 Data Sheet): Number clocks necessary latch .S.R. input lines every analog output line 1792 CLKs [i.e., H_CLKO] CX25870 must ensure input upsampled. Therefore: active CLKs analog line 2*(H_ACTIVE) active CLKs analog line 1280 active CLKs analog line percent input used create active video area {1280 active CLKs 1792 total CLKs} 71.4286 percent Therefore: active region percent analog output line 71.4286 percent active region percent typical analog video NTSC 52.65556 63.55556 82.4945 percent line active Ratio [x/y] {71.4286 percent 82.4945 percent} 0.862147 percentage 1-{Ratio [x/y]} percent 1-0.862147 13.785 percent percentage Autoconfiguration Mode result, 13.785 percent horizontal active region within each line NTSC signal will forcibly blanked CX25870. most TVs, this will resize upsampled digital image properly pixels horizontally within bezeled area North American Japanese TVs. 13.785 percent overscan percentage equally distributed either side horizontal active region (i.e., 13.785 percent 6.89 percent extra blanking beginning line). original active pixels (i.e., H_ACTIVE) will then `squeezed' into remaining analog active region faster pixel rate. explanation vertical overscan percentage value similar. autoconfiguration mode V_ACTIVEO 212, which means there full active lines field. first last lines filtered lines that assist smoothing transitions into active region avoid flickering counted. NTSC standard calls active lines field, 210/243 0.864198 vertical active region used. This calculation yields vertical overscan compensation percentage 100-86.4198 13.5802 percent.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Flicker filtering vertical horizontal overscan compensation SUPPORTED interlaced YCrCb input format sent CX25870. Interlaced input data commonly used from MPEG2 Decoder chip. Because data image content types, flicker filtering overscan compensation necessary this case. Illustrations showing before after effects overscan compensation found Figures 1-10.
Figure 1-9. Windows Desktop Image From Encoder Without Overscan Compensation
Active Viewable Area with Vertical Overscan Compensation number active lines hidden behind TV's bezel
Active Viewable Area with Horizontal Overscan Compensation number active pixels hidden behind TV's bezel
NOTE(S): Overscan percentages taken from CX25870's Autoconfiguration Mode
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-10. Windows Desktop Image From CX25870 With Overscan Compensation
Functional Description
Device Description
13.58 6.79 Blanking Each Side
13.78 6.89 Blanking Each Side
NOTE(S): Overscan percentages taken from CX25870's Autoconfiguration Mode
100381_073
Figure 1-10, CX25870 overscan compensated horizontal active pixels data within viewable video region. With 13.78 percent HOC, active data contained within 45.397 portion time within each active line while remaining 7.26 (52.65556 µs.-45.397 µs.) part active region blanked encoder. result overscan compensation will interlaced NTSC, PAL, SECAM video image that fits within bezel area Monitor. Correct choice Vertical Overscan Compensation (VOC) percentages important that regions active input image will hidden behind plastic unit. Various require different values fully utilize entire viewable area user's convenience, Conexant generated Appendix CX25870/871 datasheet which lists many possible overscan ratios major desktop resolutions (640x480, 800x600, 1024x768) most popular video outputs (NTSC PAL-BDGHI). Varying amounts blanking would required depending percentages active input resolutions. Ultimately, blanked regions would dictated BLANK* signal itself and/or internal pixel counter CX25870/871. Actual transmission null blanked pixels necessary since encoder ignores data sent pixel input port within blanked regions. Only active pixels need sent encoder from controller during digital active period.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figures through illustrate many allowable overscan compensation percentage pairs major desktop resolutions most popular video outputs. These figures illustrate minimum horizontal blanking times data master must possess along with overscan compensation plots pixel based data masters well 8-and 9-cycle character clock based graphics controllers.
1.3.18 Standard Flicker Filtering
understand what flicker filtering must understand primary differences between analog video standards used technology used today's computer monitors. First all, computer monitors receive their video signal more basic, pristine form than discussed earlier, video signal sent computer monitor broken into multiple electrical components (red, green, blue sync) while signal necessary information combined into single composite signal separate Luma Chroma analog channels (S-Video). order process this composite signal, must break into original components, inevitably degrading picture quality creating distortions. second factor contributing decreased quality images displayed monitors interlacing, technique which complete picture drawn passes from bottom picture tube. interlacing, first pass paints "odd" lines second pass paints "even" lines. Noticeable flicker occurs when images lines very different from images even lines. even lines alternately displayed, perceives quick appearing disappearing visual information. This results irritation called flicker. Flicker especially noticeable when viewing thin horizontal lines that only take single within even field. example, line happens row, totally disappears every time even rows displayed resulting that item appearing disappearing field rate Unlike monitors, computer monitors paint entire image pass from bottom, display format called noninterlaced progressive. Images displayed noninterlaced format suffer from same flicker problems. improved image quality reduced flickering, CX25870 contains 5-tap 5-line flicker filter both Luma (F_SELY[2:0]) channel Chroma (F_SELC[2:0]) channel. Conexant standard flicker-filter works applying mathematically weighted averaging algorithm incoming pixels data from different lines. This slightly alters digital information that processed eventually converted even lines picture that alternating lines more similar each other. This way, when they appear disappear interlacing process, flicker less noticeable. more similar lines made appear, less flicker visible.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
However, trade-off that flicker reduced, more more information being altered encoder potentially lost from original picture. Vertical resolution therefore sacrificed text clarity suffers especially small fonts below points size. this reason, amount flicker filtering programmable should controllable user. Finding optimal standard flicker filter setting Luma Chroma somewhat subjective nature ensures that pleasing image seen television. Unlike other encoders, CX25870 integrates both standard flicker filter additional adaptive flicker filter. This implementation allows preservation small font text clarity other challenging video images lost with only filtering step. adaptive feature eliminates more flicker with less loss resolution because able selectively apply more aggressive flicker reduction only those portions image where effect will beneficial. Encoders lacking this adaptive filter apply standard flicker filtering process entire screen. Small text icons often become unreadable thin, horizontal lines completely disappear. CX25870's adaptive flicker filter prevents this from happening described section within this document. long progressive YCrCb data received, CX25870's flicker filter effective with active resolution from 320x200 maximum 1024 768. flicker reduction present interlaced video output such NTSC, PAL, SECAM. DIS_FFILT register turns standard flicker filter. vertical scaling disabled setting internal V_SCALE register 4096 noninterlaced input. Finally, CX25870 supports 24-bit color processing, meaning that converted image will feature same depth color original computer picture.
1.3.19 Adaptive Flicker Filter
Adaptive Flicker Filtering feature included with CX25870/871. allows encoder automatically alter amount flicker filtering based image being processed. result high-quality optimized image because perfect balance between vertical resolution flicker reduction been achieved. adaptive flicker filter enabled ADPT_FF bit. There four possible settings ranging from 2-line (most observable flicker, greatest vertical resolution) 5-line (minimal observable flicker, moderate vertical resolution). luminance chrominance outputs independent terms level adaptive flicker filtering. When adaptive flicker filter manual flicker filter vice versa. Vertical filtering CX25870/871 serves three purposes: Vertical polyphase interpolation filtering upsample image data vertically. This increases resolution accuracy subsequent vertical downsampling required entire image into visible region television. Anti-alias filtering reduce aliasing artifacts when downsampling vertically. Flicker filtering reduce flicker produced when vertical high frequency content displayed interlaced device.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
vertical interpolation filtering vertical anti-alias filtering requirements driven amount vertical down scaling required, vary substantially with image content. flicker filtering requirement, however, dependent upon image content. Regions image with vertical high frequency content will flicker proportion amplitude that high frequency content. Regions with high amplitude vertical high frequency content require substantial flicker filtering, regions with amplitude vertical high frequency content require little flicker filtering. this reason, CX25870/871 provides adaptive flicker filtering. analyzes image content detect areas that require strong flicker filtering, adjusts vertical filtering apply stronger flicker filtering those regions. This analysis adjustment occurs pixel pixel basis, each pixel output line optimal amount flicker filtering applied Adaptive_FF1 Adaptive_FF2 registers (0x34 0x36) configure adaptive algorithm. Y_ALTFF[1:0] C_ALTFF[1:0] fields allow selection alternative (i.e., stronger) flicker filter combine with standard flicker filter selected fields F_SELY[1:0] F_SELC[1:0] (register 0xC8). This creates array flicker filters channel channel respectively. actual flicker filter applied given pixel output depends detection location high amplitude vertical high frequency content within input samples that creates that output pixel. amplitude high frequency content that triggers adaptation flicker filter adjusted Y_THRESH[2:0] C_THRESH[2:0] fields. FFRTN offers ways combine standard alternate flicker filters generate array flicker filters. YSELECT allows Chroma channel flicker filter adapted based Chroma channel (i.e., Luminance) channel content.
NOTE:
Neither standard adaptive flicker filtering supported CX25870/871 noninterlaced video output formats (VGA style RGB, HDTV 480p, 720p).
Table 1-16 summarizes recommended configurations adaptive flicker filter various types image content resolutions.
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Table 1-16. Optimal Adaptive Standard Flicker Filter Settings Common Applications Resolutions CX25870 Adaptive settings
ADPT_FF On=Checked On=Checked On=Checked On=Checked On=Checked On=Checked ADPT_FF On=Checked On=Checked On=Checked ADPT_FF Y_ALTFF C_ALTFF Y_THRESH C_THRESH 5-line 5-line Y_SELECT 5-line 5-line 4-line 4-line FFRTN Y_ALTFF C_ALTFF Y_THRESH C_THRESH Y_SELECT FFRTN 5-line 5-line BYYCR BYYCR 5-line 5-line CHROMA_BW CHROMA_BW 5-line 5-line 5-line 5-line Final Value Final Value 4-line 4-line 4-line 4-line Y_ALTFF C_ALTFF Y_THRESH C_THRESH Y_SELECT FFRTN BYYCR CHROMA_BW Final Value
100381B Register 0x34 Register 0x36
Final Value Final Value Final Value On=Checked On=Checked 5-line 5-line 4-line 4-line
Standard settings
CX25870/871
Desktop Resolution/ Video Output Type
FSEL_Y
FSEL_C
640x480 NTSC
3-line
3-line
640x480 PAL-BDGHI
3-line
3-line
800x600 NTSC
4-line
4-line
800x600 PAL-BDGHI
4-line
4-line
1024x768 NTSC
5-line
5-line
1024x768 PAL-BDGHI
5-line
5-line
Flicker-Free Video Encoder with Ultrascale Technology
Page Resolution/ Video Output Type
FSEL_Y
FSEL_C
Conexant
640x480 NTSC
4-line
3-line
800x600 NTSC
4-line
4-line
1024x768 NTSC
5-line
5-line
Word Processing Resolution/Video Output Type
FSEL_Y
FSEL_C
640x480 NTSC
3-line
3-line
800x600 NTSC
4-line
4-line
NOTE(S): means setting while denotes setting.
Functional Description
Device Description
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.20 Registers Involved Process
Timing constraints CX25870/871 driven timing requirements analog video output (NTSC, PAL, SECAM) together with active resolution overscan compensation ratio (i.e., amount blanking active region) television image. explain what specific CRTC registers within graphics controller need involved displaying nonstandard desktop format both CRT, work backwards from those output signal timing requirements determine input timing requirements. Each output field vertical blanking region active region. These regions defined relative vertical sync pulse, horizontal sync pulse, given format (i.e., number lines field), given pixel clock frequency (i.e., number pixel clocks line). Within each line active region there horizontal blanking period (that includes horizontal sync pulse) active period (where image data located). Given those parameters, least registers within every generic graphics controller need changed each active/total resolution. Table 1-17 lists VGA/CRTC Registers Involved Process.
Table 1-17. VGA/CRTC Registers Involved Process Register Name
Start VBLANK/VSYNC* VBLANK/VSYNC* VACTIVE VTOTAL HBLANK/HSYNC* Start HBLANK/HSYNC* HACTIVE HTOTAL
Description
These registers work combination with each other control scan line which vertical blanking period begins point which ends. Dictates specific number active lines present digital frame. Specifies number scan lines from VSYNC* active next VSYNC* active pulse. difference between Vtotal Vactive amount blanked lines. This register works combination with each other control value pixel character clock counter where HSYNC* signal becomes active position which HSYNC* becomes inactive. Dictates specific number active pixels line. Specifies number pixel clocks character clocks from HSYNC* active next HSYNC* active pulse. other words, this total time required both displayed nondisplayed portions single scan line. difference between Htotal Hactive amount blanked pixels line.
achieve compatibility, controller must manipulate some register settings order produce hi-quality dual display both computer monitor should noted that encoder knowing that different mode been selected. result, relies I2C®-compatible master device reconfigure autoconfiguration mode complete register rewrite make adjustments timing. When devices programmed correctly, regardless interface, required input HSYNC*/VSYNC* first input active pixel line spacing "matches" output HSYNC*/VSYNC* first output active pixel line spacing. When this occurs, graphics controller always transmits active data time CX25870/871 expects receive Superior quality achieved only when this type timing symmetry exists.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
1.3.21 Output Modes
encoder generate output video Composite/Y-C(S-Video), component, VGA-style RGB, SCART, Component (YPRPB) HDTV HDTV. These outputs selected OUT_MODE[1:0] register bits combination with HDTV_EN EN_SCART bits. While encoder style RGB, color space conversion possible from input output. Analog transmitted from digital input analog YCrCb output from digital YCrCb input. When outputting with HDTV_EN device outputs VGA/SVGA analog with bilevel sync. this mode, input data DACs after addition horizontal sync and, SETUP one, setup pedestal added. output currents scaled that DACs output proper full-scale (sync peak white) levels driving monitor. graphics controller must provide timing control (HSYNC VSYNC signals) monitor, which results encoder operating slave this case. Only P[23:0], BLANK*, HSYNC*, VSYNC* input pins analog output pins active. BLANK*, HSYNC*, VSYNC* pins automatically enabled inputs this mode. Each four video signals generated OUT_MODE[1:0] field multiplexed using OUT_MUXA[1:0], OUT_MUXB[1:0], OUT_MUXC[1:0], OUT_MUXD[1:0] register bits. this, program 2-bit value representing desired type output into appropriate OUT_MUXx[1:0] register. example, suppose system requires composite video (i.e., output from DAC_A, chroma (10) DAC_B, luma (01) DAC_C, composite video (00) DAC_D. This scheme could accomplished programming register 0xC6 with 0001 1000 binary hex. LUMADLY[1:0] register bits control amount delay Y_DLY analog output. allowable delay ranges from delay) pixel clocks. digital-to-analog converters designed drive standard video levels into combined RLOAD 37.5 (doubly-terminated loads). Unused outputs should disabled setting corresponding DACDISx minimize supply current left connect. Disabling unused outputs reduces cross chroma distortion improves picture quality.
1.3.22 Analog Horizontal Sync
HSYNC_WIDTH[7:0] register determines duration horizontal sync pulse. beginning horizontal sync pulse corresponds reset internal horizontal pixel counter. horizontal line rate determined H_CLKO[11:0]. internal horizontal counter reset beginning horizontal sync counts H_CLKO. sync rise fall times automatically controlled. sync amplitude programmable over range values SYNC_AMP[7:0]. Incrementing sync increases sync amplitude analog sync pulse millivolts.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.23 Analog Vertical Sync
analog vertical sync duration selectable either lines register VSYNC_DUR. VSYNC_DUR lines selected; VSYNC_DUR lines selected. device automatically blanks video from start horizontal sync interval through burst, well vertical sync prevent erroneous video timing generation.
1.3.24 Analog Video Blanking
Analog video blanking controlled H_BLANKO, V_BLANKO, V_ACTIVEO registers. Together they define active region where pixels displayed. V_BLANKO defines number lines from leading edge analog vertical sync first active output line field. V_ACTIVEO defines number active output lines. H_BLANKO defines number output pixels from leading edge horizontal sync first active output pixel. H_ACTIVE defines number active output pixels. device automatically blanks video from start horizontal sync interval through burst, well vertical sync interval prevent erroneous video timing generation.
1.3.25 Video Output Standards Supported
There several bits (625LINE, SETUP, VSYNC_DUR, PAL_MD, DIS_SCRST), pin, various autoconfiguration modes, that control generation various video standards. (These summarized Table 1-18.) They allow generation different NTSC, PAL, SECAM video standards. aforementioned bits control specific encoding process parameters. likely other registers need modified meet video parameters particular video standard. Video timing diagrams illustrated Figures 1-11 through 1-22. These show typical events that occur each type video format.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Functional Description
Device Description
Table 1-18. Important Settings Various Video Outputs
Video Output NTSC-M NTSCJapan PALBDGHI PAL-N PAL-Nc PAL-M PAL-60 SECAMSECAMSECAM-L(1) H(3) K1(2)
VSYNC_DUR 625LINE SETUP PAL_MD DIS_SCRST
NOTE(S):
SECAM-L used primarily France. SECAM-D, used primarily Russia Eastern European nations. SECAM-B, used primarily Middle East. Other CX25870 registers bits must reprogrammed generate different video outputs. bits Table 1-18 most important settings.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-11. Interlaced 525-Line (NTSC) Video Timing
RESET* Start VSYNC
Analog FIELD
BURST PHASE Analog FIELD
Analog FIELD
BURST PHASE Analog FIELD
Burst Begins with Positive Half-Cycle Burst Phase Reference Phase 180° Relative Burst Begins with Negative Half-Cycle Burst Phase Reference Phase 180° Relative
Note(s): SMPTE line numbering convention used rather than CCIR624.
100381_006
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-12. Interlaced 525-Line (PAL-M) Video Timing
Functional Description
Device Description
RESET* Start VSYNC*
Analog FIELD
Burst Phase Analog FIELD
Analog FIELD
Burst Phase Analog FIELD
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
100381_007
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-13. Interlaced 625-Line (PAL-B, Video Timing (Fields 1-4)
RESET*
Start VSYNC Analog FIELD
PHASE Analog FIELD
Analog FIELD
Analog FIELD
FIELD Burst Blanking Intervals FIELD FIELD Three FIELD Four
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
100381_008
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-14. Interlaced 625-Line (PAL-B, Video Timing (Fields 5-8)
RESET* Start VSYNC Analog FIELD
Functional Description
Device Description
PHASE Analog FIELD
Analog FIELD
Analog FIELD
FIELD Five Burst Blanking Intervals FIELD FIELD Seven FIELD Eight
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
100381_009
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-15. Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4)
VSYNC*
Analog FIELD RESET*
PHASE Analog FIELD
Analog FIELD
Analog FIELD
FIELD Burst Blanking Intervals FIELD FIELD Three FIELD Four
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
1000381_010
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-16. Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8)
Functional Description
Device Description
VSYNC* Analog FIELD
PHASE Analog FIELD
Analog FIELD
Analog FIELD
FIELD Five Burst Blanking Intervals FIELD FIELD Seven FIELD Eight
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
100381_011
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-17. Noninterlaced 262-Line (NTSC) Video Timing
START VSYNC
FIELD
Burst Begins with Positive Half-Cycle Burst Phase Reference Phase 180° Relative Burst Begins with Negative Half-Cycle Burst Phase Reference Phase 180° Relative
100381_012
Figure 1-18. Noninterlaced 262-Line (PAL-M) Video Timing
START VSYNC
FIELD
Burst Begins with Positive Half-Cycle Burst Phase Reference Phase 180° Relative Burst Begins with Negative Half-Cycle Burst Phase Reference Phase 180° Relative
100381_013
Figure 1-19. Noninterlaced 312-Line (PAL-B, Video Timing
RESET* Start VSYNC
Burst Phase Reference Phase 135° Relative Switch Component Burst Phase Reference Phase 225° Relative Switch Component
100381_014
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-20. Interlaced 625-Line (SECAM-B, Video Timing (Fields 1-4)
Functional Description
Device Description
RESET* Start VSYNC preceding 4-field sequence
Analog FIELD
Analog FIELD
DRDB
DRDB
Analog FIELD
DBDR
DBDR
Analog FIELD
DRDB
NOTE(S): color subcarrier signal sequences over four consecutive fields shown above. color subcarrier frequency 4.406250 MHz. color subcarrier frequency 4.250000 MHz.
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Functional Description
Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.26 Subcarrier Generation
device uses 32-bit-word synthesize subcarrier. value subcarrier increment required generate desired subcarrier frequency found with following equations: NTSC: MSC[31:0] int((455/(2*H_CLKO)) *232 0.5) PAL: MSC[31:0] int((1135+1/625)/H_CLKO)*232 SECAM: MSC_DB[31:0] int((272/(2*H_CLKO)*232 0.5) MSC_DR[31:0] int((272/(2*H_CLKO)*232 0.5) where:H_CLKO number output clocks/line (this register 0x76 nibble 0x86). This allows generation desired subcarrier desired video standard. 32-bit subcarrier increment must loaded serial interface before subcarrier enabled. device reset disable chroma until last byte 32-bit increment loads, which time chroma enabled, unless DCHROMA set. order prevent residual errors from accumulating, subcarrier (Discrete Time Oscillator) reset every four fields NTSC formats every eight fields formats. best quality SECAM, DIS_SCRST should preventing subcarrier phase reset beginning each color field sequence. Furthermore, SECAM subcarrier generated lines 23-310 336-623 automatically unless disabled PROG_SC bit.
1.3.27 Subcarrier Phase Reset/Offset
order maintain correct SC-H phasing, subcarrier phase degrees leading edge analog vertical sync every four (NTSC) eight (PAL) fields, unless DIS_SCRST (bit four register 0xA2) logical This true both interlaced noninterlaced outputs. subcarrier phase adjusted from nominal degrees phase PHASE_OFF[7:0] register, where each change corresponds 360/256 1.406 degrees change phase. Setting DIS_SCRST useful situations where ratio CLK/2 HSYNC* edges color frame noninteger, which could produce significant phase impulse resetting
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
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