1394B Interface Link Backward compatible with 1394A 800Mb/s Support SB

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1394B Interface Link Backward compatible with 1394A 800Mb/s Support SB

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OXUF922 DATA SHEET
1394B Interface Link Backward compatible with 1394A 800Mb/s Support SBP2 Mastering USB2.0 Link Layer Backward Compatible with USB1.1 480Mb/s Support Bulk Transfer Slave receiver 100MHz interface Full support Drives support large drives Full Master Slave support Supports Data Rates 80MBytes/s Simple master scheme accelerator Groups orbs provides high speed response hard coded commands High-Performance, Power ARM7TDMI Processor 50MHz Clock Rate 32Bit 8KByte Closely Coupled 12Mb/s Async UART Extended 128Byte Buffer Local Support Generic support external peripherals GPIO pins Programmable 6KByte Cache 1394 data 0.18µm advanced CMOS process LQFP VFBGA Supply Voltage 3.3V 0.3V Core Supply Voltage 1.8V 0.15V
OXUF922 combined USB2.0 1394B bridge device based SRAM architecture. Optimised performance OXUF922 flexible ARM7 embedded processor, which programmed next generation Computer Peripheral Consumer Applications. 1394B USB2.0 Apple Storage Devices HDD, DVD, Tape Dual Combinations above. Consumer Appliance (STB, PVR) Storage solutions DVD. Digital Camera Companions Digital Camcorder Storage Devices Advanced Compressed Audio Players (MP3) Printers Scanners 1394B Raid Array with UART Back-channel monitor support. embedded ARM7TDMI processor enables innovative products supported through custom firmware development. Program code programmed `In-System' through 1394 port simplifying manufacture. 1394 Link supports Beta Phys fully backward compatible with earlier 1394 standards. Link interface supports data rates S800 (800Mb/s) rich complement 1394 second layer functionality. OXUF922 fully supports 1394 Peer-To-Peer operation enabling PC-less communication over 1394 file copying manipulation. addition OXUF922 backward compatible with Oxford FW900 FW911 enabling limited Peer-To-Peer operation SBP2 mastering 1394 bus. OXUF922 data accelerator which, without processor intervention, significantly increases performance bridge device when transferring many small files.
Oxford Semiconductor Ltd. Milton Park, Abingdon, Oxon, OX14 4SH, Tel: (0)1235 824900
Oxford Semiconductor 2002 Template: DS_C018A DATA SHEET. CONFIDENTIAL.
OXFORD SEMICONDUCTOR LTD.
OXUF922
CONTENTS
OXUF922 DESCRIPTION.5
BLOCK DIAGRAM
3.2.1
INFORMATION DESCRIPTIONS
CONFIGURATION REQUIREMENT. POWER RESET SEQUENCE LOCKUP HAZARD. FUNCTIONAL MODES EXTERNAL DEVICES REQUIRED
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3.1 5.5.1 5.6.1 5.6.2 5.7.1 5.7.2 5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.9.1 5.9.2
MEMORY ORGANISATION.17
MEMORY ORGANISATION. REGISTER BASE ADDRESSES HARDW DEVICES CLOCK BLOCK CLOCK CONTROL REGISTERS SERIAL REGISTER UTMI REGISTER CLOCK STOP REGISTER CLOCK START REGISTER. STATIC CONTROLLER. REGISTER STATIC BANK REGISTERS EXAMPLE TIMING WITH WAIT STATES GENERAL ADDRESS DECODING ADDITIONAL FUNCTIONS BLOCK. BLOCK DESCRIPTIONS REGISTER SUMMARY. INTERRUPT OPERATION. INTERRUPT MAPPING. WATCHDOG TIMER. WATCHDOG TIMER ATION 0X0A000380 PERIOD COUNTER TIMERS. OVERVIEW. TIMER OPERATION GPIO BLOCK. OVERVIEW. GPIO DATA REGISTER LOCATION 0X0A0003C0 GPIO OUTPUT ENABLE REGISTER LOCATION 0X0A0003C4 GPIO INTERRUPT ENABLE (MASK) REGISTER LOCATION 0X0A0003C8. GPIO INTERRUPT EVENT REGISTER LOCATION 0X0A0003CC GPIO MULTIPLEXING RESET CONTROL OVERVIEW. BLOCK RESET MAPPING LOCATION 0A000340.
FUNCTIONS.18
UART.32 INTERFACE PERIPHERAL FUNCTIONS
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Data Sheet
OXFORD SEMICONDUCTOR LTD.
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4.1 7.5.1 7.5.2 7.5.3 7.5.4 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.11 7.11.1 7.11.2 7.11.3
OXUF922
ENGINE. BLOCK. BYPASS. MAPPING. OPERATION BYPASS CONFIGURATION BYPASS CONTROL STATUS CONFIGURATION PARAMETERS TIMING PARAMETERS. BYPASS LIMITATIONS. BYPASS MODE STREAMING IMPLEMENTATION LINK-CORE. REGISTER FIFO MANAGER. DATA PLANE CONTEXT SLAVE UNITS INTERFACE REGISTER CO-PROCESSOR. QUEUE SELECTOR. ASYNC ENGINE. USB2 CORE. SERIAL CONTROLLER. SERIAL ADDRESS CONTROL REGISTER LOCATION 0X0AA00000. SERIAL READ DATA REGISTER LOCATION 0X0AA00004 SERIAL SOFTWARE CONTROL REGISTER LOCATION 0X0AA00008 SERIAL CONTROL SOFTWARE REGISTER LOCATION 0X0AA0000C SERIAL AUDIO. REGISTER FEATURE LIST LIMITATIONS
11.1 11.2
FORCE FLASH 1.1.58 OPERATING CONDITIONS.60 ELECTRICAL CHARACTERISTICS PHY-LINK INTERFACE TIMING DIAGRAMS.62
MODE MODE
14.1 14.2
EXTERNAL TIMING DIAGRAMS.64 POWER CONSUMPTION.68 PACKAGE INFORMATION
LQFP PACKAGE PACKAGE.
ORDERING INFORMATION.71
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
REVISION HISTORY
0.10 0.11 0.12 DATE 15/4/02 29/4/02 23/7/02 29/7/02 19/9/02 6/11/02 11/11/02 18/11/02 19/11/02 20/11/02 06/12/02 REASON CHANGE SUMMARY CHANGE Output drive strengths added. Package drawing clarified active polarity (FFLASH) changed added reset info Added VFBGA info. 1394 Link timings updated. Revision updated Added clarification PLL_TEST PLL_EN pins. Front page updated Added block descriptions register details General formatting changes, addition related functions registers Added Static Interface details timing Added bypass details Final review. Missing references fixed. GPIO tables fixed First Release more detail into sections Link-Core, FIFO Manager., 7.10 Serial Controller 7.11 Serial Audio.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
OXUF922
Description OXUF922 combined USB2.0 1394 bridge device. 1394 Link supports PHYs fully backward compatible with earlier 1394 standards. OXUF922 also includes on-chip USB2.0 allowing 480Mb/s data transfer. 1394 Link interface supports data rates S800 (800Mb/s) rich complement 1394 second layer functionality. OXUF922 fully supports 1394 Peer-To-Peer operation enabling PC-less communication over 1394 file copying manipulation. chip data accelerator which, without processor intervention, significantly increases performance bridge device when transferring many small files, frees processor other tasks. OXUF922 integrates ARM7TDMI operating with closely coupled zero wait state 2Kx32 SRAM provided local program, stack data storage. closely coupled supports byte, word quadlet access. embedded ARM7TDMI processor enables innovative products supported through custom firmware development. Program code programmed `In-System' through 1394 port simplifying manufacture. combining ARM7TDMI processor core with on-chip SRAM wide range peripheral functions including timers, serial communication controllers Oxford Semiconductor extensive knowledge 1394 applications OXUF922 provides highly flexible cost-effective solution many compute-intensive applications requiring connectivity storage normal micro-controller features. Development Support OXUF922 supported open source compiler (GCC) coupled with free UNIX environment (Cygwin) enable compiling debugging software. Free Uploader software allows quick easy method uploading software device in-circuit.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
Block Diagram
ATA/ATAPI
Fifo/Queue Manager
USB2.0 CORE
Reference Peripheral
Serial Audio
Serial
MISC
control FIFO pointers Fill level information Unified memory architecture:
BRIDGE
SERIAL
UART
Async Engine
ASYNC ENGINE
1394
1394 Link Layer
Processor
Queue Selector
7TMDI
SCRATCH
STATIC CONTROLLER
External STATIC
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
INFORMATION
PLL_EN PLL_TEST LREQ LINKON PINT TEST0 TEST1 TEST2 USB_IND CGND CVDD A1VDD33 A1GND A2VDD33 A2GND REXT RPU_EXA UVDD33 UGND UGND FSDP HSDP HSDM FSDM UGND UGND UVDD33 RESET# CGND CVDD CS2# OGND OVDD
VCOIN CPOUT PLL_VDD PLL_GND OVDD XTLO CLK_48M OGND IVDD PCLK IGND LCLK CVDD CGND CTL0 CTL1 OVDD OGND OVDD OGND SOUT GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
OXUF922-LQ-B
Data Sheet
IGND IVDD CS0# CS1# CGND CVDD OGND OVDD INT# CGND CVDD
PHY_SEL BUS_SEL DMACK# IORDY DIOR# DIOW# DMARQ ID15 ID14 CGND CVDD OVDD OGND ID13 ID12 IDE_OE# ID11 OVDD OGND ID10 CGND CVDD ICS0# ICS1# INTRQ IRESET FFLASH
Figure LQFP Information
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OXFORD SEMICONDUCTOR LTD.
OXUF922
GND:
STATIC_ STATIC_ STATIC_ Z_RESE Z_CS2
FSDM
UGND:
REXT
A1GND:
GND:
TESTPIN
PINT
LREQ
CPOUT
STATIC_
VDD:
STATIC_ STATIC_ STATIC_
GND:
UGND:
UGND: A2GND:
VDD:
TESTPIN LINK_O
VDD:
STATIC_ STATIC_
STATIC_
UVDD:
HSDM
HSDP
UVDD:
A2VDD:
USB_IN
VCOIN
XTLO
STATIC_ STATIC_ STATIC_
VDD:
UGND:
FSDP
RPU_EN TESTPIN PLLTES A1VDD:
GNDP:
VDD:
VDD:
STATIC_
GND:
STATIC_
GND:
CLK_48
VDDP:
LCLK
STATIC_ STATIC_ STATIC_ STATIC_ Z_CS0 Z_CS1
VDD:
IGND:
PHY_CL K_1394
CTL0
GND:
VDD:
STATIC_ STATIC_ Z_WE Z_OE
CTL1
GND:
STATIC_ STATIC_ STATIC_ STATIC_
GND:
VDD:
STATIC_ STATIC_ STATIC_ STATIC_
GND:
VDD:
GND:
STATIC_
VDD:
STATIC_
OXUF922-VB-B
Z_CTS
STATIC_ STATIC_ STATIC_ STATIC_
GPIO_1 GPIO_6
Z_RTS
SOUT
STATIC_ STATIC_ Z_INT
GND:
GND:
IDE_D5
VDD:
IDE_D12
VDD:
IDE_D0
GPIO_2
GPIO_5
GPIO_7
STATIC_
VDD:
IDE_Z_C
IDE_A0 IDE_D8 IDE_D10 IDE_D11 IDE_D2
VDD:
IDE_Z_D MACK
GPIO_0
GPIO_4
STATIC_
IDE_RES IDE_A2
IDE_D7 IDE_D9
GND:
IDE_Z_O
GND:
IDE_D14
IDE_DM IDE_IOR BUS_SE
GPIO_3
Z_FORC IDE_INT IDE_Z_C IDE_A1 E_FLASH
VDD:
IDE_D6
IDE_D4
IDE_D3 IDE_D13 IDE_D1
GND:
IDE_D15 IDE_Z_D IDE_Z_D A_B_PH Y_SEL
Figure VFBGA Information (Top view)
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
DESCRIPTIONS
VFBGA K14,K15,J15, J14,H12,H15 G15,G12 G13,F15 C5,B5,A3,B4, A2,B3,D3,C2 C5,B5,A3,B4, B3,D3,C2 B4,A2,B3,D3, B1,C1,D2,D1, E4,E2,F4,F3 H3,H2,H1,H4, J4,J1,J3,J2,K 4,K2,L1,L4,L3 ,M1,L2,N1,P1 A4,F2,F1 Type1 Name PD[7:0] Description Phy-Link Data
LQFP 1394 LINK 93,94,97-100,103,104
105,106 STATIC 153-158,1,2 153-157 158,1,2 156-158,1,2 3-7,10-12 19-27,30-37
T_B_8 T_O_8
CTL[1:0] PCLK LREQ LINKON LCLK PINT D[15:8] TDI,TDO, TMS, TCK, TRST A[19:17] A[21:17] D[7:0] A[16:0]
Phy-Link Control 49.152 (A)/ 98.304 clock sourced Link Request Requests link power when power mode Indicates that link powered ready Only PCLK returned Only Interrupt Static external upper data when TEST[2:0] JTAG when TEST[2:0] =001 Extended Static external address when TEST[2:0] =001 Extended Static external address when TEST[2:0] =101 Static external lower data Static external address
152,14,13
T_O_8 T_O_8 T_O_8 T_B_8 T_B_8
CS#[2:0] INT# CLK_50 BUS_SEL
Static external chip selects. CS0# always used Flash. External utput enable. Active when reading data from external devices including Flash Write Enable. Active when writing external devices External interrupt Defined input default 50MHz clock output function controlled firmware High external Flash device, external Flash device High Speed Data+ Connect line High Speed Data Connect line fixed reference bias current pin. Connect ground external resister Rext 12.5K Full Speed Data Connect line external resister Full Speed Data Connect line external resister
USB_B USB_B USB_O USB_B USB_B
HSDP HSDM REXT FSDP FSDM
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
USB_O RPU_ENA
OXUF922
mode chirp mode, this supply external resister (1.5K operation, tri-stated. data
73,71,65,63,60,56,54,52, 49,53,55,57,61,64,68,72
46,48,47 44,45 UART MISC 129-127
R12,P10,R9, M9,N8,N7,P6, N6,P5,R6,M7, R7,R8,N9,R1 0,M11 P4,R4,N5 N4,R3 D11,A12,B12
T_B_4
ID[15:0]
T_O_4 T_O_4 T_O_8 T_O_4 T_O_4 T_O_4 T_O_4 T_B_4 T_B_4 T_B_4 T_B_4 T_B_4 T_B_4 T_B_4 T_B_4
IA[2:0] ICS#[1:0] IDE_OE# IRESET DMARQ DIOW# DIOR# IORDY DMACK# INTRQ SOUT RTS# CTS# XTLI XTLO PLL_TEST PLL_EN VCOIN CPOUT GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO TEST[2:0] RESET# FFLASH PHY_SEL USB_IND
address chip select. Selects drive output enable. Only used when external buffering required drive data interface reset interface write strobe interface read strobe
Transmitter serial data output. Active-low Request-To-Send output. Receiver serial data input. Active-low Clear-To-Send input. input from crystal crystal oscillator) output Test Enable (tie normal operation) Enable (tie high normal operation) Loop filter Loop filter General purpose DTR# Serial Audio driver word General purpose DSR# Serial Audio driver data General purpose DCD# Serial Audio driver General purpose General purpose General purpose STATIC WE2# (upper byte write enable) General purpose Serial Data General purpose Serial Test pins select functional modes. section Functional Modes Active reset While device configured force_flash mode. Selects Link High indicate
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
Power ground2 18,40,50,69,108,132,151 17,39,51,70,107,131,150 9,29,59,67,96,102,112,1 16,160 8,28,58,66,95,101,110,1 13,159 133,135,139,148 134,136,140,141,146,14
OXUF922
G2,N2,R5,N1 0,F12,B11,D5 G1,M4,M6,R1 1,G14,A11,B6 E1,K3,M8,M1 0,J13,H14,D1 5,B15,B2 E3,K1,P7,P9, J12,H13,F13, E12,A1 D10,C10,C9, A10,B10,A8,B 9,B7,D6
CVDD CGND
digital digital digital digital
1.8V Core voltage
3.3V voltage
UVDD UGND PVDD PGND
3.3V voltage
1.8V voltage
Table Description Note Type (w_) (y)(_z) CMOS levels Tolerance tolerant 3.3V Direction input output Bi-directional Pull-up/down pull-up pull-down none Output drive capability drive drive Dedicated output Dedicated bi-directional 1.8V Digital Core Power Core Ground 3.3V Digital Power Ground 1.8V Digital Core Power Ground 3.3V Analogue Power Analogue Ground
USB_O USB_B CVDD CGND PVDD PGND UVDD UGND
Note Power ground Separate supplies recommended digital analogue power supplies.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
Configuration Requirement
HSDP RPU_ENA
DRs'
FSDP FSDM HSDM REXT
OXUF922
Rext
XOUT
(Note: Table Description resistor values)
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
Power reset sequence
OXUF922 Requires reset timing follows:
PWR_GOOD PLL_EN nRESET
oscillator needs time stabilise before OXUF922's enabled pulling high PLL_EN). time required from power being stable (within limits) oscillator stabilize. >2mS. This minimum delay required lock. must locked prior taking OXUF922 reset.
OXUF922 Enable Reset inputs have Schmitt type inputs allow delay elements shown example below.
VCC3V3
PLL_EN
PWR_GOOD
nRESET
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
calculating values `PWR_GOOD' assumed open drain output from local power conditioning circuitry that sink least with output voltage 0.3v thereby setting nearest convenient value). this example requirement 40mS (the actual requirement will depend oscillator used which application dependant.) lowest value input high voltage OXUF922 Schmitt inputs Volts (Min Hysteresis Using ln[(Vaim Vstart)/(Vaim Vth)]) Calculate value given 50mS Vaim (Supply voltage) Vstart (PWR_GOOD Output Low) (Input high voltage) Gives 224K therefore 220K nearest standard value. When tolerances, thresholds supply range accounted for, +20%, +5%, Vaim 3.0, becomes calculate values given 1uF. -20% 52mS Vaim (Supply voltage) Vstart (PWR_GOOD Output Low) (Input high voltage) Gives 291.3K therefore 330K standard values account tolerance pull-up will extend these times slightly insignificant compared capacitor tolerance.
VCC3V3 PLL_EN
MAX809
nRESET
nRESET
ohms 330nF makes 4.5mS.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
determined from minimum threshold 0.9V, starting 0.3v. making large enough load output 69K. This leads value 240nF. This been rounded 330nF nearest standard value provides some margin. MAX809 provides reset pulse 140mS, easily accommodating requirements MAX809? reset controller defined this circuit because using requires knowledge user systems power supply characteristics, specifically supply rise time.
3.2.1
Lockup Hazard
OXUF922 /PHY combination powered attached 1394 bus, there potential hazard where OXUF922 misses node from hence fails operate correctly. This only issue when trying access flash port when firmware loaded. When firmware loaded first things does cause reset which sorts everything out. Avoidance action: Ensure OXUF922 comes reset before PHY.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
Functional Modes
Description Normal mode data bus, 128Kbyte address range JTAG bond upper data bus, data only, 1Mbyte address range 1394 Only, clock source required Reserved Reserved Extended address upper data bus, data only, MByte address range Reserved Reserved
Test Mode1
Notes Test Mode TEST [2:0] pins
External Devices Required
8/16-bit Flash crystal oscillator (and system clock). 1394 corresponding crystal.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
MEMORY ORGANISATION
Memory Organisation
Base Address 0x00000000 0x01000000 0x02000000 0x03000000 0x04000000 0x05000000 0x06000000 0x07000000 0x08000000 0x09000000 0x0A000000 0x0B000000 0x0C000000 0x0D000000 0x0E000000 0x0F000000 0x80002000 Decode Size (Bytes)
Block External Chip Selects Repeat above Repeat above Repeat above Unused Unused FIFO Manager UART Unused Unused Logic Registers Logic Registers (Repeat) Unused Unused Static Unused SCRATCH Base address
Register Base Addresses Hardware Devices
Base Address (31:16) 0x0000 0x0040 0x0080 0x00C0 0x0700 0x0A00 0x0A10 0x0A20 0x0A28 0x0A30 0x0A40 0x0A50 0x0A60 0x0A70 0x0A80 0x0A90 0x0AA0 0x0AB0 0x0AC0 0x0AD0 0AF0 0x0E00 Location section Static Controller section Static Controller section Static Controller section UART section Block section Link-Core section Async Engine section Queue Selector section USB2 core section FIFO Manager. section Engine section Block section Co-Processor. section 7.10 Serial Controller section Clock Block section 7.11 Serial Audio section Static Controller
Block Chip Select address (External Flash) Chip Select Chip Select used UART Link Async Engine Queue Selector FIFOMAN used used serial control clock control Serial Audio used Static Registers
Note register repeats, only bits 27:24 decoded
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
FUNCTIONS
Clock Block
clock block contains clock generation gating logic required. There four registers allow control serial clock, clock suspend power saving control stop start controls clocks majority logic. addition stopping clocks also possible slow logic clocks, except clock half speed. This done start stop registers. table below details which clocks what speed, which controllable their state after reset. normal application device would have source being used system clock clock, separate crystal being used 1394 PHY. There additional mode where 1394 clock used replace MHz, this then precludes USB. section Functional Modes details assignment this. Block Fifoman Fifoman master function Static Serial UART UART sys_clk Link Async Queue subsys Serial Audio Frequency (MHz) Clock Stop Reset Value Stopped Stopped Stopped Stopped Running Stopped Stopped Stopped Running Running Stopped Stopped
Data Sheet
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OXUF922
5.1.1
Clock Control Registers
Offset Reset value 0x020 0x01 0x01DC 0x01DC Description Divider value generate serial clock UTMI clock enable (1=enabled) Write stop various clocks Write start various clocks
Clock control registers found starting location 0AB00000 Register Serial Control UTMI Control Clock Stop Clock Start
5.1.2
31-8
Serial Register
Serial frequency (MHz) 1024 reserved Reset read value
select serial frequency when using serial controller
5.1.3
UTMI Register
Writing this register will enable disable UTMI PHY's clock. This used conjunction with suspend indication core into power save mode. 31-1 UTMI enable enable clk, disable reserved Reset read value
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
5.1.4
Clock Stop Register
Write stop clocks (bits Write slow clocks below half rate (bit Clock Stop 29:9 Clock(s) Link system clock Async clock Queue clock system clock system clock clock system clock clock system clock system clock Static system clock Serial system clock Serial Audio system clock UART system clock UART clock defined Slow clock select Reserved Reset read value started, stopped normal, slow
5.1.5
Clock Start Register
Write start clocks (bits Write return clocks below full rate Clock Start 29:9 Clock(s) Link system clock Async clock Queue clock system clock system clock clock system clock clock system clock system clock Static system clock Serial system clock Serial Audio system clock UART system clock UART clock defined Slow clock select reserved Reset read value started, stopped normal, slow
Data Sheet
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OXUF922
Static Controller
controller supports three chip select banks with independent timing control. This allows external connection flash peripherals OXUF922, chip take responsibility application host. Three separate chip select banks (CS0, CS2). 8bit 16bit memory support (pin select boot, register select cs2) Bank size 4MBytes (A21:0) when chip mode Bank size 1MBytes (A19:0) when chip mode with JTAG debug Bank size 128KBytes(A16:1) when chip mode Programmable burst fetch. Supports external buffer glue-less data expansion. Configurable interrupt input from static peripheral output synchronous peripheral static bus. Second write enable selected used upper byte write enable SRAM static bus.
each chip select bank accessed controlled register. register each bank (address space) controls Whether bus. Note that when mode bank size 4Mbytes, when mode 128Kbytes. delay clocks added strobing after strobes write cycle. number clocks into write cycle that goes high controlled. number clocks write cycle (from 64). number clocks read cycle (from 64). delayed after strobes read cycle. Note: Setting test pins constrain data width connected memory devices, regardless register settings.
5.2.1
Register
addresses stated offset from static controller register base address, 0x0E000000. Address offset from STATIC_REG_BASE 0x00 0x04 0x08 0x0C 0x10 Reset Value 0x00000001 0xXFFFFFFF 0x0FFFFFFF 0x0FFFFFFF Register Version register Static Bank register (Boot Bank) Static Bank register Static Bank register used
Note values Boot bank reset. below.
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
OXUF922
5.2.2
Bits 31:30 27:26 25:24 23:22 21:16 15:14 13:8
Static Bank registers
Name Width Read Burst Enable Buffer Present write_start turn_cycle Reserved write_pulse Reserved write_cycle Delay Reserved read_cycle Reset 111111 111111 111111 Function External memory width "00" 8bit, "01" 16bit, "10" 32bit Enable read bursts speeds access raising between accesses External buffer required this bank number clocks into write cycle that strobes fall. Turn around time clocks. high time. number clocks into write cycle that strobes rise. write_cycle+1 write access Specifies whether should delayed clock from read_cycle+1 read access.
reset value such that memory works slowest possible mode. *The Width configuration boot block BUS_SEL that boot block accessed correctly from reset. This should conjunction with test pins. Section External Timing Diagrams gives examples various configurations.
5.2.3
Example Timing with Wait States
Assuming 8-bit Flash device CS(0), following diagram tables gives example values bank registers depending access time device (tAA).
system
access access overhead (load dependant) device data sampled total access
START
START
START
assert address, wait state, hold sample data, finish access, negate address,
Example with burst enabled
Data Sheet
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OXFORD SEMICONDUCTOR LTD.
system clock (USB and/or 1394) (ns) 15pF load 25pF load 25.4 24.4 46.3 45.3 67.1 66.1 87.9 86.9
OXUF922
Read_cycle
Total Access Time (ns) 32bit Read (ARM) 16bit Read (Thumb) Burst Burst Burst Burst
49.152 system clock (1394 only) (ns) 15pF load 25pF load 24.4 23.4 44.8 43.8 65.1 64.1 85.5 84.5 Total Access Time (ns) 32bit Read (ARM) 16bit Read (Thumb) Burst Burst Burst Burst
Read_cycle
Notes: read_cycle defined bits (5:0) bank register Load seen address, (chip select) (output enable). Affects access overhead. (16.25ns 15pF, 17.25ns 25pF) calculated from read_cycle) system period access overhead. Total access time read_cycle system period number required memory accesses Total access time read_cycle) system period number required memory accesses) system period
5.2.4
General Address Decoding
following address decodes used this block. Note processor must have boot code address 0x00000000. address offset from STATIC_BASE 0x00000000 0x00400000 0x00800000 Block External FLASH chip select External chip select External chip select Function External Flash SRAM Bank
5.2.5
Additional Functions
provide means directly interface external device running synchronously OXUF922, there facility output clock. This controlled from GPIO data register detailed below. Timing diagrams showing timing relationship shown section External Timing Diagrams. Additionally when interfacing 16bit SRAM second write enable maybe required byte write accesses. This function also provided through GPIO register below. GPIO data register location 0x0A0003C0 note this will also control direction change pin. GPIO data Data Sheet Write static_wen(1) onto GPIO(2) SRAM writes output static_clk MHz) (static_int) Read Register write value Register write value Reset value Page
OXFORD SEMICONDUCTOR LTD.
OXUF922
Block
Reference Peripheral provides basic standard peripherals. reference peripheral RPS) intended provide useful common functionality that required many embedded systems. This block implements counter timer, interrupt controller addre controller. These peripherals fully defined ARM's specification. addition these, this includes following extra system peripherals: watchdog timer providing system reset should software hang, software present GPIO controller provide flexible digital Block reset controller which allows individual design sub-blocks reset independently another under software control
5.3.1
Block descriptions
Brief description blocks given below with more detailed descriptions following Interrupt Controller (see section 5.4) interrupt controller provides means which processors enable, disable, clear various interrupts system. actual terrupts seen processor routed from this block. This block also fully specified specification. Watchdog Timer (see section This block provides counter which continually counting (incremen ting every clock cycle). count reset every time register read (returning count immediately prior read), timeout output goes active terminal count ever reached. This timeout used reset system processor. This provides useful facility software crash protection. addition, watchdog timeout modes, Fast (default) slow. fast timeout mode, terminal count 16,384 clock cycles (327uS with 50MHz clock). slow timeout mode (which entered writing special value watchdog register), timeout longer programmable period. (This defined more detail register block description). watchdog switch timeout output programmable output (reset ACTIVE) interfacing "Force Flash" controller. intended cause transition force flash mode watchdog timeout occurs while this set. Programmable Counters (see section 5.7) These programmable 16-bit down counting interval (re-loading) timeout (one-shot) counters used generating timed interrupts processor. These timers fully specified specification. GPIO (see section 5.8) This block provides user I/O. GPIOs programmed inputs outputs. Additionally, inputs cause interrupt upon transition. Each GPIO direction control (output enable), open drain outputs emulated easily setting output value zero, writing inverse data instead output. Block Reset Controller (see section 5.9) This block simply defines writable register which generates several reset outputs which routed various sub-blocks system, order provide more flexible resetting. reset outputs activated global system reset input, setting appropriate reset control register. this case self clearing, reset activated clock cycles.
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Register Summary
BASE
READ
WRITE
Interrupt Control 0x0000 Masked Source Status 0x0004 Source Status 0x0008 Enable Mask 0x000C none 0x0010 none Interrupt Control 0x0104 Masked Source Status 0x0108 Source Status 0x010C Enable Mask 0x0110 none Timer 0x0200 0x0204 0x0208 0x020C 0x0210 Timer 0x0220 0x0224 0x0228 0x022C 0x0230
none none Enable bits Disable bits Software Interrupt
none none Enable bits Disable bits
Timer Load Timer Current Count none Timer Control none Timer Clear none none
Timer Load Timer Current Count none Timer Control none Timer Clear none none
Reset Remap 0x0300 0x0304 0x0308 0x030C 0x0310
none Identification none Reset Status none
Pause none Clear Reset Reset Status Reset Status Clear
Note: Reset Remap registers implemented OXUF922.
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Interrupt Operation
interrupt controller provides means which processor enable, disable, clear various interrupts system. actual interrupts seen processor routed from this block. This block fully specified specification.
5.5.1
Interrupt Mapping
interrupt registers found starting location 0A000000. table below shows OXUF922 interrupt 32-bit assignment Interrupt Controller. Interrupt 16:30 Write Read SERIAL AUDIO Software (SWI) Reserved Reserved Timer Timer Link UART Async FIFOMAN Reserved USBCORE Static GPIO interrupt Reserved Reset value
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Watchdog Timer
This block provides counter which continually counting (incrementing every clock cycle). count reset every time register read (returning count immediately prior read) under normal operation watchdog timer must cleared regular interval. this done timeout output goes active terminal count ever reached. This timeout used reset system processor. This provides useful facility software crash protection providing system reset should software hang. addition, watchdog timeout modes, Fast (default) slow. fast timeout mode, terminal count 16,384 clock cycles (327uS with 50MHz clock). slow timeout mode (which entered writing special value watchdog register), timeout longer programmable period. (This defined more detail register block description below). watchdog switch timeout output programmable output (reset ACTIVE) interfacing "Force Flash" controller. intended cause transition force flash mode watchdog timeout occurs while this set.
5.6.1
Offset 0x0380
Watchdog timer location 0x0A000380
Watchdog Control Register
Number clock cycles sincle last read reset) Timeout
Reading watchdog returns number clock cycles since last time read reset) then resets count. count also reset when timeout occurs, reset input signal asserted. Writing this register with values from 0x1068AFC5 0x1068AFC7 allows bits (according bottom bits value written). Switch timeout intended conjunction with external "Force flash" controller, allowing enter force flash mode upon watchdog timeout when this set. This default. Fast Timeout used cause watchdog timeout after just 16,384 clock cycles. This default state, hence software should clear this soon possible after booting writing 0x1068AFC4)
5.6.2
PERIOD
Writing this register with 0x20D15F89 OR'ed with (timeout allows setting long timeout value `0'). timeouts defined given following table: Timeout (default) Clocks timeout 1024 4096 1024 8192 1024 16384 1024 32768 1024 65536 1024 Reserved Period 50MHz clock 1.34 Undefined
watchdog completely disabled writing value 0x20D15F88. should noted that once watchdog been disabled counter stopped. Writing with timeout value specified above will re-enable watchdog.
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Counter Timers
5.7.1 Overview
OXUF922 timer modules which either programmable 16-bit down counting interval (re-loading) timeout (one-shot) counter used generating timed interrupts processor. Each channel independently programmed perform wide range functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing pulse-width modulation. Each timer wide down counter with selectable pre-scalar. pre-scalar allows either clock MHz) used directly, clock divided used. This provided stages pre-scale. modes operation available, free-running periodic timer. periodic timer mode counter will generate interrupt constant interval. free-running mode timer will overflow after reaching zero value continue count down from maximum value.
5.7.2
Timer Operation
Each timers loaded writing value there respective load register then, enabled setting enable timer control register timer will count down zero. reaching count zero interrupt will generated. interrupt cleared writing respective Timer clear register. After reaching zero count, timer operating free-running mode then timer will continue decrement from maximum value. periodic timer mode selected then timer will reload from load register continue decrement. this mode timer will effectively generate periodic interrupt. mode selected Control register. point current timer value read from Value (Current count) register. timer enabled control register. reset timer will disabled, interrupt will cleared Load register will undefined. mode pre-scale value will also undefined.
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GPIO Block
5.8.1 Overview
OXUF922 user pins provided GPIO block. These pins programmed either inputs outputs. Additionally, when inputs they cause interrupt upon transition. Each GPIO direction control (output enable), open drain outputs emulated easily setting output value zero, writing inverse data (output enable) instead output. interrupt enable mask allows input transition interrupts generated. Setting interrupt mask given input will cause interrupt event flagged interrupt event register every time state that input changes. Setting interrupt mask GPIO which defined output [OE] output enable register) will have affect. Interrupt events read from Input Interrupt events register individual inputs events cleared writing this register with appropriate bits clear event. GPIO internal interrupt will whenever Input Interrupt Events register non-zero (i.e. events set). This interrupt read from interrupt controller same other interrupt, must enabled such order generate actual interrupt CPU. GPIO registers found starting location 0x0A0003C0 Register GPIO data GPIO output enable GPIO Interrupt enable mask GPIO Interrupt event Offset Reset value Description This allows setting reading GPIO pins. Additional functions related GPIO controlled here. GPIO direction setting This allows GPIO inputs used interrupts, enabling ones required. Interrupt status clear register
5.8.2
GPIO Data Register location 0x0A0003C0
Write Output value multiplexing control below section 5.8.6 static_wen(1) onto GPIO(2) SRAM writes Output static_clk MHz) (static_int) Reserved Read value setting A_B_PHY_SEL USB_IND BUS_SEL TEST0 TEST1 TEST2 Register write value Register write value Reset value specific specific specific specific specific specific specific
GPIO data 10:8 31:19
5.8.3
GPIO Output Enable register location 0x0A0003C4
This register determines whether GPIO will input output dependent what written example Write value register GPIO Write output enable (oen), input, output Read write value Reset value
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5.8.4
GPIO Interrupt Enable (mask) register location 0x0A0003C8
value written this register determines whether corresponding input will generate interrupt when transition occurs input. Setting interrupt mask given input will cause interrupt event flagged interrupt event register every time state that input changes. seen important that value used here corresponds value loaded into GPIO Output Enable register. GPIO interrupt enable mask Write interrupt enable (int en), interrupt, enable interrupt Read write value Reset value
5.8.5
GPIO interrupt event register location 0x0A0003CC
This register used read from determine which input generated interrupt. Conversely this register then written appropriate bits clear interrupt(s). GPIO interrupt mask Write effect, clear interrupt Read interrupt, interrupt event Reset value
5.8.6
GPIO Multiplexing
setting gpio_data bits GPIO pins reconfigured other functions detailed below. Note only GPIO always GPIO pin. GPIO data(10:8) GPIO(7) GPIO GPIO Serial Audio_word Serial Audio_word GPIO(6) GPIO GPIO Serial Audio_data Serial Audio_data GPIO(5) GPIO GPIO Serial Audio_clk Serial Audio_clk GPIO(4) GPIO GPIO GPIO GPIO GPIO(3) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO(2) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO(1) GPIO serial_data GPIO serial_data GPIO serial_data GPIO serial_data GPIO(0) GPIO serial_clk GPIO serial_clk GPIO serial_clk GPIO serial_clk
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Reset Control
5.9.1 Overview
reset strategy divided into three sections, firstly synchronisation system reset, secondly reset control ARM, thirdly control resets each major block logic. system reset asynchronous synchronised internal clock before being distributed around chip. When force flash mode, setting device reset force flash port will generate sync reset, causing chip come force flash mode negating reset. negation sync reset enables counter which times brings reset. This ensures that system interfaces stable prior start code execution. also reset watchdog timeout exiting force flash mode, both events also kick timer. sync reset used block reset controller which allows software control resets major logic blocks detailed below. This function found block.
5.9.2
Block Reset Mapping location 0A000340
block reset register found starting location 0A000340. Writing relevant generates cycle reset pulse MHz. Block reset 31:14 Write Read Reserved Static Link core Async_engine queue selector FIFOMAN Reserved core Serial UART Serial Audio Reserved Reset value
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UART
UART operates synchronous mode only clocked clock. Note: exact frequency will either 49.152 depending configuration. UART based UART with receive transmit FIFO's 128x8 deep. internal UART located address 0x07000000. following pins permanently available chip I/O, SIN, SOUT, RTS. information UART refer Oxford products incorporating UART's. Indexed Control Register Register pidx Offset from 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 UART Registers Register Address Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
offset column indicates value that must written into prior reading writing Indexed Control Registers ICR.
UART Registers Register Xon1 Xon2 Xoff1 Xoff2 Address Offset 0x02 0x04 0x05 0x06 0x07
UART Registers Register Address Offset 0x00 0x03 0x04 0x05
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hardware flow control required then there GPIO pins available this. (DTR, DSR, GPIO data(10:8) GPIO(7) GPIO GPIO Serial Audio_word Serial Audio_word GPIO(6) GPIO GPIO Serial Audio_data Serial Audio_data GPIO(5) GPIO GPIO Serial Audio_clk Serial Audio_clk GPIO(4) GPIO GPIO GPIO GPIO GPIO(3) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO(2) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
OXUF922
GPIO(1) GPIO serial_data GPIO serial_data GPIO serial_data GPIO serial_data
GPIO(0) GPIO serial_clk GPIO serial_clk GPIO serial_clk GPIO serial_clk
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INTERFACE PERIPHERAL FUNCTIONS
Engine
OXUF922 includes single-channel high speed controller supporting requesting sources. controller capable transferring 32-bit data between FIFO manager blocks. registers found starting location 0x0A600000 Register control status Register base source address register base destination address register byte count register current source address register current destination address register current byte count register Offset Reset value Description below Holds base-Source address transfers Stores current Source address transfer. This value transfer-width aligned incremen number bytes transferred cycle fixed. Holds Destination-base address transfers Stores current destination address transfer. This value transfer-width aligned increment number bytes transferred cycle fixed. below Indicates number bytes read from source point during current transaction. byte aligned decrements each cycle number bytes transferred. Indicates number bytes read from source. below
interrupt register version
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Control status Register FAIR_SHARE_ARB DMA_IN_PROGRESS SFT_S_DREQ
SFT_D_DREQ
NEXT_FREE
14,13
CH_RESET DIRECTION
INC_ADDR_S
INC_ADDR_D
21-19
MODE_A MODE_B DEVICE_TYPE_S
Indicates which Stage channel belongs Stage higher group (reset value) Stage lower group This indicates channel idle not. idle. busy, transfer completed (current-byte-count zero). uses these bits indicate valid source request channel. always reads from source. 0000: req0 (reset value) 0001: req1 0010: req2 1111: memory uses these bits indicate valid destination request channel. always writes destination. 0000: req0 (reset value) 0001: req1 0010: req2 1111: memory When interrupt enabled, indicates completion transfer (when current byte count register zero). This cleared when writes BYTE_COUNT register transfer BASE_X_ADDR registers expecting transfer). When high, this indicates that address- byte-count registers ready programmed. DMA-controller will this high after loads current registers. deactivates when writs BYTE_COUNT register. Setting this will disable next bus-cycle transfer reset channel. Minimum pulse Width High 30ns Hclk) .CPU needs back when starting transfer. Indicates data transfer direction between interfaces DMAcontroller always reads from source writes destination. Source Destination (reset value) Source Destination Source Destination Source Destination Determines whether Source address will fixed incremented during transfer. Fixed address during transfer, only lowest 4-bits will increment (reset value). Address will increment current byte count increments. Determines whether Destination address will fixed incremented during transfer. Fixed address during transfer, only lowest 4-bits will increment (reset value) Address will increment current byte count increments. Determines data transfer mode Interface Single transfer mode (reset value) Burst transfer mode. Determines data transfer mode Interface Single transfer mode (reset value) Burst transfer mode. This determines maximum data transfer width source device. Page
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000: 8-bits Device (reset value) 001: 16-bits Device 010: 32-bits Device Others: Unused. This determines maximum data transfer width destination device. 000: 8-bits Device (reset value) 001: 16-bits Device 010: 32-bits Device Others: Unused. Writing this will pause next bus- cycle transfer, until zero. Setting this will disable interrupt this channel. Reset value "1". reset value, effect, Source address really fixed (all bits); must `0'. reset value, effect, Destination address really fixed (all bits); must `0'. reset value Starve priority channels. priority channels executed when high priority requesting. cleared software when needed. Writing these bits effect. Read will return zeros.
24-22
DEVICE_TYPE_D
PAUSE_DMA INT_ENABLE FIXED_ADDR_S FIXED_ADDR_D STARVE_LOW_PRIO
31-30
UNUSED
Byte count register (Byte_count_size RD_EOT WR_EOT BYTE_COUNT Setting this will enable read transfer signal this channel. Reset `0'. Setting this will enable write transfer signal this channel. Reset `0'. Byte_count_size programmable. Byte_count holds block size bytes next transfer.
Channel Interrupt Register DMA-version Channels 23-16 31-24 INT_REG NUM_OF_CH Version Indicates what channel interrupting, where zero indicates channel zero, channel etc. Returns number channels. Highest 8-bits version number 0x01.
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Block
ATA(PI) controller core dedicated hardware block performin function controlling devices, either ATAPI. core provides full interface, core communication interface high speed data interface. Commands sent attached devices form SBP-2 compliant ORBs, interface. data associated with command transferred from device either interface. core responsible protocols, data transfers commands handling ATAPI device, fully compliant with mandatory features ATA/ATAPI-6 spec. addition interfacing drives, core contains bypass mode which allows systems engine interface with external capable device such SCSI controller. This interface uses almost same pins interface does (see section Bypass). Register ORB1 ORB2 ORB3 ORB4 Command Status Command Status Ctrl Burst buffer port RBC1 RBC2 RBC3 access Interrupt status Interrupt enable Interrupt enable clear Interrupt enable Version Burst Buffer Control Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x34/8 0x3C 0x48 Description First four registers used write ATA/ATAPI commands into device Second four registers used write ATA/ATAPI commands into device Third four registers used write ATA/ATAPI commands into device Fourth four registers used write ATA/ATAPI commands into device Contains command status information MASTER device Contains command status information SLAVE device present) Provides interface setting core operation parameters read write access FIFO First three registers used write CDBs into device that require translation. Second three registers used write CDBs into device that requires translation. Third three registers used write CDBs into device that require translation. Direct register access Read determine interrupt status, write clear active interrupt Active high interrupt enable register write only Active high interrupt enable clear register write only Active high interrupt enable register read only Read only version register Software force complete transfer when required
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Bypass
Bypass function allows specific protocols bypassed, which allows engine burst buffer FIFO pins block drive external bus. used variety different modes enable interfacing various external peripherals controllers. Master FIFO control. master Bypass Control drives transfers peripherals. quadlet deep FIFO Programmable control signal polarity. Programmable parity. Programmable strobe timing. Configurable data size Asynchronous interface. Single, burst continuous transfer modes. main compatibility modes, Am53CF94/6 compatible mode.
Engine
DREQ /DACK
Core
STATIC
/DMARD /DMAWR 8/16 data parity
External Engine Peripheral
Control
7.3.1
Mapping
Name ID[15:0] ICS#[1:0] DMARQ DIOW# DIOR# DMACK Bypass data(15:0) parity(1:0) DREQ DMAWR DMARD DACK
number 44,45
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7.3.2
Operation
transfer started External Peripheral asserting DREQ. This acknowledged OXUF922 asserting /DACK. Reads (data being transferred OXUF922), peripheral drives data onto Data lines this latched into edge /DACK /DMARD being de-asserted. Writes (data being transferred from OXUF922), data driven onto data lines OXUF922 should latched into peripheral edge /DMAWR being de-asserted. There types operation that used `Valid DREQ' `Start DREQ'. former mode requires DREQ asserted whole transfer. DREQ goes inactive during transfer, transfer data suspended until asserted again. `Start DREQ' mode requires DREQ asserted only until transfer starts. operation /DACK signal determined DACK type selected. completes, follows active strobe signal. either remains asserted until transfer
Bypass mode entered setting enable bypass config register. This disables specific blocks, multiplexes pins allow engine pass data through burst buffer external capable device engine receive data from external device through burst buffer. many parameters associated with timing configuration interface controlled through bypass configuration register. Once core engine have been configured, start bypass control register allow data transfers proceed. size transfer controlled engine. Once transfer completed interrupt shall generated.
Bypass Registers
Address Offset 0x40 0x44 Name Description Bypass Configure bypass control match external interface chip Configuration Bypass Control Write only start bypass transfer
7.3.3
Bypass Configuration
Address Name 0x40 Read /Write Bypass Config parameters section 7.3.5 Configuration Parameters Bits Description Direction: DMA_IN, DMA_OUT Parity: parity, Even parity Data bus: bus, Byte lane: upper byte lane, lower byte lane dreq_lvl: active low, active high dack_lvl: active low, active high dmard_lvl: active low, active high dmawr_lvl: active low, active high dma_type Valid Dreq, Start Dreq dack_type: cselect, strobe 15:10 Burst size 18:16 tsaw 21:19 tsnw 24:22 tndack 27:25 tsndn 30:28 tdacks enable Data Sheet Page
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7.3.4
Bypass Control Status
Address Name 0x44 Read/ Write Bypass Control status Bits 31:3 Description Start start transfer from external interface self-clearing bit. Write only Parity Error Read only Dreq resampled Dreq Read only Reserved (0x000000)
7.3.5
Configuration Parameters
Setting DMA_IN Byte Upper High High High High Valid Dreq Chip Select DMA_OUT Even Word Lower Start Dreq Strobe Default DMA_IN Word Upper High Valid Dreq Chip Select
Parameter Direction Parity Data Byte Location Dreq active level Dack active level Dmard active level Dmawr active level Type note Dack Type note Burst Size note
Notes: Type Start Dreq only requires Dreq asserted until transfer starts. transfer shall only valid burst sizes transfers. allowed continuous transfers when burst size Valid Dreq requires Dreq remain asserted validate transfer. during strobe Dreq negates, that transfer remains valid, state machine must Dreq asserted again before more strobes will generated. Continuous transfers only. Dack Type Chip Select type causes Dack signal remain asserted until transfer completes. Strobe type caused Dack signal follow active strobe signal. Burst Size continuous transfer, transfers started stopped Dreq. Must Valid Dreq Type. number transfers assertion dreq. Must Start Dreq Type.
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7.3.6
Timing Parameters
Symbol tSAW tSNW tNDACK tSNDN tDACKS Option Notes clk_period (tSAW+1) clk_period (tSNW+1) clk_period (tNDACK+1) clk_period (tSNDN+1) clk_period (tDACKS+1)
Parameter Strobe Active Width Strobe Negated Width Dack Negated Dack Active Strobe Negated Dack Negated Dack asserted Strobe asserted Dack_type=CSELECT only
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Am53CF94/6 Compatible Read Byte Control
DREQ tSAW tSNW
/DACK
DATA
Bypass Configuration Parameters: Direction DMA_IN, Parity Odd, Data_bus Word, Dreq_lvl High, Dack_lvl Low, Mode Valid DREQ, DACK Mode Strobe, Burst Size
Am53CF94/6 Compatible Write Byte Control
DREQ tSNW
/DACK tSAW
/DMAWR
DATA
tSNW Bypass Configuration Parameters: Direction DMA_OUT, Parity Odd, Data_bus Word, Dreq_lvl High, Dack_lvl Low, DMAWR_lvl Low, Mode Valid DREQ, DACK Mode Strobe, Burst Size
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Am53CF94/6 Compatible Read with Byte Control
DREQ tSAW tSNW
/DACK
/DMARD
DATA
Bypass Configuration Parameters: Direction DMA_IN, Parity Odd, Dreq_lvl High, Dack_lvl Low, DMARD_lvl Low, Mode Valid DREQ, DACK Mode Strobe, Burst Size Data_bus Byte_Lane must configured match setting Am53CF94/6
Am53CF94/6 Compatible Write with Byte Control
DREQ tSNW
/DACK tSAW
/DMAWR
DATA
tSNW Bypass Configuration Parameters: Direction DMA_OUT, Parity Odd, Dreq_lvl High, Dack_lvl Low, DMAWR_lvl Low, Mode Valid DREQ, DACK Mode Strobe, Burst Size Data_bus Byte_Lane must configured match setting Am53CF94/6
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Compatible Read
DREQ
/DACK
/DMARD
tSAW
tSNW
tSAW
DATA
Bypass Configuration Parameters: Direction DMA_IN, Parity Even, Dreq_lvl High, Dack_lvl Low, DMARD_lvl Low, Mode Valid DREQ, DACK Mode CSELECT, Burst Size
Compatible Write
DREQ
/DACK
tSNW
/DMAWR
tSAW
tSAW
DATA
MODE Valid DREQ, DACK Burst Valid only when DREQ active during strobe, number bytes/words burst size. /DACK used chip select, data valid DMAWR rising edge DREQ active point during strobe)
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7.3.7
Bypass Limitations
termination state
None interfaces have terminate state that distinguished from pause therefore when engine finishes (burst_buffer_empty=TRUE) state machine will return start state resetting internal pointers. burst buffer will likewise. burst_buffer_empty shall only asserted when burst buffer FIFO empty signal from engine been asserted. situations exist which cause problems. External device does return enough data when reading stops before write data been sent. must work with some timeout value then check registers external device determine what action take. Note, interrupts this case. External device sends more valid data than engine programmed for. quads could received this block lost when engine finishes. Possible solution would programme enable engine determine action after engine finished programmed transfer. Note, interrupts this case. This does affect writes. logical state dreq passed back register block examine necessary. size transfers limited multiples quadlet this version.
Bypass mode does work with 8bit mode when data upper byte lane
Lower byte lane Possible work-around route data lower byte lane.
Bypass mode bandwidth limitations
Fastest setting 16bit write transfer, tsaw=0, tsnw=1 MB/s Fastest setting 16bit read transfer, tsaw=0, tsnw=0 plus quad overhead cycle MB/s (Assuming input clock)
7.3.8
Bypass Mode streaming implementation
implementation could stream data continuously from 1394 interface external interface. This operation would bypass into continuous data stream mode. never sent core when done, needs done FIFO Manager order empty queues that subsequent 1394 packets received.
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Link-Core
Link provides interface between 1394 side internal sub-blocks other (Async Engine isochronous Block). implemented either 1394b 1394-1995/ 1394a-2000 Link, selectable external pin. phy-link interface parallel, operating 800Mb/s (S800) 1394b 400Mb/s (S400) 1394a. Link core capable transmitting receiving asynchronous isochronous data. Link designed re-usable core, which passes 1394 packet information internal interface quadlet format varying rates. performs processing contents valid packets. Packets with corrupt headers discarded. Cycle Master capable, Isochronous Resource Manager capable Manager capable. Link capable operating multiple clock domains. side uses generated 50MHz (49.152) 100MHz (98.304) clock, legacy beta respectively.
7.4.1
Register Link0 Link1 Link2 Link3 Link4 Link5 Link6 Link7 Link8 Link9 Link10 Link11
Register
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 Description Function enable register register access notifi cation status Value current cycle timer Power power down reset control Link core version Isochronous format controls Enables specific doorbells Indicates which enabled doorbells have been received. Isoch channel available downto Isoch channel available down timer packet transmision reserved reserved reserved General enables status Interrupt Status Interrupt Enable Isoch channel status downto Isoch channel status down reserved reserved
Link12 Link13 Link14 Link15 Link16
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FIFO Manager.
asynchronous 1394 rx/tx FIFOs endpoints maintained FIFO manager. This block allows dynamic allocation FIFO sizes provides high speed access them. FIFO Manager registers found starting location 0x0A400000. FIFO manager functionality broken down into three distinct sections: data plane access unit, context unit slave units.
7.5.1
Data plane
data plane function provides arbitration timing control allowing multiple read write sources access shared memory resource. data plane only supports four quadlet incrementing address accesses from even start addresses. reader writer arbitrate once granted writers provide four clock burst write data controlled enable signal, readers provided with read data accompanied with valid signal. function within chip FIFO manager data plane unit without using other functions just would ram. data plane arbitration implemented simple round robin inspecting high priority requests then priority requests. Back back requests granted allow continuous bursting.
7.5.2
Context
context unit allows readers, writers controlling define FIFO structures data plane maintain state e.g. sizes, locations, read/write pointers fill level. Therefore this unit plus distributed control read write functions, which maintains logical FIFOs FIFO manager memory. position length FIFOs programmable along with many other characteristics. readers writers data plane will this resource. Access context controlled arbitration series locks that agents cannot write same FIFO same time. writing reading context about FIFOs will require time which agents must allow latency calculations arbitration current activity within context unit.
7.5.3
slave units interface
There slave interface units, interfacing data other interfacing interface. Both interfaces allow access FIFOs supporting read write operations through FIFO context, other reader writer would expect. There interface which deals with configuration registers context configuration. Debug access data plane provided overlaying FIFO structure over addresses required accessing FIFO.
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7.5.4
Register
Offset 0x00 0x04 0x08 0x0C 0x10 0x1C 0x20 0x24 0x28 0x2C 0x30 0x3C 0x40 0x4C 0x50 0x5C 0x60 0x6C 0x70 0x7C 0x80 0x8C 0x90 0x9C 0x100 0x104 0x108 0x10C 0x110 0x114 0x200 0x204 0x208 0x20C 0x210 0x214 Description access queue number version register future future future read write pointers context windows specify queue number specify queue number specify queue number specify queue number clear lock queue clear mask queue queue interrupt status read lock status queues write lock status queues fill status queues threshold exceeded status queues various control bits read only read pointer write pointer register read only base pointer register read only new_read_ptr register read only new_write_ptr register future various control bits read only read pointer write pointer register read only base pointer register read only new_read_ptr register read only new_write_ptr register future
Register control scratch_control spare1 spare2 ctx_win[4] clear write clear read write read cpu_lock[4] cpu_mask[4] cpu_int[4] read_lock[4] write_lock[4] not_empty[4] thresh_exceed[4] control rw_ptr base_top new_read_ptr new_write_ptr fill_level control rw_ptr base_top new_read_ptr new_write_ptr fill_level
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OXUF922
-Processor.
Coprocessor (OCP) acceleration unit designed facilitate efficient 1394 SBP-2, SBP-3 Bulk transfer mode operations hardware speeds system. Coprocessor unloads task packet based header building ORBs. unit interacts with FIFO manager engine, move data into FIFO manager. destination source data stream either memory mapped SDRAM FIFO based i.e. ATA. Support transfers essentially subset that required 1394 header building required USB. Registers start from 0x0A200000 Address Offset 0x000 0x004 0x0FF 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x1F8 0x1FC Quadlet offset Register Name OCP_AHB_CONTROL Unused OCP_STATUS OCP_ORB_CONTROL OCP_DMA_CONTROL OCP_FM_QUEUE Unused OCP_NODE_ID OCP_ORB_LEN Unused Unused Unused OCP_DMA_SOURCE OCP_DMA_DEST OCP_DATADESC_1A OCP_DATADESC_1B OCP_DATADESC_2A OCP_DATADESC_2B Unused OCP_VERSION Reset Value 0x00000000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x4F435031 "OCP1"
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Queue Selector
queue selector resides between 1394 Async Link receive Async Engine management sub-system order examine incoming packets route them into appropriate queues. design takes form very simple microcode engine maximum flexibility reusability. Queue Selector registers start from 0x0A280000. Address Offset 0x000 0x004 0x014 0x018 0x01C 0x020 0x0F8 0x0FC 0x100 0x100 0x1FC Register Name QS_CSR Unused QS_HB_DEBUG QS_CPU_DEBUG Unused QS_VERSION QS_RAM_ACCESS_BASE QS_RAM_ACCESS registers
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Async Engine
Asynchronous Engine provides data handling stage between IEEE-1394 Link Core FIFO Manager. Asynchronous Engine provides hardware support following: 1394 Packet Receive 1394 Packet Transmit Packet Transmission Error Handling Received Packet Queue Selector Interface FIFO Manager Previous bridge implementations have limited amount queue selection, designed expressly efficient SPB-2 implementation. order support other protocols make solution more generic better queue selection scheme required. Async Engine registers start from 0x0A200000 Address Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x0FF 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x1F8 0x1FC Quadlet offset Register Name AE_CONFIG AE_SPLIT_TRANS AE_CONTROL AE_STATUS AE_RETRANS AE_INTR_ENABLE AE_INTR_STATUS AE_RESET AE_TX_QUEUES_0 AE_ACK_DISCARD AE_STREAM_CHANNEL_EN_0 AE_STREAM_CHANNEL_EN_1 AE_RX_QUAD_COUNT_CONFIG AE_INTR_0 AE_INTR_1 AE_INTR_2 Unused AE_RX_DEBUG AE_RXFIFO_DEBUG AE_RX_IF_DEBUG AE_RX_QUAD_COUNT_DEBUG AE_TX_DEBUG AE_TXFIFO_DEBUG AE_TX_IF_DEBUG Unused AE_VERSION
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USB2 core
core interfaces USB2.0 internal physical layer (PHY) FIFO manager system. core performs functions required efficiently manage points generic applications including bulk transfer protocols. core base address 0x0A300000. different clock domains design, method safe clock crossing must used read write registers. following table defines registers that must used. When writing data write address must written then control register polled ensure write completed. reads read address register should written first, control register polled until data valid, then read from data register. Address Offset Register DATA register READ address register WRITE address register CONTROL register Operation
Endpoint other registers defined address below. Address Targeted Register 00000h Endpoint (Control) 00004h Endpoint 00040h 00044h 00048h 00088h 000CCh 00300h 00304h 003F0h 003F4h 003FCh Endpoint (Control) Endpoint Endpoint Status Control General Purpose Register Timeouts Timeouts Function Enables Mask Register Universal Register
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7.10 Serial Controller
OXUF922 provides wire method transmitting receiving serial data. Serial Controller registers found starting location 0x0AA00000. Offset Read ADDRESS/CONTROL READ DATA CONTROL CONTROL Write ADDRESS/CONTROL WRITE DATA CONTROL CONTROL
Serial address control register Register Read SERIAL TRANSACTION DONE SERIAL TRANSACTION FAIL SERIAL READ/WRITE TRANSACTION TYPE SERIAL CONTROLLER RESET ADDRESS[10:0] Undefined
Write SERIAL TRANSACTION SERIAL READ/WRITE TRANSACTION TYPE SERIAL CONTROLLER RESET ADDRESS[10:0]
SERIAL TRANSCATION When chosen transaction indicated other bits this registers executed. cleared hardware when transaction completed. This polled indicate that transaction progress. Note: That write transaction WRITE DATA Serial read DATA register must programmed advance. SERIAL TRANSACTION DONE: Cleared hardware indicates completion transaction. SERIAL TRANSACTION FAIL: When indicates that completed transaction failed. This likely response from serial slave. This eared hardware when transaction successful. SERIAL READ WRITE: When TRANSACTION TYPE then this controls whether read write cycle performed. WRITE CYCLE READ CYCLE TRANSACTION TYPE: When transaction will SERIAL READ WRITE When serial controller will perform RESET TRANSACTION bus. NOTE: must execute this transaction. reset transaction should performed after power ensure serial properly reset. should also performed successive failures noticed. SERIAL CONTROLLER RESET: serial software should implement timeout ensure that serial locked there timeouts within serial controller logic. time occurs then software should perform SERIAL CONTROLLER RESET setting this bit. should then clear this execute RESET TRANSACTION. Timeout periods will function selected clock rate. ADDRESS: address mapped directly serial data bus.
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Serial read DATA register Register
OXUF922
Read SERIAL READ DATA Undefined
Write SERIAL WRITE DATA undefined
Serial software control register Register Read Write SERIAL CLOCK SERIAL CLOC SERIAL DATA SERIAL DATA SERIAL DATA ENABLE SERIAL DATA ENABLE SERIAL CONTROL SERIAL CONTROL order allow more flexibility over serial possible software directly control serial bus. serial been multiplexed with GPIO pins Table Serial control register. SERIAL CLOCK DATA: These directly SERIAL CLOCK SERIAL DATA pins enabled through GPIO) illustrated below: GPIO data(10:8) GPIO(7) GPIO GPIO GPIO(6) GPIO GPIO GPIO(5) GPIO GPIO GPIO(4) GPIO GPIO GPIO GPIO GPIO(3) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO(2) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO(1) GPIO serial_data GPIO serial_data GPIO serial_data GPIO serial_data GPIO(0) GPIO serial_clock GPIO serial_clock GPIO serial_clock GPIO serial_clock
Table Serial control register SERIAL DATA ENABLE: When this enables tri-state SERIAL DATA output. SERIAL CONTROL: Must enable control mode allow software drive serial bus. Serial control software register Register Read SERIAL DATA single provided allow software read serial input data bit.
Write APPLICABLE
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7.11 Serial Audio
Serial Audio serial (path) design digital audio devices technologies such compact disc players, digital sound processors, digital sound. Serial Audio design handles audio separately from clock signals. Serial Audio design consists three serial lines: line with time-division multiplexing (TDM) data line (SDA): single direction clock line (SCL): minimal frequency 2*Fs*(number bits/sample). `Word Select' line (SWS): determines between left right channel samples
Data transferred first. channels sample period transferred: left channel first. left channels, signal level. figure
Figure
clock word select data
clock word select data
Transmitter
Receiver
Transmitter
Receiver
Transmitter Master
Receiver Master
Controller
Transmitter Controller Master Receiver
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7.11.1
Register
following tables show definition functions wire serial audio interface status control register starting location 0x0AC00000. Offset Read Clock Register Control Register Status Register Write Clock Register Control Register FIFO Register
SERIAL AUDIO Clock Register NAME 10-0 DTO_TERMINAL_COUNT 23-11 CLOCK_ACCUMULATION SERIAL AUDIO Control Register NAME SERIAL AUDIO_ENABLE DELAY_BIT DATA_WIDTH INPUT_DATA_WIDTH
DESCRIPTION Defines roll-over. Defines accumulation value, used generate increment signal.
INVERT WORD SELECT RIGHT JUSTIFY MSB_FIRST
DESCRIPTION wire serial audio enable active) reset inactive When interrupts enabled, when reset interrupts disabled reset disabled Interrupt only pulses clock cycle. When wire serial audio Philips format, when reset EIAJ format reset Philips format. audio data audio data audio data audio data audio data audio data audio data Used convert between Philips (set Sony mode (bit When wire serial audio data will right justified when output wire serial audio Philips mode Sony Defines which sent across wire serial audio first. first, first) reset Only used major problem
SERIAL AUDIO Status Register NAME INT_PENDING UNDERFLOW
DESCRIPTION When input FIFO least quadlet space. when interrupt triggered, reset when wire serial audio status register read. when input FIFO underrun, reset when wire serial audio status register read.
SERIAL AUDIO FIFO register NAME 31-0 C_REG_DATA
DESCRIPTION Audio data input FIFO
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7.11.2
Feature list
3byte input FIFO methods serial audio clock generation; that maintains exact lock input 1394 stream will have short term jitter that never varies needs software support ensure constant data stream. Supports data Philips EIAJ formats. Supports range 61883 audio formats; generic, AM824 (raw, IEC60958). However checking labels MUST done processor. (Note necessary processor check samples). Supports output only. event underflow input FIFO, last data will transmitted. Supports stereo sample rates KHz, 44.1 KHz, KHz, 22.05 KHz.
Quick Summary Audio DACs
PCM1742, 24-Bit, 96kHZ Sampling Enhanced Multilevel, Delta-Sigma, Audio PCM1741 same 1742, single supply PCM1772 same 1742, voltage
tolerent clock jitter, tolerent clock jitter, available
Philips TA1311, stereo continuous calibration UDA1320ATS; Low-cost stereo filter UDA1330 same above UDA1350/1351 IEC958 audio Analog Devices tolerent clock jitter tolerent clock jitter, tolerent clock jitter, jitter
1866 dual 1865 dual dacs 1851 single 1862 noise 1859 Stero 18bit WM8740 high performance
tolerent clock jitter tolerent clock jitter tolerent clock jitter tolerent clock jitter jitter tolerent clock jitter
Wolfson
7.11.3
Limitations
Only simple clock generator implemented. When locked 1394 stream this implies that chip connecting serial audio will need have tolerance clock jitter, less expensive applications (fixed frequency method) data might lost replicated event underflows overflows. Does cope with audio data clustered into quadlets where UNIT_SIZE UNIT_DIMENSION (see 61883 spec details 24-bit audio pack supported). This means that each sample occupies complete quadlet, regardless actual sample size. Input samples will 24-bit 16-bit only. MIDI data 32-bit floating defined 61883. Input controlled processor triggered from interrupt that every
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FORCE FLASH
program flash 1394 device must Force Flash mode host must issue Write Quadlets FLASH PORT which Link interprets, sends complete puts data into Flash Port register. Flash Port register 23:17 Function reset overlay address used address data External Mapping cs#(0) (flash) data output enable cs#(1) cs#(2) addr data
Addr selected when (overlay addr) true force flash controller generates flash_loading signal which controls muxing, enable Flash Port register data onto external static bus, hence will take accesses write cycle e.g. Address, overlay address, Data, overlay address, data output enable Data, overlay address, data output enable. Multiple write cycles required program each location Flash depending programming algorithm. time between host accesses must sufficient meet timing requirements particular Flash device. Note that there currently host read back data from Flash method. whole Flash image programmed using above method downloader program programmed executed program Flash. This downloader would from internal allow host send Write Block packets containing Flash image. This would allow more efficient faster software controlled programming sequence. enter Force Flash mode, flash_loading signal generated under following conditions force_flash held active. Highest priority. host writes enable value UPLOAD_MODE_CTRL CSR, Link will generate flash_loading signal. watchdog times when switch_on_timeout signal true. This default start position with blank flash. Force Flash mode shall exited under following conditions chip reset either through reset setting reset Flash Port register
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switch_on_timeout enabled reset, when force flash mode entered pin, when writes register enabling This requires data match ensure accidental setting, enable disable feature. When flash_loading true, addition muxing control, following conditions also true held reset Sync_reset generated clock cycles after reset flash_port. This takes chip force flash mode enables CPU. 1394 Reset shall cause chip exit Force Flash mode
Function UPLOAD_MODE_CTRL FLASH_PORT Function Enable switch-on- timeout Disable switch-on-timeout
Address F0080000 Address 0x4A000380 0x4A000380
Enable Value Value 1068AFC5* 1068AFC4*
*bit fast_timeout must appropriately
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OPERATING CONDITIONS
Symbol VDDH Iout TSTG Parameter supply voltage Core supply voltage input voltage (3.3V I/O) input voltage tolerant I/O) output current Storage temperature -0.3 -0.3 -0.3 -0.3 VDDH Units
Symbol VDDH
Parameter supply voltage Core supply voltage Ambient Temperature
1.65
1.95
Units
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ELECTRICAL CHARACTERISTICS
Symbol Parameter Input high voltage Condition CMOS Interface CMOS Schmitt trig tolerant CMOS Schmitt trig CMOS Interface CMOS Schmitt trig tolerant CMOS Schmitt trig Schmitt -1mA -24mA 24mA Units
Input high voltage Input voltage
Input voltage Hysteresis voltage Input high leakage current Input leakage current Output high voltage Output high voltage Output voltage Output voltage 3-state output leakage current
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PHY-LINK INTERFACE TIMING DIAGRAMS
11.1 Mode
SCLK
tlsu D(n:0) CTL(1:0)
Link transfer waveform Link
SCLK
D(n:0) CTL(1:0) LREQ
Link transfer waveform Link
Mode timing Name tlsu tld(1/2/3) 1394a-2000 specification OXUF922
load outputs from link 10pF
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11.2 Mode
PCLK
D(n:0) CTL(1:0) Pint
thld
Link transfer waveform Link
PCLK
LCLK D(n:0) CTL(1:0) LREQ
Link transfer waveform Link
Mode timing Name thld tpd(1/2/3) 1394b OXUF922
Capacitance load outputs seen from link 10pF
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EXTERNAL TIMING DIAGRAMS
Asynchronous timing Name Description Common Timings CSx# falling valid Address Wait State Additional Delay (number wait states (WS) taddr Address Valid Common Read Timings Address hold after CSx# rising Access Time external device tdsa Data setup CSx# rising tdha Data hold after CSx# rising Common Write Timings twds Data valid rising twdh Data hold after rising tcsw setup before valid tadw Address setup before valid valid Synchronous timing Name Description Common Timings tcycle clock period tcych clock high tcycl clock tsaa address valid after rising clock edge tsan address invalid after rising clock edge tscsa asserted after rising clock edge tscsn negated after rising clock edge Common Read Timings tsoea asserted after rising clock edge tsoen negated after rising clock edge Common Write Timings data valid after rising clock edge tsdh data hold after rising clock edge tswa asserted after rising clock edge tswn negated after rising clock edge
(ns) 17.5
(ns) 5120 20+tws 5125 20+(tws -20) 20+tws
(ns) 20.3 tcycle -0.1 -0.1
(ns) 20.8 57.7 42.5 tcycle -0.5 -0.3 -0.2
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taddr Address
Data
tdsa tdha
taddr
taddr
Address
Data tdsa tdha tdsa tdha
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OXUF922
taddr Address
Data
twds twdh
tcsw
taddr
taddr
Address
Data twds twdh twds twdh
tadw
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OXUF922
tcych tsaa Address
tcycl
tcycle
tsan
Data tscsa tsoea tsoen tscsn
Address
Data tsdh
tswa tswn
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OXUF922
POWER CONSUMPTION
Current USB2 Running(idle) Running(Working) USB1 Running(idle) Running(Working) 1394 Mode Running(idle) Running(Working) 1394 Mode Running(idle) Running(Working) Total Total Total Total
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PACKAGE INFORMATION
14.1 LQFP Package
26.00 24.00
24.00
26.00 1.35 1.45 0.05 0.15
0.45 0.75 1.00 REF.
detail
detail
1.60 0.17 0.27
dimentions millimeters additional details JEDEC MS-026
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14.2 Package
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ORDERING INFORMATION
OXUF922
Revision Package Type LQFP VFBGA Part Number
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NOTES
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CONTACT DETAILS
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1394B Interface Link Backward compatible with 1394A 800Mb/s Support SB

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