HCPL-3120 Minimum Peak Output Current kV/µs Minimum Common Mode R

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HCPL-3120 Minimum Peak Output Current kV/µs Minimum Common Mode R

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Output Current IGBT Gate Drive Optocoupler Technical Data
HCPL-3120
Minimum Peak Output Current kV/µs Minimum Common Mode Rejection (CMR) 1500 Maximum Level Output Voltage (VOL) Eliminates Need Negative Gate Drive Maximum Supply Current Under Voltage Lock-Out Protection (UVLO) with Hysteresis Wide Operating Range: Volts Maximum Switching Speeds Industrial Temperature Range: -40°C 100°C Safety Approval Recognized 2500 minute UL1577 Approval 0884 Approved with VIORM peak (Option only)
Industrial Inverters Switch Mode Power Supplies (SMPS)
Description
HCPL-3120 consists GaAsP optically coupled integrated circuit with power output stage. This optocoupler ideally suited driving power IGBTs MOSFETs used
motor control inverter applications. high operating voltage range output stage provides drive voltages required gate controlled devices. voltage current supplied this optocoupler makes ideally suited directly driving IGBTs with ratings 1200 V/100 IGBTs with higher ratings, HCPL-3120 used drive discrete power stage which drives IGBT gate.
Functional Diagram
ANODE
CATHODE
SHIELD
TRUTH TABLE "POSITIVE GOING" "NEGATIVE GOING" (i.e., TURN-ON) (i.e., TURN-OFF) 13.5 13.5
TRANSITION
Applications
Isolated IGBT/MOSFET Gate Drive Brushless Motor Drives
bypass capacitor must connected between pins
CAUTION: advised that normal static precautions taken handling assembly this component prevent damage and/or degradation which induced ESD. 1-182 5965-4779E
Ordering Information
Specify Part Number followed Option Number desired) Example HCPL-3120#XXX Option Standard Package, tube. 0884 VIORM peak Option, tube. Gull Wing Surface Mount Option, tube. Tape Reel Packaging Option, 1000 reel. Option data sheets available. Contact Hewlett-Packard sales representative authorized distributor.
Package Outline Drawings
Standard Package
9.40 (0.370) 9.90 (0.390) OPTION CODE* DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310) 0.20 (0.008) 0.33 (0.013)
3120Z YYWW
TYP.
1.19 (0.047) MAX.
1.78 (0.070) MAX.
4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS MILLIMETERS (INCHES). DIAGRAM *MARKING CODE LETTER OPTION NUMBERS. OPTION VDD1 OPTION NUMBERS MARKED. 0.76 (0.030) 1.40 (0.055) 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) VIN+ VIN- VOUT+ VOUT-
GND1 GND2
Gull Wing Surface Mount Option
LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
1.016 (0.040) 1.194 (0.047)
3120Z YYWW
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
MOLDED
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
0.20 (0.008) 0.33 (0.013)
1.080 0.320 (0.043 0.013) 2.540 (0.100)
0.635 0.130 (0.025 0.005)
0.635 0.25 (0.025 0.010) NOM.
DIMENSIONS MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx 0.01 xx.xxx 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004)
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Reflow Temperature Profile
145°C, 1°C/SEC 115°C, 0.3°C/SEC
Regulatory Information
HCPL-3120 been approved following organizations: Recognized under 1577, Component Recognition Program, File E55361.
TEMPERATURE
100°C, 1.5°C/SEC
TIME MINUTES MAXIMUM SOLDER REFLOW THERMAL PROFILE (NOTE: NON-CHLORINE ACTIVATED FLUXES RECOMMENDED.)
Approved under Component Acceptance Notice File 88324. (Option Only) Approved under 0884/06.92 with VIORM peak.
0884 Insulation Characteristics (Option Only)
Description Installation classification 0110/1.89, Table rated mains voltage rated mains voltage Climatic Classification Pollution Degree (DIN 0110/1.89) Maximum Working Insulation Voltage Input Output Test Voltage, Method VIORM 1.875 VPR, 100% Production Test with sec, Partial discharge Input Output Test Voltage, Method VIORM VPR, Type Sample Test, sec, Partial discharge Highest Allowable Overvoltage* (Transient Overvoltage tini sec) Safety Limiting Values-Maximum Values Allowed Event Failure, Also Figure Thermal Derating Curve. Case Temperature Input Current Output Power Insulation Resistance Symbol Characteristic I-IV I-III 55/100/21 1181 Unit
VIORM
Vpeak Vpeak
VIO
6000
Vpeak Vpeak
INPUT OUTPUT
*Refer front optocoupler section current catalog, under Product Safety Regulations section, (VDE 0884) detailed description Method Method partial discharge test profiles. Note: Isolation characteristics guaranteed only within safety maximum ratings which must ensured protective circuits application.
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Insulation Safety Related Specifications
Parameter Symbol Value Units Conditions Minimum External L(101) Measured from input terminals output terminals, (External shortest distance through air. Clearance) Minimum External L(102) Measured from input terminals output terminals, Tracking (External shortest distance path along body. Creepage) Minimum Internal Plastic 0.08 Insulation thickness between emitter detector; (Internal Clearance) also known distance through insulation. Tracking Resistance Volts 112/VDE 0303 Part (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN 0110, 1/89, Table Option surface mount classification Class accordance with CECC 00802.
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current pulse width, pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol IF(AVG) IF(TRAN) IOH(PEAK) IOL(PEAK) (VCC VEE) Min. -55. Max. Units Note
Volts Volts Volts 260°C sec., below seating plane Package Outline Drawings section
Recommended Operating Conditions
Parameter Power Supply Voltage Input Current (ON) Input Voltage (OFF) Operating Temperature Symbol (VCC VEE) IF(ON) VF(OFF) Min. -3.0 Max. Units Volts
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Electrical Specifications (DC)
Over recommended operating conditions 100°C, IF(ON) VF(OFF) -3.0 Ground) unless otherwise specified. Parameter High Level Output Current Level Output Current Symbol Min. Typ.* Max. Units (VCC (VCC Test Conditions (VCC (VCC (VEE (VEE 15V) -100 Output Open, Output Open, -3.0 +0.8 Fig. Note
High Level Output Voltage Level Output Voltage High Level Supply ICCH Current Level Supply ICCL Current Threshold Input IFLH Current High Threshold Input Voltage High VFHL Input Forward Voltage Temperature Coefficient Forward Voltage Input Reverse Breakdown Voltage Input Capacitance UVLO Threshold VUVLO+ VUVLO- UVLO Hysteresis UVLOHYS
-1.6
mV/°C MHz,
12.3 10.7
11.0
13.5 12.0
typical values 25°C unless otherwise noted.
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Switching Specifications (AC)
Over recommended operating conditions 100°C, IF(ON) VF(OFF) -3.0 Ground) unless otherwise specified. Parameter Symbol Min. Propagation Delay tPLH 0.10 Time High Output Level Propagation Delay tPHL 0.10 Time Output Level Pulse Width Distortion Propagation Delay (tPHL tPLH) -0.35 Difference Between Parts Rise Time Fall Time UVLO Turn tUVLO Delay UVLO Turn tUVLO Delay Output High Level |CMH| Common Mode Transient Immunity Output Level |CML| Common Mode Transient Immunity Typ.* 0.30 Max. 0.50 Units Test Conditions kHz, Duty Cycle Fig. Note
0.27
0.50
0.35
34,35
kV/µs 25°C, 1500 25°C, 1500
kV/µs
*All typical values 25°C unless otherwise noted.
Package Characteristics
Parameter Symbol Input-Output VISO Momentary Withstand Voltage** Resistance RI-O (Input Output) Capacitance CI-O (Input Output) LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance Min. 2500 Typ. Max. Units VRMS °C/W °C/W °C/W Test Conditions 50%, min., 25°C VI-O Thermocoupler located center underside package Fig. Note
1012
**The Input-Output Momentary Withstand Voltage dielectric voltage rating that should interpreted input-output continuous voltage rating. continuous voltage rating refer your equipment level safety specification Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
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Notes: Derate linearly above 70°C free-air temperature rate mA/°C. Maximum pulse width maximum duty cycle 0.2%. This value intended allow component tolerances designs with peak minimum Applications section additional details limiting peak. Derate linearly above 70°C free-air temperature rate mW/°C. Derate linearly above 70°C free-air temperature rate mW/°C. maximum junction temperature should exceed 125°C. Maximum pulse width maximum duty cycle 0.5%. this test measured with load current. When driving capacitive
loads will approach approaches zero amps. Maximum pulse width maximum duty cycle 20%. accordance with UL1577, each optocoupler proof tested applying insulation test voltage 3000 Vrms second (leakage detection current limit, II-O µA). This test performed before 100% production test partial discharge (method shown 0884 Insulation Characteristic Table, applicable. Device considered two-terminal device: pins shorted together pins shorted together.
difference between tPHL tPLH between HCPL-3120 parts under same test condition. Pins need connected common. Common mode transient immunity high state maximum tolerable dVCM common mode pulse, VCM, assure that output will remain high state (i.e., 15.0 Common mode transient immunity state maximum tolerable dVCM/dt common mode pulse, VCM, assure that output will remain state (i.e., This load condition approximates gate load 1200V/75A IGBT. Pulse Width Distortion (PWD) defined |tPHL-tPLH| given device.
(VOH OUTPUT HIGH VOLTAGE DROP
(VOH HIGH OUTPUT VOLTAGE DROP
OUTPUT HIGH CURRENT
IOUT -100
VOUT (VCC
TEMPERATURE
TEMPERATURE
OUTPUT HIGH CURRENT
Figure Temperature.
Figure Temperature.
Figure IOH.
0.25
OUTPUT VOLTAGE
OUTPUT CURRENT
0.20
OUTPUT VOLTAGE
VF(OFF) -3.0 IOUT
VF(OFF) -3.0 VOUT
VF(OFF) -3.0
0.15
0.10
0.05
OUTPUT CURRENT
TEMPERATURE
TEMPERATURE
Figure Temperature.
Figure Temperature.
Figure IOL.
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SUPPLY CURRENT
SUPPLY CURRENT
IFLH HIGH CURRENT THRESHOLD
OUTPUT OPEN
ICCH ICCL
ICCH ICCL
ICCH ICCL
ICCH ICCL
TEMPERATURE
SUPPLY VOLTAGE
TEMPERATURE
Figure Temperature.
Figure VCC.
Figure IFLH Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
PROPAGATION DELAY
DUTY CYCLE
TPLH TPHL
DUTY CYCLE
DUTY CYCLE
TPLH TPHL
TPLH TPHL
SUPPLY VOLTAGE
FORWARD CURRENT
TEMPERATURE
Figure Propagation Delay VCC.
Figure Propagation Delay
Figure Propagation Delay Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
OUTPUT VOLTAGE
DUTY CYCLE
DUTY CYCLE
TPLH TPHL
TPLH TPHL
SERIES LOAD RESISTANCE
LOAD CAPACITANCE
FORWARD CURRENT
Figure Propagation Delay
Figure Propagation Delay
Figure Transfer Characteristics.
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1000
FORWARD CURRENT
25°C
0.01
0.001 1.10
1.20
1.30
1.40
1.50
1.60
FORWARD VOLTAGE VOLTS
Figure Input Current Forward Voltage.
Figure Test Circuit.
Figure Test Circuit.
Figure Test Circuit.
Figure Test Circuit.
Figure IFLH Test Circuit.
Figure UVLO Test Circuit.
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DUTY CYCLE
VOUT tPLH tPHL
Figure tPLH, tPHL, Test Circuit Waveforms.
SWITCH SWITCH 1500
Figure Test Circuit Waveforms.
Applications Information
Eliminating Negative IGBT Gate Drive keep IGBT firmly off, HCPL-3120 very maximum specification HCPL-3120 realizes this very using DMOS transistor with (typical) resistance pull down circuit. When HCPL3120 state, IGBT
gate shorted emitter Minimizing lead inductance from HCPL3120 IGBT gate emitter (possibly mounting HCPL-3120 small board directly above IGBT) eliminate need negative IGBT gate drive many applications shown Figure Care should taken with such board design avoid routing
IGBT collector emitter traces close HCPL-3120 input this result unwanted coupling transient signals into HCPL-3120 degrade performance. IGBT drain must routed near HCPL3120 input, then should reverse-biased when state, prevent transient signals coupled from IGBT drain from turning HCPL-3120.)
HCPL-3120
HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE
HVDC
Figure Recommended Drive Application Circuit.
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Selecting Gate Resistor (Rg) Minimize IGBT Switching Losses. Step Calculate Minimum from Peak Specification. IGBT Figure analyzed simple circuit with voltage supplied HCPL-3120. (VCC VOL) --------------- IOLPEAK (VCC --------------- IOLPEAK ------------------
value previous equation conservative value peak current 2.5A (see Figure lower values voltage supplied HCPL-3120 ideal voltage step. This results lower peak currents (more margin) than predicted this analysis. When negative gate drive used previous equation equal zero volts. Step Check HCPL-3120 Power Dissipation Increase Necessary. HCPL-3120 total power dissipation (PT) equal emitter power (PE) output power (PO):
Duty Cycle PO(BIAS) (SWITCHING) (VCC VEE) ESW(RG, circuit Figure with (worst case) Duty Cycle 80%, 85C: 4.25 (PO(MAX) mW-15C*4.8 mW/C)
HCPL-3120
HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE
HVDC
Figure HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive.
Parameter Duty Cycle
Description Current Voltage Maximum Duty Cycle
Parameter ESW(Rg,Qg)
Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated HCPL-3120 each IGBT Switching Cycle (See Figure Switching Frequency
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shown Figure HCPL3120 improves performance using detector with optically transparent Faraday shield, which diverts capacitively coupled current away from (LC||(LD sensitive circuitry. Since this case greater ---------------- ever, this shield does than PO(MAX), must eliminate capacitive coupling increased reduce HCPLbetween optocoup3120 power dissipation. --------------- pins shown Figure This capacitive PO(SWITCHING MAX) coupling causes perturbations PO(MAX) PO(BIAS) (DC||(LD current during common mode transients becomes Inserting values major source failures PO(SWITCHINGMAX) ESW(MAX) --------------- shown Figure gives: shielded optocoupler. main design objective high (256°C/W drive circuit becomes ------- 4.65 (57°C/W keeping proper (57°C/W state off) during common (111°C/W mode transients. example, from Figure recommended application value 4.65 example, given circuit (Figure 25), achieve gives 10.3 70°C kV/µs while minimizing 83°C/W: component complexity. Thermal Model steady state thermal model 339°C/W 140°C/W Techniques keep HCPL-3120 shown 339°C/W proper state discussed Figure thermal resistance 140°C/W 70°C 120°C next sections. values given this model used calculate temperaTJD 140°C/W 194°C/W tures each node given 140C/W operating condition. shown 194°C/W 70°C 125°C model, heat generated flows through which raises case temperature should limited 1000 accordingly. value 125C based board layout depends conditions part placement (CA) specific board design therefore, application. determined designer. value 83°C/W Drive Circuit obtained from thermal measureConsiderations Ultra ments using inch High Performance. board, with small traces Without detector shield, ground plane), single HCPLdominant cause optocoupler GATE RESISTANCE 3120 soldered into center failure capacitive board still air. coupling from input side Figure Energy Dissipated absolute maximum power optocoupler, through HCPL-3120 Each IGBT Switching dissipation derating specifications package, detector Cycle. assume CAvalue 83°C/W. value 4.25 previous equation obtained derating (which occurs -40°C) (see Figure From thermal mode Figure detector junction temperatures expressed
ENERGY SWITCHING CYCLE
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°C/W °C/W °C/W* °C/W
junction temperature detector junction temperature case temperature measured center package bottom LED-to-case thermal resistance LED-to-detector thermal resistance detector-to-case thermal resistance case-to-ambient thermal resistance will depend board design placement part.
Figure Thermal Model.
with (CMRH).
high drive circuit must keep during common mode transients. This achieved overdriving current beyond input threshold that pulled below threshold during transient. minimum current provides adequate margin over maximum IFLH achieve kV/µs CMR.
open collector drive circuit, shown Figure cannot keep during +dVcm/dt transient, since current flowing through CLEDN must supplied LED, recommended applications requiring ultra high CMRL performance. Figure alternative drive circuit which, like recommended application circuit (Figure 25), does achieve ultra high performance shunting state.
coupler output will into state with typical delay, UVLO Turn Delay, When HCPL-3120 output state supply voltage rises above HCPL3120 VUVLO+ threshold (11.0 VUVLO+ 13.5) optocoupler output will into high state (assumes "ON") with typical delay, UVLO Turn Delay
with (CMRL).
high drive circuit must keep VF(OFF)) during common mode transients. example, during -dVcm/dt transient Figure current flowing through CLEDP also flows through RSAT VSAT logic gate. long state voltage developed across logic gate less than VF(OFF), will remain common mode failure will occur.
Under Voltage Lockout Feature.
HCPL-3120 contains under voltage lockout (UVLO) feature that designed protect IGBT under fault conditions which cause HCPL-3120 supply voltage (equivalent fully-charged IGBT gate voltage) drop below level necessary keep IGBT resistance state. When HCPL-3120 output high state supply voltage drops below HCPL-3120 VUVLO- threshold (9.5 VUVLO- 12.0) opto-
Dead Time Propagation Delay Specifications.
HCPL-3120 includes Propagation Delay Difference (PDD) specification intended help designers minimize "dead time" their power inverter designs. Dead time time period during which both high side power transistors Figure off. overlap conduction will result large currents flowing through power devices between high voltage motor rails.
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CLEDP
CLEDO1 CLEDP
CLEDO2
CLEDN
CLEDN
SHIELD
Figure Optocoupler Input Output Capacitance Model Unshielded Optocouplers.
Figure Optocoupler Input Output Capacitance Model Shielded Optocouplers.
CLEDP
ILEDP
VSAT
CLEDP
CLEDN
SHIELD
CLEDN ILEDN
ARROWS INDICATE DIRECTION CURRENT FLOW DURING -dVCM/dt.
SHIELD
Figure Equivalent Circuit Figure During Common Mode Transient.
Figure Recommended Open Collector Drive Circuit.
CLEDP
CLEDN
SHIELD
Figure Recommended Drive Circuit Ultra-High CMR.
minimize dead time given design, turn LED2 should delayed (relative turn LED1) that under worst-case conditions, transistor just turned when transistor turns shown Figure amount delay necessary achieve this conditions equal maximum value propagation delay difference specification, PDDMAX,
which specified over operating temperature range -40°C 100°C. Delaying signal maximum propagation delay difference ensures that minimum dead time zero, does tell designer what maximum dead time will maximum dead time equivalent difference between
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maximum minimum propagation delay difference specifications shown Figure maximum dead time HCPL-3120 (-350 ns)) over operating temperature range -40°C 100°C.
Note that propagation delays used calculate dead time taken equal temperatures test conditions since optocouplers under consideration typically mounted close proximity each other switching identical IGBTs.
ILED1
OUTPUT VOLTAGE
(10.7, 0.1) (12.3, 0.1) (12.3, 10.8) (10.7, 9.2)
VOUT1
VOUT2 ILED2
tPHL tPLH PDD* (tPHL- tPLH)MAX tPHL tPLH
(VCC SUPPLY VOLTAGE
*PDD PROPAGATION DELAY DIFFERENCE NOTE: CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
Figure Minimum Skew Zero Dead Time.
Figure Under Voltage Lock Out.
ILED1
OUTPUT POWER INPUT CURRENT
(mW) (mA)
VOUT1
VOUT2
ILED2 tPHL tPHL tPLMIN
tPLH (tPHL-tPLH) PDD* MAXIMUM DEAD TIME (DUE OPTOCOUPLER) (tPHL tPHL MIN) (tPLH tPLH MIN) (tPHL tPLH MIN) (tPHL tPLH MAX) PDD* PDD* *PDD PROPAGATION DELAY DIFFERENCE NOTE: DEAD TIME CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
CASE TEMPERATURE
Figure Thermal Derating Curve, Dependence Safety Limiting Value with Case Temperature 0884.
Figure Waveforms Dead Time.
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HCPL-3120 Minimum Peak Output Current kV/µs Minimum Common Mode R

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