The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

LITELINKIII Phone Line Interface (DAA) Superior voice solution wi


Datasheet Thumbnail

  

Download PDF



Top Searches for this datasheet



CPC5620/CPC5621
LITELINKIII Phone Line Interface (DAA)
Superior voice solution with high power option, noise, automatic gain control circuit, excellent part-to-part gain accuracy Data access arrangement (DAA) solution modems speeds V.92 power supply operation Caller signal reception function Easy interface with modem voice CODECs Worldwide dial-up telephone network compatibility Supplied application circuit complies with requirements TIA/EIA/IS-968 (FCC part 68), UL1950, UL60950, EN60950, IEC60950, EN55022B, CISPR22B, EN55024, TBR-21 Complies with UL1577 Line-side circuit powered from telephone line Compared other silicon solutions, LITELINK: Uses fewer passive components Takes less printed-circuit board space Uses less telephone line power Offers simplified operation single-chip solution
Description
LITELINK single-package silicon phone line interface/DAA used voice data communication applications make connections between host equipment telephone networks. LITELINK provides high-voltage isolation barrier, phone line termination, switchhook, 2-wire 4-wire hybrid, ring detection, on-hook signal detection. LITELINK used both differential single-ended signal applications. LITELINK uses on-chip optical components inexpensive external components form complete voice high-speed data phone line interface. LITELINK eliminates need large isolation transformers capacitors used other interface configurations. incorporates required high-voltage isolation barrier surface-mount SOIC package. CPC5620 (half-wave ring detect) CPC5621 (full-wave ring detect) PLIs build upon Clare's LITELINK line, with improved insertion loss control, improved noise performance, lower minimum current draw from phone line.
Applications
Computer telephony gateways, such VoIP PBXs Satellite cable set-top boxes V.92 (and other standard) modems machines Voicemail systems Embedded modems terminals, automated banking, remote metering, vending machines, security, surveillance
Isolation Barrier Transmit Isolation Amplifier Vref Gain Trim Vref Gain Trim Receive Isolation Amplifier CID/ RING CSNOOP Snoop Amplifier CSNOOP RSNOOP RSNOOP
Part Number CPC5620A CPC5620ATR CPC5621A CPC5621ATR
Transconductance Stage Wire Hybrid AC/DC Termination Hookswitch
Ordering Information
Description 32-pin with half-wave ring detect, tubed 32-pin with half-wave ring detect, tape reel 32-pin with full-wave ring detect, tubed 32-pin with full-wave ring detect, tape reel
Figure CPC5620/CPC5621 Block Diagram
TIP+
TxTransmit Diff. Amplifier MODE RING RxReceive Diff. Amplifier
DS-CPC5620/5621-R0.E
www.clare.com
Slope Control Current Limit Control RING-
Impedance Control
CPC5620/CPC5621
Electrical Specifications. Absolute Maximum Ratings. Performance Description Application Circuits Resistive Termination Application Circuit 2.1.1 Resistive Termination Application Circuit Part List Reactive Termination Application Circuit. 2.2.1 Reactive Termination Application Circuit Part List Using LITELINK Switch Hook Control (On-hook Off-hook States) On-hook Operation 3.2.1 Ring Signal Reception Snoop Circuit 3.2.2 Polarity Reversal Detection with CPC5621 3.2.3 On-hook Caller Signal Reception Off-Hook Operation 3.3.1 Receive Signal Path. 3.3.2 Transmit Signal Path Start-up Requirements Characteristics. 3.5.1 Non-Current Limited Applications 3.5.2 Current Limited Applications Characteristics. 3.6.1 Resistive Termination Applications 3.6.2 Reactive Termination Applications. 3.6.3 Mode Usage.
LITELINK Performance Manufacturing Information. Mechanical Dimensions. Tape Reel Packaging Soldering 7.3.1 Moisture Reflow Sensitivity 7.3.2 Reflow Profile Washing.
LITELINK Design Resources Clare, Inc. Design Resources Third Party Design Resources.
Regulatory Information
www.clare.com
R0.E
CPC5620/CPC5621
Electrical Specifications
Absolute Maximum Ratings
Parameter Isolation Voltage Continuous Ring Current (RZDC 5.2) Total Package Power Dissipation Operating temperature Storage temperature Soldering temperature Minimum Maximum 1500 +125 +220 Unit VRMS
Absolute maximum ratings stress ratings. Stresses excess these ratings cause permanent damage device. Functional operation device these other conditions beyond those indicated operational sections this data sheet implied. Exposure device absolute maximum ratings extended period degrade device affect reliability.
Performance
Parameter Characteristics Operating Voltage Operating Current Operating Voltage VDDL Operating Current IDDL On-hook Characteristics Metallic Resistance Ring Signal Detect Level Ring Signal Detect Level Snoop Circuit Frequency Response Snoop Circuit CMRR Ringer Equivalence Longitudinal Balance Off-Hook Characteristics Impedance Longitudinal Balance Return Loss Transmit Receive Characteristics Frequency Response Trans-Hybrid Loss Minimum Typical
Maximum 5.50 >4000 0.1B 4000 www.clare.com
Longitudinal Resistance
Unit VRMS VRMS part 68.3 ring, using resistive termination application circuit part 68.3 Into 1800 corner frequency Into 1800 with resistive termination application circuit Conditions Host side Host side Line side, derived from ring Line side, drawn from ring while off-hook ring, applied applied from ring Earth ground ring signal applied ring ring signal applied across ring corner frequency Clare application circuit VRMS common-mode signal across ring
Rev.
CPC5620/CPC5621
Parameter Transmit Receive Insertion Loss Average In-band Noise Harmonic Distortion Transmit Level Receive Level RX+/RX- Output Drive Current TX+/TX- Input Impedance Isolation Characteristics Isolation Voltage Surge Rise Time Input Threshold Voltage High Level Input Current Level Input Current RING Output Logic Levels Output High Voltage Output Voltage -0.4 1500 2000 -120 VRMS V/µS Minimum -0.4 Typical -126 Maximum Unit dBm/Hz VP-P VP-P Conditions kHz, resistive termination application circuit with MODE de-asserted reactive termination application circuit with MODE asserted. flat bandwidth dBm, harmonic Single-tone sine wave. into Single-tone sine wave. into Sink source
MODE, Control Logic Inputs
-120
www.clare.com
Specifications subject change without notice. performance characteristics based Clare application circuits. Functional operation device conditions beyond those specified here implied. specifications
VINVDD VIN=GND IOUT -400 IOUT
Line side host side damage ring
Rev.
CPC5620/CPC5621 Description
Name TXSM TXTX+ MODE RING Function Host (CPE) side power supply Transmit summing junction Negative differential transmit signal from host Positive differential transmit signal from host Transmit differential amplifier output When asserted low, changes gain path path accommodate reactive termination networks Host (CPE) side analog ground Assert logic off-hook operation Indicates ring signal, pulsed high Assert logic while hook place information pins. Negative differential analog signal received from telephone line. Must coupled with Figure Pinout
TXSM TXTX+ MODE RING RXRX+ SNP+ SNPRXF REFL TXSL BRNTS DCS1 DCS2 BRRPB VDDL
SNP+ SNP15 VDDL BR21 DCS2 DCS1 BR28 TXSL REFL
Positive differential analog signal received from telephone line. Must coupled with Positive differential snoop input Negative differential snoop input
Receive photodiode summing junction Power supply line side, regulated from ring. Receive isolation summing junction Receive pre-bias current Bridge rectifier return Electronic inductor DCR/current limit feedback output slope control Network amplifier feedback External MOSFET gate control Receive signal input Bridge rectifier return Transmit photodiode summing junction Receiver impedance Transmit transconductance gain Transmit photodiode amplifier output 1.25 reference
Receive photodiode amplifier output
www.clare.com
Rev.
CPC5620/CPC5621
Application Circuits
LITELINK used with telephone networks worldwide. Some public telephone networks, notably North America Japan require resistive line temrination. Other telephone networks Europe elsewhere require reactive line termination. application circuits below address both line termination models. reactive termination application circuit (see Section page describes TBR-21 implementation. This circuit adapted easily other reactive termination needs. Worldwide applications LITELINK described more fully Clare application note AN-147, Worldwide Application LITELINK.
Resistive Termination Application Circuit
Figure Resistive Termination Application Circuit Schematic
(RTX) 80.6K TXTX+ RING RXRX+ TXSM TXTX+ MODE RING LITELINK REFL TXSL BRNTS BRR5 (RTXF) 60.4K
(RNTX) 261K (RNTS) (RGAT) (RNTF) 499K (RDCS2) 1.69M (RZDC) (RHNTF) 200K BRR18 (RZTX) 3.32K
0.01 500V 0.01 500V CPC5602C BRR22 (RDCS1A) (RDCS1B) (CGAT) BRC12 (CDCS) 0.027 (RVDDL) (RHTX) 221K (RZNT) BRTIP RING NOTE: Unless otherwise noted, resistors Ohms, capacitors microFarads. (RSNP-1) 1.8M 1/10W (RSNP+1) 1.8M 1/10W
SNP+ SNP15
design tested found comply with Part with this part. Other compliance requirements require different part. power supplies require substitution inductor, Toko 380HB-2215 similar. Power Quality section Clare appli-
DCS1 DCS2 BRRPB VDDL (RRXF) 130K (RPB) 68.1 BRC7 (CSNP-) 220pF 2000V (RSNPD) 1.5M
(RSNP+2) (CSNP+) 1.8M 1/10W 220pF 2000V
(RSNP-2) 1.8M 1/10W
cation note AN-146, Guidelines Effective LITELINK Designs more information. enhanced trans-hybrid loss.
www.clare.com
Rev.
CPC5620/CPC5621
2.1.1 Resistive Termination Application Circuit Part List
Quantity
Reference Designator C13, C10, C151 (optional) R44, R451
Description ±10% ±10% 0.01 ±10% 0.027 ±10% ±10% ±10% 80.6 1/16 1/16 1/16 68.1 1/16 60.4 1/16 1/10
Suppliers
Panasonic, AVX, Novacap, Murata, SMEC, etc.
1/16 1/16 1/16 1/16 1/16 1.69 1/16 1/16 3.32 1/16 1/16 1/16 1/16 1/16 ±5%, inductor 1/16 1/16 ferrite bead SIZB60 bridge rectifier P3100SB Sidactor CPC5602 CPC5620 LITELINK
Through-hole components offer significant cost savings over SMT.
Rev.
www.clare.com
Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S similar Shindengen, Diodes, Inc. Teccor, Microelectronics, Clare
CPC5620/CPC5621 Reactive Termination Application Circuit
Figure Reactive Termination Application Circuit Schematic
(RTX) 80.6K TXTX+ RING RXRX+ TXSM TXTX+ MODE RING
LITELINK REFL TXSL BRNTS DCS1 DCS2 BRRPB VDDL (RNTF) 221K (RDCS2) 1.69M (RNTX) 110K (RNTS) BRR5 (RTXF) 60.4K 0.01 500V 0.01 500V
BRBR+
(CGAT) (RVDDL) (RZTX)
CPC5602C
(RDCS1A) (RDCS1B)
(RGAT)
RXC4 SNP+ SNP15 (RRXF) 130K
(RZDC) 22.1 (RHNTF) 200K
BRBR-
(CDCS) 0.027
(RPB) 68.1
(RHTX) 200K
RING
(RZNT1)
(CZNT) 0.68
(RZNT2)
NOTE: Unless otherwise noted, resistors Ohms, capacitors microFarads.
(CSNP-) 220pF 2000V (RSNPD) 1.5M (RSNP-2) 1.8M 1/10W (RSNP-1) 1.8M 1/10W
(RSNP+2) (CSNP+) 1.8M 1/10W 220pF 2000V
(RSNP+1) 1.8M 1/10W
design tested found comply with Part with this part. Other compliance requirements require different part. power supplies require substitution inductor, Toko 380HB-2215 similar. Power Quality section Clare application note AN-146, Guidelines Effective LITELINK Designs more information.
www.clare.com
Rev.
CPC5620/CPC5621
2.2.1 Reactive Termination Application Circuit Part List
Quantity
1Through-hole
Reference Designator C13, C10, C151 R44, R451
Description ±10% ±10% 0.01 ±10% 0.027 ±10% ±10% 0.68 ±10% 80.6 1/16 1/16 1/16 68.1 1/16 60.4 1/16 1/10
Supplier
Panasonic, AVX, Novacap, Murata, SMEC, etc.
1/16 1/16 1/16 1/16 1/16 1/16 1.69 1/16 22.1 1/16 1/16 1/16 1/16 1/16 1/16 ±5%, inductor 1/16 1/16 ferrite bead SIZB60 bridge rectifier P3100SB Sidactor CPC5602 CPC5620 LITELINK
components offer significant cost savings over SMT.
Rev.
www.clare.com
Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S similar Shindengen, Diodes, Inc. Teccor, Microelectronics, Clare
CPC5620/CPC5621
Using LITELINK
full-featured telephone line interface, LITELINK performs following functions: termination impedance control slope control 2-wire 4-wire conversion (hybrid) Current limiting Ring signal reception Caller signal reception Switch hook hook state, loop current flows through LITELINK system answering placing call.
On-hook Operation
LITELINK application circuit leakage current less than with across ring tip, equivalent greater than on-hook resistance.
This section data sheet describes LITELINK operation standard configuration usual operation. Clare offers additional application information online (see Section page 14). These include information following topics: Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection considerations
Other specific application materials also referenced this section appropriate.
Switch Hook Control (On-hook Off-hook States)
LITELINK operates conditions, on-hook off-hook. on-hook condition telephone line available calls. off-hook condition telephone line engaged. control input place LITELINK these states. With high, LITELINK on-hook ready make receive call. snoop circuit enabled. Assert place LITELINK off-hook state. off10
High transmit power operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (911 feature) Battery reversal detection Line presence detection World-wide programmable operation
www.clare.com
on-hook state asserted), internal multiplexer turns snoop circuit. This circuit monitors telephone line conditions; incoming ring signal, caller data bursts.
Refer application schematic diagram (see Figure page (CSNP-) (CSNP+) provide high-voltage isolation barrier between telephone line SNP- SNP+ LITELINK while coupling signals snoop amplifier. snoop circuit "snoops" telephone line continuously while drawing current. LITELINK, ringing signals compared threshold. comparator output forms RING signal output from LITELINK. This signal must qualified host system valid ringing signal. level RING indicates that LITELINK ring signal threshold been exceeded. CPC5620 (with half-wave ring detector), frequency RING output follows frequency ringing signal from central office (CO), typically RING output CPC5621 (with full-wave ring detector) twice ringing signal frequency. Hysteresis employed LITELINK ring detector circuit provide noise immunity. setup ring detector comparator causes RING output pulses remain most ringing signal half-cycle. RING output returns high entire negative half-cycle ringing signal CPC5620. CPC5621, RING output returns high short period near zero-crossing ringing signal before returning during positive half-cycle. both CPC5620 CPC5621, RING output remains high between ringing signal bursts. ring detection threshold depends values (RSNPD), (RSNP-), (RSNP+), (CSNP-), (CSNP+). values these components shown typical application circuits recommended
LITELINK accommodate specific application features without sacrificing basic functionality performance. Application features include, limited
3.2.1 Ring Signal Reception Snoop Circuit
Rev.
CPC5620/CPC5621
typical operation. ring detection threshold changed according following formula:
750mV RINGPK
RING
North American applications, follow these steps receive on-hook caller data LITELINK outputs: Detect first ringing signal outputs RING. Assert low. Process data from outputs. De-assert (high floating).
3.2.3 On-hook Caller Signal Reception
On-hook caller (CID) signals processed LITELINK coupling data burst through snoop circuit LITELINK outputs under control pin. North America, data signals typically sent between first second ringing signal.
Figure On-hook Caller Signal Timing North America CPC5620 (with Halfwave Ring Detect)
Caller data
RING First Ring
Second Ring
Signal levels scale
full-wave ring detector CPC5621 makes possible detect ring polarity reversal using RING output. When polarity ring reverses, pulse RING indicates event. Your host system must able discriminate this single pulse approximately msec (using recommended snoop circuit external components) from valid ringing signal.
GAIN
3.2.2 Polarity Reversal Detection with CPC5621
gain from ring determined
Clare Application Note AN-117 Customize Caller Gain Ring Detect Voltage Threshold spreadsheet trying different component values this circuit. Changing ring detection threshold will also change caller gain timing polarity reversal detection pulse, used.
Note: Taking LITELINK off-hook (via pin) disconnects snoop path from both receive outputs RING output, regardless state pin.
where frequency data signal. recommended components application circuit yield gain 0.27 Clare Application Note AN-117 Customize Caller Gain Ring Detect Voltage Threshold spreadsheet trying different component values this circuit. Changing gain will also change ring detection threshold timing polarity reversal detection pulse, used. single-ended snoop circuit output dBm, total resistance across series resistors (R6/ R7/R45)
Off-Hook Operation
3.3.1 Receive Signal Path
Signals from telephone network appear ring connections application circuit. Receive signals extracted from transmit signals LITELINK two-wire four-wire hybrid. Next, receive signal converted infrared light receive photodiode amplifier receive path LED. intensity light modulated receive signal coupled across electrical isolation barrier reflective dome. host equipment side barrier, receive signal converted photodiode into photocurwww.clare.com
Rev.
CPC5620/CPC5621
rent. photocurrent, linear representation receive signal, amplified converted differential voltage output RX-. Variations gain controlled within ±0.4 factory gain trim, which sets output photoamplifier unity gain. accommodate single-supply operation, LITELINK includes small bias outputs Vdc. Most applications should couple outputs shown Figure LITELINK used differential single-ended output shown Figure Single-ended will produce less signal output amplitude. exceed into (2.2 VP-P) signal input with standard application circuit. application note AN-149, Increased LITELINK Transmit Power more information. unity factory, limiting insertion loss ±0.4
Figure Differential Single-ended Transmit Path Connections LITELINK
Host CODEC Transmit Circuit LITELINK
0.1uf TXA1 0.1uf
TXTX+
TXA2
Host CODEC Transmit Circuit
TXA1
0.1uf 0.1uf
LITELINK
TXTX+
Figure Differential Single-ended Receive Path Connections LITELINK
Host-side CODEC Voice Circuit
RX0.1uF 0.1uF
LITELINK
RXRX+
0.1uF
3.3.2 Transmit Signal Path
Connect transmit signals from host equipment pins LITELINK. exceed signal level VP-P). Differential transmit signals converted single-ended signals LITELINK. signal coupled transmit photodiode amplifier similar manner receive path. output photodiode amplifier coupled voltage-to-current converter transconductance stage where transmit signal modulates telephone line loop current. receive path, gain
Start-up Requirements
must de-asserted (set logic high) once after power-up least transfer internal gain trim values within LITELINK. This would normal operation most applications.
Characteristics
CPC5620 CPC5621 designed worldwide application regarding characteristics, including under requirements TBR-21. ZDC, DCS1, DCS2 pins control slope characteristics LITELINK. Selecting appropriate resistor values RZDC (R16) RDCS (R15) provided application circuits assure compliance with requirements.
3.5.1 Non-Current Limited Applications
LITELINK includes telephone line current limit feature that selectable selecting desired value RZDC (R16) using following formula:
Amps 0.011A
Clare recommends using RZDC North America Japan, limiting telephone line current www.clare.com
Rev.
CPC5620/CPC5621
3.5.2 Current Limited Applications
TBR-21 sets telephone line current limit meet this requirement, RZDC (R16) 22.1 Clare application note AN-146 Guidelines Effective LITELINK Designs information heat sinking this application.
Characteristics
3.6.1 Resistive Termination Applications
North American Japanese telephone line termination requirements with resistive termination. Receive termination applied LITELINK (pin resistor, RZNT (R10).
3.6.2 Reactive Termination Applications
Many countries single-pole complex impedance model telephone network transmission line characteristic impedance shown table below. Line Impedance Model TBR-21
Matching complex impedance requires complex network shown "Reactive Termination Application Circuit" page
3.6.3 Mode Usage
Assert MODE introduce into transmit path gain receive path. These changes compensate gain changes made transmit receive paths reactive termination implementations. Insertion loss with MODE de-asserted resistive termination application circuit Insertion loss with reactive termination application circuit MODE asserted also
www.clare.com
Australian
Rev.
CPC5620/CPC5621
Regulatory Information
LITELINK used build products that comply with requirements TIA/EIA/IS-968 (formerly part 68), part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, many other standards. LITELINK complies with requirements UL1577. LITELINK provides supplementary isolation. Metallic surge requirements through inclusion Sidactor application circuit. Longitudinal surge protection provided LITELINK's optical-across-thebarrier technology high-voltage components application circuit needed. information provided this document intended inform equipment designer sufficient assure proper system design regulatory compliance. Since equipment manufacturer's responsibility have their equipment properly designed conform relevant regulations, designers using LITELINK advised carefully verify that their end-product design complies with applicable safety, EMC, other relevant standards regulations. Semiconductor components rated withstand electrical overstress electro-static discharges resulting from inadequate protection measures board system level.
LITELINK Design Resources
Clare, Inc. Design Resources
Clare, Inc. site wealth information useful designing with LITELINK, including application notes reference designs that already meet applicable regulatory requirements. LITELINK data sheets also contains additional application design information. following links: LITELINK datasheets reference designs
Application note AN-107 LOCxx Series Isolated Amplifier Design Principles Application note AN-114 ITC117P Application note AN-117 Customize Caller-ID Gain Ring Detect Voltage Threshold CPC5610/11 Application note AN-140, Understanding LITELINK Application note AN-141, Enhanced Pulse Dialing with LITELINK Application note AN-143, Loop Reversal Detection with LITELINK Application note AN-146, Guidelines Effective LITELINK Designs Application note AN-147, Worldwide Application LITELINK
www.clare.com
Application note AN-149, Increased LITELINK Transmit Power Application note AN-150, Ground-start Supervision Circuit Using IAA110.
Third Party Design Resources
following also contain information useful designs. books available amazon.com. Understanding Telephone Electronics, Stephen Bigelow, al., Butterworth-Heinemann; ISBN: 0750671750 Newton's Telecom Dictionary, Harry Newton, Books; ISBN: 1578200695 Photodiode Amplifiers: Solutions, Jerald Graeme, McGraw-Hill Professional Publishing; ISBN: 007024247X Teccor, Inc. Surge Protection Products United States Code Federal Regulations, Part 68.3
Rev.
CPC5620/CPC5621
LITELINK Performance
following graphs show LITELINK performance using North American application circuit shown this data sheet.
Figure Receive Frequency Response
Figure Transmit Ring
Gain
THD+N
-100
1000 1500 2000 2500 3000 3500 4000
-120 -140
1000 1500 2000 Frequency 2500 3000 3500 4000
1000 1500 2000 2500 3000 3500 4000
Frequency
Figure Transmit Frequency Response
Gain
1000 1500 2000 2500 3000 3500 4000
Frequency
1000 1500 2000 Frequency 2500 3000 3500 4000
Figure Trans-Hybrid Loss
Figure Receive
Figure Return Loss
THD+N
Return Loss (dB)
-100
-120
-140
1000 1500 2000 Frequency (Hz) 2500 3000 3500 4000
Rev.
www.clare.com
Frequency
CPC5620/CPC5621
Figure Snoop Circuit Frequency Response
Gain (dBm
1000 1500 2000 2500 3000 3500 4000 Frequency (Hz)
Figure Snoop Circuit
1.5K
2.5K 3.5K
Figure Snoop Circuit Common Mode Rejection
-2.5 -7.5 -12.5 -17.5 -22.5 -27.5 CMRR (dBm) -32.5 -37.5 -42.5 -47.5 -52.5 -57.5 Frequency (Hz)
www.clare.com
Rev.
CPC5620/CPC5621
Manufacturing Information
Mechanical Dimensions
Figure Dimensions
10.287 .254 (0.405 0.010) Max.
7.493 0.127 (0.295 0.005)
10.363 0.127 (0.408 0.005)
0.635 0.076 (0.025 0.003)
9.525 0.076 (0.375 0.003)
1.650 (0.065)
2.134 Max. (0.084 Max.)
0.051 0.051 (0.002 0.002)
11.380 (0.448) 9.730 (0.383)
1.981 0.051 (0.078 0.002)
7.239 0.051 (0.285 0.002) 0.635 (0.025 45°) 1.016 Typ. (0.040 Typ.) 0.203 (0.008)
0.330 0.051 (0.013 0.002)
Coplanar 0.08/(0.003)
Figure Recommended Printed Circuit Board Layout
0.635 (0.025)
0.330 (0.013)
Rev.
www.clare.com
DIMENSIONS
(Inches)
Tape Reel Packaging
Figure Tape Reel Dimensions
330.2 DIA. (13.00) Cover Tape Thickness .102 MAX. (.004) 12.090 (.476) 6.731 MAX. (.265) 1.753 .102 (.069 .004) .406 MAX. (.016) 7.493 .102 (.295 .004) 3.20 (.126) 2.70 (.106) 2.007 .102 1.498 ±.102 3.987 .102 (.079 .004)(.059 .004) (.157 ±.004)
Feed Direction
11.989 .102 (.472 .004) 10.897 .025 (.429 .001)
16.002 .305 (.630 .012) 10.693 .025 (.421 .001)
Embossed Carrier
Cover Tape Embossment
.050R TYP.
1.549 .102 (.061 .004)
Washing
Dimensions (inches)
Soldering
7.3.1 Moisture Reflow Sensitivity
which were used determine moisture sensitivity level this component.
Clare characterized moisture reflow sensitivity LITELINK using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs diffusion. During solder reflow process, which component attached PCB, whole body component exposed high process temperatures. combination moisture uptake high reflow soldering temperatures lead moisture induced delamination cracking component. prevent this, this component must handled accordance with IPC/JEDEC standard J-STD-020A labeled moisture sensitivity level (MSL), level
Clare does recommend ultrasonic cleaning LITELINK.
7.3.2 Reflow Profile
maximum ramp rates, dwell times, temperatures assembly reflow profile should exceed those specified IPC/JEDEC standard J-STD-020A, additional information please visit www.clare.com
Clare, Inc. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. Neither circuit patent licenses indemnity expressed implied. Except forth Clare's Standard Terms Conditions Sale, Clare, Inc. assumes liability whatsoever, disclaims express implied warranty relating products, including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. products described this document designed, intended, authorized, warranted components systems intended surgical implant into body, other applications intended support sustain life, where malfunction Clare's product result direct physical harm, injury, death person severe property environmental damage. Clare, Inc. reserves right discontinue make changes products time without notice. Specification: DS-CPC5620/CPC5621-R0.E Copyright 2002, Clare, Inc. LITELINKis trademark Clare, Inc. rights reserved. Printed USA. 5/14/2002

Other recent searches


V048F040T050 - V048F040T050   V048F040T050 Datasheet
V048F040M050 - V048F040M050   V048F040M050 Datasheet
TPC6104 - TPC6104   TPC6104 Datasheet
SP8904 - SP8904   SP8904 Datasheet
DS4358 - DS4358   DS4358 Datasheet
HMC-C005 - HMC-C005   HMC-C005 Datasheet
CSS-1816DF - CSS-1816DF   CSS-1816DF Datasheet
1817DF - 1817DF   1817DF Datasheet
CSS-1817DF - CSS-1817DF   CSS-1817DF Datasheet
BLD1501H - BLD1501H   BLD1501H Datasheet
BLD05002S - BLD05002S   BLD05002S Datasheet
2SK3108 - 2SK3108   2SK3108 Datasheet
2N7002V - 2N7002V   2N7002V Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive