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CS4328

18-Bit, Stereo D / A Converter for Digital Audio

CS4328
18-Bit, Stereo D / A Converter for Digital Audio
Features General Description
Rates · Adjustable System Sampling & 48kHz including 32kHz, 44.1kHz
· 120 dB Signal-to-Noise Ratio · Low Clock Jitter Sensitivity · Completely Filtered Line-Level Outputs Linear Phase Filtering
Interface · Flexible Serial Data for Either 16 or 18 bit Input Zero Phase Error Between Channels No External Components Needed
ORDERING INFORMATION: CS4328-KP 0 to 70 °C 28-pin Plastic CS4328-KS 0 to 70 °C 28-pin Plastic CS4328-BP -40 to +85 °C 28-pin Plastic CS4328-BS -40 to +85 °C 28-pin Plastic CDB4328 CS4328 Evaluation Board
DIP SOIC DIP SOIC
DIF0 13 LRCK BICK SDATAI 20 19 18
DIF1 12
VD+ 16
DGND 17
AGND1 1
VA+ 3 28 -VREF
Serial Input Interface 8x Interpolator Delta-Sigma Delta-Sigma Modulator Modulator
Voltage Reference
TST RST
10 9 8x Interpolator Interpolator Calibration Microcontroller 21 CALO 8 CMPI Delta-Sigma Delta-Sigma Modulator Modulator Clock Osc / Divider 14 15 11 22 24 ACKI DAC
Analog Low-Pass Filter
MOSFET Output Stage
2 AOUTL
Analog Low-Pass Filter
MOSFET Output Stage
26 AOUTR 4 25 AGND2 AGND3
27 CALI
6 CMPO
XTI XTO CKS ACKO
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com
CS4328
ANALOG CHARACTERISTICS
Parameter Symbol Specified Temperature Range Resolution TA CS4328-K Min Typ Max 0 16 +70 CS4328-B Min Typ Max -40 16 +85 Units °C Bits
Dynamic Performance
Total Harmonic Distortion + Noise (A-Weighted) THD+N 0 dB Output, -20 dB Output, -60 dB Output, Deviation From Linear Phase Passband: to -3 dB corner to 0.00025 dB corner (Note 2) (Notes 3, 4) (Notes 3, 4) -
dc Accuracy
Analog Output
Full Scale Output Voltage VOUT 3.8 4.0 4.2 3.8 4.0 4.2 Vpp
Power Supplies
Power Supply Current: VA+ VAVD+ IA+ IAID+ (1 kHz) PSRR 40 -40 50 650 50 55 -55 60 850 40 -40 50 650 50 55 -55 60 850 mA mA mA mW dB
Power Dissipation Power Supply Rejection Ratio
CS4328
DIGITAL CHARACTERISTICS
Note: 5. TST, DIF0 & DIF1 have internal pull-down devices, nominally 90k.
(VD+)+0.4 125 150
WARNING: Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
DS62F3
CS4328
SWITCHING CHARACTERISTICS
2 periods of XTI / XTO
Note:
6. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling."
LRCK t blrs t blrd BICK t sbs SDATAI t bsh t bickl t bickh
LRCK t blrs t blrd BICK t sbs SDATAI MSB t bsh MSB-1 t t bickl bickh
Serial Input Timing (Modes 0, 1, &3)
Serial Input Timing (Mode 2)
DS62F3
CS4328
+5V Digital 10 µF + 0.1 µF 16 VD+ 20 Audio Data Processor 19 18 LRCK BICK SDATAI VREFNC NC XTO AOUTL 14 15 pF 22 24 External Clock 11 Mode Select 13 12 9 XTI AOUTR ACKO ACKI CMPO CKS DIF0 DIF1 RST TST DGND 10 17 AGND3 AGND2 25 4 AGND1 1 CALO CALI CMPI 6 8 21 27 CS4328 D / A CONVERTER 0.1 µF 3 VA+ VA5 0.1 µF 28 0.1 µF
+5V Analog 10 µF 0.1 µF -5V Analog 10 µF
optional crystal oscillator 7 23 74HC device 10 pF 1.2 M 15
2 51 26 51 10 nF NPO 10 nF NPO
Power Up / Cal. Control
Figure 1. Typical Connection Diagram
DS62F3
LRCK (kHz) 32 32 44.1 44.1 48 48 CKS low high low high low high XTI / XTO (MHz) 8.192 12.288 11.2896 16.9344 12.288 18.432 ACKO (MHz) 4.096 4.096 5.6448 5.6448 6.144 6.144
Table 1. Common Clock Frequencies
DS62F3
CS4328
RST LRCK "Kickstart" XTI / XTO ACK0
40 ns minimum
Reset Status
Exit Reset
Figure 2. RESET Cancellation Timing
Reset and Offset Calibration RST is an active low signal that resets the digital filter and the delta-sigma modulator, synchronizes LRCK with internal control signals and starts an offset calibration cycle upon exiting reset. When RST goes low, CALO goes high and stays high until the end of an offset calibration cycle. An offset calibration cycle takes 1024 IWR cycles to complete. CALO must be connected to CALI and CMPO must be connected to CMPI for offset calibration. During an offset calibration the analog output is forced to zero. Power-Up Considerations Upon initial application of power to the DAC, offset calibration and digital filter registers will be indeterminate. RST should be low during power-up to activate an internal mute and prevent this erroneous information from being output from the DAC. Bringing RST high will begin a calibration cycle and initialize these registers. Muting There are two types of mutes that can be implemented with the CS4328. The first is a -50 dB
Table 2. Digital Input Formats
DS62F3
CS4328
LRCK BICK SDATAI Mode 0 SDATAI Mode 1 1 0
Left Channel
Right Channel
Figure 3. Digital Input Formats 0 & 1
LRCK BICK SDATAI 16 Bit SDATAI 18 Bit
Left Channel
Right Channel
Figure 4. Digital Input Format 2
LRCK BICK SDATAI 16 Bit SDATAI 18 Bit
Left Channel
Right Channel
Figure 5. Digital Input Format 3
Left Channel
Right Channel
BICK SDATAI Mode 2 BICK SDATAI Mode 0
SDATAI
Mode 3
LRCK must be inverted.
Figure 6. Digital Input Formats 0, 2 and 3 with 16 BICK Periods
DS62F3
CS4328 clean -5 volt supply. VD+, which powers the digital interpolation filter and delta-sigma modulator, may be powered from the system +5 volt logic supply. Decoupling capacitors should be located as near to the CS4328 as possible. The printed circuit board layout should have separate analog and digital regions with individual ground planes. The CS4328 should straddle the ground plane break as shown on the CDB4328 Evaluation board. Optional jumpers for connecting these planes should be included near the DAC, where power is brought on to the board and near the regulators. All signals, especially clocks, should be kept away from the VREF- pin to avoid unwanted coupling into the CS4328. The VREF- decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from VREF- to Pin 1 AGND and to minimize the path between VREF- and the capacitors. Extensive use of ground plane fill on both the analog and digital sections of the circuit board will yield large reductions in radiated noise effects. An application note "Layout and Design Rules for Data Converters" is printed in the Application Note section of this book. Analog Output and Filtering Full scale analog output for each channel is typically 4V peak-to-peak. The analog outputs can drive load impedances as low as 600 and are short-circuit protected to 20mA. The CS4328 analog filter is a 5th order switched-capacitor filter followed by a secondorder continuous-time filter. The switched-capacitor filter is clock dependent and will scale with the IWR frequency. The continuous-time filter is fixed and not related to IWR. A low-pass filter consisting of a 51 resistor and a .01 µF NPO capacitor is recommended on the analog outputs.
CS4328 21 CALO CALI
27 MUTE
Figure 7. -50dB Muting
mute which can be activated by forcing the CALI pin high. Figure 7 shows how to implement a -50 dB mute using an OR gate. The propagation of the gate will be the only delay in moving the CS4328 to a muted state.
CS4328 18 SDATAI
Figure 8. -120 dB Muting
The second mute option is a two stage operation which involves forcing SDATAI to 0 using an AND gate as shown in Figure 8. The first mute occurs following 33 LRCK cycles when the 0 input data propagates to the output of the DAC. The rms noise present at the output will typically be 93 dB below fullscale. Following a total of 4096 LRCK cycles with 0 input data the output of the CS4328 will mute and lower the output rms noise to a minimum of 120 dB below fullscale. Upon release of the MUTE command and non-zero input data the CS4328 output mute will immediately release. However, 33 LRCK cycles are required for input data to propagate to the output of the CS4328. Grounding and Power Supply Decoupling As with any high resolution converter, the CS4328 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangements with VA+ connected to a clean +5 volt supply and VA- connected to a
DS62F3
10 DS62F3
CS4328
CRYSTAL 2.0 1.5 1.0 -86 0.5 0.0 -0.5 -1.0 -96 -1.5 -2.0 10 100 1k 10k 30k -98 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -88 -90 -92 -94 FRQRSP48 AMPL(dBr) vs GENFRQ(Hz) CRYSTAL THDAM18A -80 -82 -84 THD+N(dBr) vs GENAMP(dBFS)
Figure 9. Frequency Response (48 kHz word rate)
CRYSTAL NOISE 0 -20 -40 AMP1(dBr) & AMP1(dBr) vs FREQ(kHz)
Figure 12. THD+N vs 18-bit Input Signal Level
CRYSTAL TR20R 10 8 6 4 BANDPASS(dBr) vs LEVEL(dBr)
Figure 10. Muted Idle Channel Noise
CRYSTAL NOISEUNM 0 -20 1.583 -40 -60 -80 -100 0.333 -120 -140 -160 0.02 9.82 -0.083 1.167 AMP1(dBr) vs FREQ(kHz) CRYSTAL 2.000
Figure 13. Fade-to-Noise Linearity
IMPULSE AMP1(V) vs TIME(usec)
Figure 11. Unmuted Idle Noise DS62F3
Figure 14. Impulse Response 11
CS4328
CRYSTAL M90DB1K 0 -20 -40 -60 -80 -100 -120 -640 -140 20 100 1k 10k 20k -800 0 5 10 15 20 25 30 35 40 45 50 AMP1(dBr) vs FREQ(kHz) CRYSTAL 800 640 480 320 160 0 -160 -320 -480 MONOTON AMP1(uV) vs TIME(msec)
Figure 15. 1 kHz, -90 dB Input FFT Plot
CRYSTAL 250 200 -20 150 100 50 0 -50 -100 -150 -200 -250 0.0 0.50 1.00 1.50 2.00 2.50 3.00 -120 -140 20 -80 -100 -40 -60 M90TIME AMP1(uV) vs TIME(msec)
Figure 17. Monotonicity Test (16-bit data)
CRYSTAL 1k 0dBFFT 0 AMP1(dBr) vs FREQ(Hz)
Figure 16. 1 kHz, -90 dB Input Time Domain Plot
CRYSTAL 0 -20 -40 -60 -80 -100 -120 -140 20 100 1k 1KM10DB
Figure 18. 1 kHz, 0 dB Input FFT Plot
AMP1(dBr) vs FREQ(Hz)
Figure 19. 1 kHz, -10 dB Input FFT Plot 12 DS62F3
CS4328
Audio Data
8x Interpolator
Delta Sigma Modulator
Switched Continuous Cap Time LPF Filter Analog Filter
Analog Output
Figure 20. CS4328 Architecture
f (kHz)
Figure 23. Spectrum After S / H
f (kHz)
Figure 21. Input Data Spectrum
Figure 24. Modulator Output Spectrum 24 8Fs 16Fs f (kHz)
f(kHz)
Figure 22. 8X Interpolated Data Spectrum
Figures 27-30 are computer simulations of the combined response of the CS4328 digital and analog filters with an input word rate of 48 kHz. Figure 27 shows the individual and combined phase response of the CS4328 filters. Notice the digital filter equalization of the analog filter to produce a linear phase response. Figures 28-30 are plots of the CS4328 magnitude response.
20 16 12 Phase (degrees)
f (kHz)
Analog Filter
8 4 0 -4 -8 -12 -16 Digital Filter Total Phase
Figure 25. Spectrum After Switched-Capacitor Filter
f (kHz)
-20 0 2 4 6 8 10 12 14 Frequency (kHz) 16 18 20
Figure 26. Spectrum After Continuous Time Filter Figure 27. Deviation From Linear Phase
DS62F3
CS4328
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 8 16 24 32 Input Frequency (kHz) 40 48
Magnitude (dB)
Figure 28. Combined Digital and Analog Filter Frequency Response
1 0 -1 Magnitude (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 20 21 22 23 Input Frequency (kHz) 24 25
Figure 29. Combined Digital and Analog Filter Frequency Response
0 -10 -20 Magnitude (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 22 23 24 25 26 27 Input Frequency (kHz) 28 29 30
Figure 30. Combined Digital and Analog Filter Transition Band DS62F3 15
CS4328 PIN DESCRIPTIONS
ANALOG GROUND ANALOG LEFT CHANNEL OUTPUT ANALOG POWER ANALOG GROUND NEGATIVE ANALOG POWER COMPARATOR OUTPUT NO CONNECT COMPARATOR INPUT RESET TEST CLOCK SELECT DIGITAL INPUT FORMAT 1 DIGITAL INPUT FORMAT 0 CRYSTAL OR CLOCK INPUT AGND1 AOUTL VA+ AGND2 VACMPO NC CMPI RST TST CKS DIF1 DIF0 XTI
VREF- VOLTAGE REFERENCE OUTPUT CALI CALIBRATION INPUT AOUTR ANALOG RIGHT CHANNEL OUTPUT AGND3 ANALOG GROUND ACKI ANALOG CLOCK INPUT NC NO CONNECT ACKO ANALOG CLOCK OUTPUT CALO CALIBRATION OUTPUT LRCK LEFT / RIGHT CLOCK INPUT BICK SERIAL BIT CLOCK INPUT SDATAI SERIAL DATA INPUT DGND DIGITAL GROUND VD+ DIGITAL POWER XTO CRYSTAL OSCILLATOR OUTPUT
Power Supply Connections VA+ - Positive Analog Power, PIN 3. Positive analog supply. Nominally +5 volts. VA- - Negative Analog Power, PIN 5. Negative analog supply. Nominally -5 volts. AGND1, AGND2, AGND3 - Analog Grounds, PINS 1, 4, 25. Analog ground reference. VD+ - Positive Digital Power, PIN 16. Positive supply for the digital section. Nominally +5 volts. DGND - Digital Ground, PIN 17. Digital ground for the digital section. Analog Outputs VREF- - Voltage Reference Output, PIN 28. Nominally -3.68 volts. Normally connected to a 0.1µF ceramic capacitor in parallel with a 10µF or larger electrolytic capacitor. Note the negative output polarity. AOUTL - Analog Left Channel Output, PIN 2. Analog output for the left channel. Typically 4V peak-to-peak for a full-scale input signal. AOUTR - Analog Right Channel Output, PIN 26. Analog output for the right channel. Typically 4V peak-to-peak for a full-scale input signal.
DS62F3
DS62F3 17
DS62F3
28 pin Plastic DIP
SEATING PLANE
NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX 3.94 4.32 5.08 0.155 0.170 0.200 A A1 0.51 0.76 1.02 0.020 0.030 0.040 0.36 0.46 0.56 0.014 0.018 0.022 B B1 1.02 1.27 1.65 0.040 0.050 0.065 C 0.20 0.25 0.38 0.008 0.010 0.015 36.45 36.83 37.21 1.435 1.450 1.465 D E1 13.72 13.97 14.22 0.540 0.550 0.560 e1 2.41 2.54 2.67 0.095 0.100 0.105 eA 15.24 15.87 0.600 0.625 L 3.18 0.150 3.81 0.125 0° 15° 15° 0°
pins 16 20 24
MILLIMETERS MIN NOM MAX 9.91 10.16 10.41 12.45 12.70 12.95 14.99 15.24 15.50 17.53 17.78 18.03 MILLIMETERS MIN NOM MAX
INCHES MIN NOM MAX 0.390 0.400 0.410 0.490 0.500 0.510 0.590 0.600 0.610
INCHES MIN NOM MAX
0.33 0.46 0.51 0.013 0.018 0.020 0.203 0.280 0.381 0.008 0.011 0.015 see table above
CDB4328
CS4328 Evaluation Board
Features General Description
The CDB4328 evaluation board allows fast evaluation of the CS4328 18-bit, stereo D / A converter. The board provides an analog output interface via BNC connectors for both channels. Evaluation requires an analog signal analyzer, a digital signal source, and a power supply. Also included is a CS8412 digital audio receiver I.C., which will accept AES / EBU, S / PDIF, and EIAJ-340 compatible audio data. The CS8412 can provide the system timing necessary to operate the CS4328. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development.
Demonstrates recommended layout and grounding arrangements
· CS4328 Supports multiple input formats · CS8412 Receives AES / EBU, S / PDIF,
& EIAJ-340 Compatible Digital Audio
· Digital and Analog Patch Areas · Operation with on-board CS8412 or
externally supplied system timing
ORDERING INFORMATION: CDB4328
Block Diagram
Digital Audio Input Digital Patch Area -15V GND +15V GND +5V Analog Patch Area
CS8412 Digital Audio Receiver
Power Supply Regulation and Conditioning
Error Info / Channel Status
Timing Signal Selector
CS4328 D / A Converter
AOUTR AOUTL
Offset Calibration Network L / R SCLK SDATA MCLK
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 http://www.crystal.com
VA+ C7 0.47 uF J1
+15V D2 AGND + C4 D3 -15V 47 uF C5 + C3 47 uF C6
U5 IN 78L05 OUT COM 0.22 uF
C8 0.47 uF COM 79L05 OUT U6
0.22 uF IN
RST CS4328
4 U7B 74HC14
Figure 1. Power Supply and Reset Circuitry 22 DS62DB2
CDB4328
VD+ 1 uF C26
0.1 uF C25 7 NC 23 NC
C23 0.1 uF C22 0.1 uF C21 0.1 uF
+5V Analog, C24 VA+ 1.0 uF
VD+ ACKO
ACKI VA+ AGND1 VAAGND2 AGND3
U3, Pin 3 U3, Pin 6 U3, Pin 8 U3, Pin 11
LRCK BICK SDATAI XTI
-5V Analog, C20 VA+ 1.0 uF
U1 CS4328
L / R SCLK SDATA MCLK 15
6 CMPO 8 CMPI 21 CALO 27 CALI 2 R5 AOUTL 51 26 R6 51
TP C18 10 nF NPO TP C19 10 nF NPO C17 10 uF + AOUTL
XTO AOUTR
AOUTR
From Reset Circuit
RST TST DGND CKS 10 17 11 JP2 VD+ VD+ DIFO 13 R11 47k
VREF DIFI 12
28 C16 0.1 uF
Figure 2. CS4328 DAC Connections
The CS4328 supports four serial data input formats. The selection of which is made via the digital input format pins DIF0 and DIF1. The different formats control the relationship of L / R to SDATA and the edge of SCLK used to latch the data. Consult the CS4328 data sheet for an explanation of the different formats.
Position EXT CLK 8412 Input Option Selected SDATA, SCLK, L / R provided by an external source. SDATA, SCLK, L / R provided by the CS8412
System Timing The master clock input to the CS4328 can be provided by several sources. JP3 selects the source of the master clock that is to be supplied to the XTI pin of the converter. When EXT CLK is selected, the master clock is provided by one of two sources. The 12.288 MHz clock signal provided by U8 can be used as the master clock for both the CS4328 and the external system that provides the serial data to the board. The other option is for a master clock that is synchronized to the external serial data coming into the board, be used as the master clock for the CS4328 as well. However, if an external
Table 1. JP3 Selectable Options DS62DB2
DS62DB2
1 1.0 uF U7A VD+ Error Information TP 0.1 uF Pin 20, U1 Pin 19, U1 JP3 7 8 R3 47k 5 6 3 4
EXT CLK
Channel Status VD+ S1 0.1 uF
8 1 NC U6 12.288 MHz VCC GND 7 14 + C14 C13
Ca / E1 SCK 12 47 k R1 4 9 10 12 47 k R12 Ce / F2 VD+ VD+ 11 13 U3 74HC126 47 k R13 MCK 19 8 U2 Cc / F0 CS8412 Cd / F1 SDATA 26 Cb / E2 5 6 7
RP1 7 Pin SIP C27 0.1 uF 9 5 11 4 3 2 27 3 13 1 U4 74HC04
13 16 25 1 14 28 SEL ERF C U VERF FSYNC 11 6 C0 / E0 C29 14 2 3
560 D5 5 D6 10 D7 4 D8 12 D9 2 7 560 560 560 560
Pin 18, U1
Pin 14, U1
VD+ L R 47 k 1 2 RXN Schott 67125450 Pulse PE65612 4 110 R8 10 3 Digital Input 1:1 TP CSLR / FCK 15 CBL RXP 9 M0 23 24 M1 18 M2 17 M3
R7 JP1
8 14 R10 C12 10 1k 7 VD+ 0.1 uF C11 R9 10 +5V Analog 21 22 0.1 uF C10 0.047 uF + 1.0 uF C9 12 7 FILT 20 8 DGND VD+ AGND VA+
0.1 uF C28
CDB4328
Figure 3. CS8412 Digital Audio Receiver Connections
CDB4328 the trace at the SDATA BNC connector and place a jumper between the SDATA BNC and U8 pin 11. CMODE is set LOW for a master clock of 256 times the sample rate. P7 must have both the internal and external jumpers installed. This will route the master clock to the EXTCLKIN BNC fo r co nn ection to the CDB4328 MCLK. If a CS5336 / 8 is installed an additional modification is required to invert the SCLK prior to transmission to the CDB4328. This can be implemented as follows: cut the trace at the SCLK BNC and install a jumper between U7 pin 4 and the SCLK BNC. CDB5336 / 7 / 8 / 9 and CDB4328 Interconnection for Method 2 Shielded coaxial cables with BNC connectors should be used to make the following connections: L / R to L / R, SCLK to SCLK, SDATA to SDATA, EXTCKIN to MCLK. CDB4328 Interfacing to the CDB5326 / 7 / 8 / 9 A method of interfacing the CDB5326 / 7 / 8 / 9 and the CDB4328 requires a direct interface through the EXTCLKIN, SCLK, SDATA, and L / R BNC connectors. This technique requires modifications to the CDB5326 / 7 / 8 / 9 to derive the proper clock frequencies. This is done by utilizing a 12.288 MHz clock and supplying a clock to the CDB5326 / 7 / 8 / 9 at 6.144 MHz. CDB4328 Configuration The CS4328 must be set to receive data in format 2 (DIF1 high and DIF0 low). Modify the jumpers located near pins 12 and 13 of the CS4328. JP2 sets the clock to sample frequency ratio (CKS) on the CS4328 and is set low for a 256 ratio. JP3 selects the source of SDATA, SCLK and L / R that will be provided to the converter and should
DS62DB2 27
be removed to access the multiple clocks from the CDB5326 / 7 / 8 / 9. Remove the 12.288 MHz oscillator (U8). CDB5326 / 7 / 8 / 9 Configuration Remove the clock source jumper (P2). Remove the 6.144 MHz oscillator (U2) and replace with the 12.288 MHz oscillator from the CDB4328. Install a divide by 2 function on the CDB5326 / 7 / 8 / 9 digital patch area. Use a 74HC74 with the D input connected to the Q output. Connect the oscillator output to the 74HC74 clock input. Connect the Q output to U1 pin 23. Position P2 to connect the oscillator output to the EXTCLKIN. CDB5326 / 7 / 8 / 9 and CDB4328 Interconnection Shielded coaxial cables with BNC connectors should be used to make the following connections: L / R to L / R, SCLK to SCLK, SDATA to SDATA, EXTCLKIN to MCLK.
CDB4328
Figure 4. Top Ground Plane Layer (NOT TO SCALE) 28 DS62DB2
CDB4328
Figure 5. Bottom Trace Layer (NOT TO SCALE) DS62DB2 29
CDB4328
Figure 5. Silk Screen Layer (NOT TO SCALE) 30 DS62DB2
· Notes ·
Smart Analog is a Trademark of Crystal Semiconductor Corporation