18-Bit, Stereo Converter Digital Audio Features General Descripti
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CS4328
18-Bit, Stereo Converter Digital Audio
Features General Description
CS4328 complete stereo digital-to-analog output system. addition traditional function, CS4328 includes digital interpolation filter followed oversampled delta-sigma modulator. modulator output controls reference voltage input ultra-linear analog low-pass filter. This architecture allows infinite adjustment sample rate between while maintaining linear phase response simply changing master clock frequency. CS4328 also includes extremely flexible serial port utilizing select pins support four different interface modes. master clock either times input word rate, supporting various audio environments.
Rates Adjustable System Sampling 48kHz including 32kHz, 44.1kHz
Complete Stereo System Interpolation Filter Delta-Sigma Analog Post Filter
Signal-to-Noise Ratio Clock Jitter Sensitivity Completely Filtered Line-Level Outputs Linear Phase Filtering
Interface Flexible Serial Data Either Input Zero Phase Error Between Channels External Components Needed
ORDERING INFORMATION: CS4328-KP 28-pin Plastic CS4328-KS 28-pin Plastic CS4328-BP 28-pin Plastic CS4328-BS 28-pin Plastic CDB4328 CS4328 Evaluation Board
SOIC SOIC
DIF0 LRCK BICK SDATAI
DIF1
DGND
AGND1
-VREF
Serial Input Interface Interpolator Delta-Sigma Delta-Sigma Modulator Modulator
Voltage Reference
Interpolator Interpolator Calibration Microcontroller CALO CMPI Delta-Sigma Delta-Sigma Modulator Modulator Clock Osc/ Divider ACKI
Analog Low-Pass Filter
MOSFET Output Stage
AOUTL
Analog Low-Pass Filter
MOSFET Output Stage
AOUTR AGND2 AGND3
CALI
CMPO
ACKO
Crystal Semiconductor Corporation P.O. 17847, Austin, 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com
Copyright Crystal Semiconductor Corporation 1993 (All Rights Reserved)
DS62F3
CS4328
ANALOG CHARACTERISTICS
25°C grade, grade; VA+,VD+ -5V; Logic VD+; Logic DGND; Full-Scale Output Sinewave, Input Word Rate kHz; Input Data Bits; BICK 3.072 MHz; 10k; Measurement Bandwidth kHz, unweighted; unless otherwise specified.)
Parameter* Symbol Specified Temperature Range Resolution CS4328-K CS4328-B Units Bits
Dynamic Performance
Signal-to-Noise Ratio (A-weighted) (Note -0.05 26.4 -100 +0.1 33/IWR -110 23.5 21.6 +0.2 0.00025 -0.05 26.4 +0.1 33/IWR -105 23.5 21.6 +0.2 0.00025
Total Harmonic Distortion Noise (A-Weighted) THD+N Output, Output, Output, Deviation From Linear Phase Passband: corner 0.00025 corner (Note (Notes (Notes
Frequency Response (Note Passband Ripple StopBand StopBand Attenuation Group Delay (IWR Input Word Rate) Interchannel Isolation kHz) (Note (Note (Note
Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift Offset Error (after calibration) ppm/°C
Analog Output
Full Scale Output Voltage VOUT
Power Supplies
Power Supply Current: VAVD+ IAID+ kHz) PSRR
Power Dissipation Power Supply Rejection Ratio
Notes: Idle channel, digital input zeros. Combined digital analog filter characteristics. passband stopband edges scale with frequency. input word rates, IWR, other than kHz, 0.00025 passband edge stopband edge Digital filter characteristics. Definitions this data sheet. Specifications subject change without notice. DS62F3
CS4328
DIGITAL CHARACTERISTICS
,VD+
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage -20µA Low-Level Output Voltage 20µA Input Leakage Current (Note Symbol 70%VD+ 30%VD+ Units
Note: TST, DIF0 DIF1 have internal pull-down devices, nominally 90k.
ABSOLUTE MAXIMUM RATINGS (AGND1-3, DGND voltages with respect ground.)
Parameter Power Supplies: Positive Digital Positive Analog Negative Analog |VA+ VD+| Input Current, Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature VIND Tstg Symbol VAMin -0.3 -0.3 -0.3 -6.0 Units
(VD+)+0.4
WARNING: Operation beyond these limits result permanent damage device Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND1, AGND2, AGND3, DGND voltages with respect ground)
Parameter Power Supplies: Positive Digital Positive Analog Negative Analog |VA+ VD+| Symbol VAMin 4.75 4.75 -4.75 -5.0 5.25 5.25 -5.25 Units
DS62F3
CS4328
SWITCHING CHARACTERISTICS
VA+, Inputs: Logic Logic VD+,
Parameter Master Clock Frequency using Internal Oscillator: CKS=H CKS=L Master Clock Frequency using External Clock: CKS=H CKS=L XTI/XTO Pulse Width XTI/XTO Pulse Width High BICK Pulse Width BICK Pulse Width High BICK Period BICK rising LRCK edge delay BICK rising LRCK edge setup time SDATAI valid BICK rising setup time BICK rising SDATAI hold time Minimum Pulse Width (Note (Note (Note (Note XTI/XTO tbickl tbickh tbickw tblrd tblrs tsbs tbsh 0.384 0.256 19.2 13.9 XTI/XTO 10.7 19.2 13.9 Symbol Units
periods XTI/XTO
Note:
"BICK rising" refers modes mode replace "BICK rising" with "BICK falling."
LRCK blrs blrd BICK SDATAI bickl bickh
LRCK blrs blrd BICK SDATAI MSB-1 bickl bickh
Serial Input Timing (Modes
Serial Input Timing (Mode
DS62F3
CS4328
Digital Audio Data Processor LRCK BICK SDATAI VREFNC AOUTL External Clock Mode Select AOUTR ACKO ACKI CMPO DIF0 DIF1 DGND AGND3 AGND2 AGND1 CALO CALI CMPI CS4328 CONVERTER
Analog Analog
optional crystal oscillator 74HC device
Power Cal. Control
Figure Typical Connection Diagram
DS62F3
CS4328 GENERAL DESCRIPTION CS4328 complete stereo digital-to-analog system designed digital audio. system accepts data standard audio frequencies, such kHz, 44.1 kHz, kHz; produces line-level outputs. architecture includes oversampling filter followed oversampled one-bit delta-sigma modulator. output from modulator controls polarity reference voltage which then passed through ultralinear analog low-pass filter. result line-level outputs with need further filtering.
LRCK (kHz) 44.1 44.1 high high high XTI/XTO (MHz) 8.192 12.288 11.2896 16.9344 12.288 18.432 ACKO (MHz) 4.096 4.096 5.6448 5.6448 6.144 6.144
Table Common Clock Frequencies
SYSTEM DESIGN Very external components required support DAC. Normal power supply decoupling components voltage reference bypass capacitors that's required. System Clock Input master clock (XTI/XTO) input used operate digital interpolation filter delta-sigma modulator. master clock either crystal placed across pins, external clock input with left floating. frequency XTI/XTO determined desired Input Word Rate, IWR, setting Clock Select pin, CKS. frequency which words each channel input equal LRCK frequency. Setting selects XTI/XTO frequency while setting high selects IWR. ACKO will always used analog low-pass smoothing filter. Table illustrates various audio word rates corresponding frequencies used DAC.
remaining system clocks, LRCK BICK, must synchronously derived from XTI/XTO. CS4328 internal oscillator used, circuit must configured buffered shown Figure XTI/XTO divided produce LRCK BICK using synchronous counter such 74HC590. Notice that value capacitor capacitor which allows gate stray capacitance. also possible divide ACKO, IWR, derive BICK LRCK. However, external circuitry must used apply "kick-start" pulse LRCK order activate ACKO. sequence cancellation RESET, beginning calibration activation ACKO shown Figure with required transitions indicated arrows. momentary loss XTI/XTO power will require "kick-start" pulse resume operation. Serial Data Interface Data input CS4328 three serial input pins; SDATAI serial data input, BICK serial data clock LRCK defines channel delineation data. supports four serial data formats which selected digital input format pins DIF0 DIF1. different formats control relationship LRCK SDATAI edge BICK used
DS62F3
CS4328
LRCK "Kickstart" XTI/XTO ACK0
minimum
minimum
Reset Status
Exit Reset
Figure RESET Cancellation Timing
latch data. Table lists four formats, along with associated figure number. Format compatible with existing 16-bit converters digital filters. Format 18-bit version format Format similar Crystal ADCs many serial ports. Format compatible with serial data protocol. Formats support 18-bit input 16-bit followed zeros. four serial input modes, serial data MSB-first 2's-complement format. Formats will operate with 16-bit data BICK pulses well. Figure 16-bit timing. However, BICK recommended minimize possibility performance degradation resulting from BICK coupling into VREF-.
Reset Offset Calibration active signal that resets digital filter delta-sigma modulator, synchronizes LRCK with internal control signals starts offset calibration cycle upon exiting reset. When goes low, CALO goes high stays high until offset calibration cycle. offset calibration cycle takes 1024 cycles complete. CALO must connected CALI CMPO must connected CMPI offset calibration. During offset calibration analog output forced zero. Power-Up Considerations Upon initial application power DAC, offset calibration digital filter registers will indeterminate. should during power-up activate internal mute prevent this erroneous information from being output from DAC. Bringing high will begin calibration cycle initialize these registers. Muting There types mutes that implemented with CS4328. first
DIF1
DIF0
Mode
Figure
Table Digital Input Formats
DS62F3
CS4328
LRCK BICK SDATAI Mode SDATAI Mode
Left Channel
Right Channel
Figure Digital Input Formats
LRCK BICK SDATAI SDATAI
Left Channel
Right Channel
Figure Digital Input Format
LRCK BICK SDATAI SDATAI
Left Channel
Right Channel
Figure Digital Input Format
LRCK
Left Channel
Right Channel
BICK SDATAI Mode BICK SDATAI Mode
SDATAI
Mode
LRCK must inverted.
Figure Digital Input Formats with BICK Periods
DS62F3
CS4328 clean volt supply. VD+, which powers digital interpolation filter delta-sigma modulator, powered from system volt logic supply. Decoupling capacitors should located near CS4328 possible. printed circuit board layout should have separate analog digital regions with individual ground planes. CS4328 should straddle ground plane break shown CDB4328 Evaluation board. Optional jumpers connecting these planes should included near DAC, where power brought board near regulators. signals, especially clocks, should kept away from VREF- avoid unwanted coupling into CS4328. VREF- decoupling capacitors, particularly must positioned minimize electrical path from VREF- AGND minimize path between VREF- capacitors. Extensive ground plane fill both analog digital sections circuit board will yield large reductions radiated noise effects. application note "Layout Design Rules Data Converters" printed Application Note section this book. Analog Output Filtering Full scale analog output each channel typically peak-to-peak. analog outputs drive load impedances short-circuit protected 20mA. CS4328 analog filter order switched-capacitor filter followed secondorder continuous-time filter. switched-capacitor filter clock dependent will scale with frequency. continuous-time filter fixed related IWR. low-pass filter consisting resistor capacitor recommended analog outputs.
CS4328 CALO CALI
MUTE
Figure -50dB Muting
mute which activated forcing CALI high. Figure shows implement mute using gate. propagation gate will only delay moving CS4328 muted state.
MUTE DATA
CS4328 SDATAI
Figure -120 Muting
second mute option stage operation which involves forcing SDATAI using gate shown Figure first mute occurs following LRCK cycles when input data propagates output DAC. noise present output will typically below fullscale. Following total 4096 LRCK cycles with input data output CS4328 will mute lower output noise minimum below fullscale. Upon release MUTE command non-zero input data CS4328 output mute will immediately release. However, LRCK cycles required input data propagate output CS4328. Grounding Power Supply Decoupling with high resolution converter, CS4328 requires careful attention power supply grounding arrangements optimize performance. Figure shows recommended power arrangements with connected clean volt supply connected
DS62F3
CS4328 Performance Plots following collection CS4328 measurement plots (IWR kHz) were taken with Audio Precision Dual Domain System One. plots 16,384 point. Figure shows frequency response with input word rate. response very flat half input word rate. Figure shows muted noise with zeros data into CS4328. This plot dominated noise floor System One. Figure shows unmuted noise. This data taken feeding CS4328 continuous zeros, pulling CALI low. This unmutes output stage CS4328. This plot shows noise shaping characteristics delta-sigma modulator combined with analog filter. Figure shows A-weighted THD+N signal amplitude dithered 1kHz input signal. Notice that there increase distortion signal level decreases. This indicates very good low-level linearity, benefits delta-sigma technique. Figure shows fade-to-noise linearity test result using track CD-1. input test signal dithered sine wave which gradually fades from level -120 During fading, output level from CS4328 measured compared ideal level. Notice very close tracking output level ideal, even level inputs gradual shift plot away from zero signal levels -100 caused background noise starting dominate measurement. Figure shows impulse response, taken from single positive full scale value track CD-1 test disk. Notice high degree symmetry, indicating good phase linearity.
DS62F3
Figure shows plot result, with dithered input. Notice complete lack distortion components tones. Figure shows bandlimited, kHz, time domain plot CS4328 output with kHz, dithered input. Notice clear residual sine wave shape, presence noise. Figure shows monotonicity test result plot. input data CS4328 LSB, four times, then LSB, four times until LSB, LSB. This data pattern taken from track CD-1 test disk. Notice increasing staircase envelope, with decreasing elements. Notice also clear resolution LSB. this test, 16-bit LSB. following tests were done filtering analog output CS4328 with System analyzer notch filter reduce peak signal level. resulting signal then amplified applied module, avoiding distortion System converter. Figure shows Plot with kHz, input. Notice order harmonic distortion -100 Figure shows Plot with kHz, input. Notice almost complete absence distortion, with small residual harmonic -110
CS4328
CRYSTAL -0.5 -1.0 -1.5 -2.0 -100 -100 FRQRSP48 AMPL(dBr) GENFRQ(Hz) CRYSTAL THDAM18A THD+N(dBr) GENAMP(dBFS)
Figure Frequency Response word rate)
CRYSTAL NOISE AMP1(dBr) AMP1(dBr) FREQ(kHz)
Figure THD+N 18-bit Input Signal Level
CRYSTAL TR20R BANDPASS(dBr) LEVEL(dBr)
-100 -120
-140 -160 0.02
9.82 19.6 29.4 39.2 49.0 58.8 68.6 78.4 88.2 98.0 -120 -110 -100
Figure Muted Idle Channel Noise
CRYSTAL NOISEUNM 1.583 -100 0.333 -120 -140 -160 0.02 9.82 -0.083 1.167 AMP1(dBr) FREQ(kHz) CRYSTAL 2.000
Figure Fade-to-Noise Linearity
IMPULSE AMP1(V) TIME(usec)
0.750
19.6
29.4
39.2
49.0
58.8
68.6
78.4
88.2
98.0
-0.500
95.8
Figure Unmuted Idle Noise DS62F3
Figure Impulse Response
CS4328
CRYSTAL M90DB1K -100 -120 -640 -140 -800 AMP1(dBr) FREQ(kHz) CRYSTAL -160 -320 -480 MONOTON AMP1(uV) TIME(msec)
Figure kHz, Input Plot
CRYSTAL -100 -150 -200 -250 0.50 1.00 1.50 2.00 2.50 3.00 -120 -140 -100 M90TIME AMP1(uV) TIME(msec)
Figure Monotonicity Test (16-bit data)
CRYSTAL 0dBFFT AMP1(dBr) FREQ(Hz)
Figure kHz, Input Time Domain Plot
CRYSTAL -100 -120 -140 1KM10DB
Figure kHz, Input Plot
AMP1(dBr) FREQ(Hz)
Figure kHz, Input Plot DS62F3
CS4328
Audio Data
Interpolator
Digital
Delta Sigma Modulator
Switched Continuous Time Filter Analog Filter
Analog Output
Figure CS4328 Architecture
THEORY OPERATION CS4328 architecture considered five blocks: Interpolation, sample/hold, deltasigma modulation, conversion, analog filtering. Audio data input CS4328 digital interpolation filter which removes images input signal that present multiples input sample frequency, (Figure 21). Following interpolation stage, resulting frequency spectrum images input signal multiples eight times input sample frequency, (Figure 22). Eliminating images between greatly relaxes requirements analog filtering, allowing suppression images while leaving audio band interest unaltered.
(dB)
tiples. sinx/x zeros completely attenuate signals largely suppress remaining energy images (Figure 23). interpolation followed sample-and(dB)
16Fs
(kHz)
Figure Spectrum After
hold results data rate delta-sigma modulator takes data (3.072 48kHz sampled systems) performs fifth-order noise shaping. digital modulator CS4328, 18-bit audio data modulated 1-bit, signal. 5th-order noise shaper allows 1-bit quantization support 18-bit audio processing suppressing quantization noise bandwidth
(kHz)
Figure Input Data Spectrum
(dB)
(dB)
Figure Modulator Output Spectrum 16Fs (kHz)
f(kHz)
Figure Interpolated Data Spectrum
interest. Figure shows frequency spectrum modulator output. CS4328 interpolation stage followed sample-and-hold function where data points from interpolator held eight clock cycles. resulting frequency response sinx/x characteristic with zeros mulDS62F3
CS4328's digital modulator followed D-to-A converter that translates 1-bit signal into series charge packets. magnitude charge each packet determined sampling voltage reference onto switched
CS4328 capacitor, where polarity each packet controlled 1-bit signal. result 1-bit conversion process that very insensitive clock jitter. This major improvement over previous generations 1-Bit converters where magnitude charge process determined switching current reference period time defined periods master clock. final stage CS4328 made order switched-capacitor pass filter order continuous time filter. switchedcapacitor filter eliminates out-of-band energy resu lting from oise shaping process (Figure 25). switched-capacitor stage scales with master clock signal being applied CS4328. final stage order continuous time filter that eliminates high frequency energy that appears multiples sample rate (Figure 26).
Figures 27-30 computer simulations combined response CS4328 digital analog filters with input word rate kHz. Figure shows individual combined phase response CS4328 filters. Notice digital filter equalization analog filter produce linear phase response. Figures 28-30 plots CS4328 magnitude response.
Phase (degrees)
(dB)
64Fs
(kHz)
Analog Filter
Digital Filter Total Phase
Figure Spectrum After Switched-Capacitor Filter
(dB)
(kHz)
Frequency (kHz)
Figure Spectrum After Continuous Time Filter Figure Deviation From Linear Phase
DS62F3
CS4328
-100 -110 -120 -130 Input Frequency (kHz)
Magnitude (dB)
Figure Combined Digital Analog Filter Frequency Response
Magnitude (dB) Input Frequency (kHz)
Figure Combined Digital Analog Filter Frequency Response
Magnitude (dB) -100 -110 Input Frequency (kHz)
Figure Combined Digital Analog Filter Transition Band DS62F3
CS4328 DESCRIPTIONS
ANALOG GROUND ANALOG LEFT CHANNEL OUTPUT ANALOG POWER ANALOG GROUND NEGATIVE ANALOG POWER COMPARATOR OUTPUT CONNECT COMPARATOR INPUT RESET TEST CLOCK SELECT DIGITAL INPUT FORMAT DIGITAL INPUT FORMAT CRYSTAL CLOCK INPUT AGND1 AOUTL AGND2 VACMPO CMPI DIF1 DIF0
VREF- VOLTAGE REFERENCE OUTPUT CALI CALIBRATION INPUT AOUTR ANALOG RIGHT CHANNEL OUTPUT AGND3 ANALOG GROUND ACKI ANALOG CLOCK INPUT CONNECT ACKO ANALOG CLOCK OUTPUT CALO CALIBRATION OUTPUT LRCK LEFT/RIGHT CLOCK INPUT BICK SERIAL CLOCK INPUT SDATAI SERIAL DATA INPUT DGND DIGITAL GROUND DIGITAL POWER CRYSTAL OSCILLATOR OUTPUT
Power Supply Connections Positive Analog Power, Positive analog supply. Nominally volts. Negative Analog Power, Negative analog supply. Nominally volts. AGND1, AGND2, AGND3 Analog Grounds, PINS Analog ground reference. Positive Digital Power, Positive supply digital section. Nominally volts. DGND Digital Ground, Digital ground digital section. Analog Outputs VREF- Voltage Reference Output, Nominally -3.68 volts. Normally connected 0.1µF ceramic capacitor parallel with 10µF larger electrolytic capacitor. Note negative output polarity. AOUTL Analog Left Channel Output, Analog output left channel. Typically peak-to-peak full-scale input signal. AOUTR Analog Right Channel Output, Analog output right channel. Typically peak-to-peak full-scale input signal.
DS62F3
CS4328 Digital Inputs Crystal Clock Input, crystal oscillator connected between this XTO, external CMOS clock input XTI. frequency must either input word rate based clock select pin, CKS. ACKI Analog Clock Input, This master clock input analog section chip must input word rate. ACKI typically connected Analog Clock Ouput pin, ACKO. CALI Calibration Input, Input analog section that used during offset calibration. Normally connected Calibration Output pin, CALO. CMPI Comparator Input, Input digital section that used during offset calibration. Normally connected Comparator Output pin, CMPO. LRCK Left/Right Clock, This input determines which channel currently being input Serial Data Input pin, SDATAI. format LRCK controlled DIF0 DIF1. BICK Serial Input Clock, PIN19. Clocks individual bits serial data from SDATAI pin. edge used latch SDATAI controlled DIF0 DIF1. SDATAI Serial Data Input, Two's complement MSB-first serial data either bits input this pin. data clocked into CS4328 BICK clock channel determined LRCK clock. format previous clocks determined Digital Input Format pins, DIF0 DIF1 DIF0,DIF1 Digital Input Format, PINS These pins select four formats incoming serial data stream. These pins format BICK LRCK clocks with respect SDATAI. formats listed Table Clock Speed Select, Selects clock frequency input pin. selects input word rate (LRCK frequency) while high selects Reset Calibrate, When reset filters modulators held reset. When reset goes high, offset calibration initiated.
DS62F3
CS4328 Digital Outputs Crystal Oscillator Output, When crystal oscillator used, tied between this XTI. When external clock input, this should left floating. ACKO Analog Clock Output, This output input word rate (LRCK frequency). Normally connected Analog Clock Input pin, ACKI. CALO Calibration Output, Used during offset calibration. Must connected Calibration Input pin, CALI. CMPO Comparator Output, Used during offset calibration. Must connected Comparator Input pin, CMPI. Miscellaneous Connection, PINS These pins bonded test outputs. They must connected external component length trace. -Test Input, Allows access CS4328 test modes, which reserved factory use. Must tied DGND.
DS62F3
CS4328 PARAMETER DEFINITIONS Total Harmonic Distortion Noise ratio value signal other spectral components over specified bandwidth (typically kHz), including distortion components. Expressed decibels. Signal-to-Noise Ratio ratio full scale value signal other spectral components over specified bandwidth with input zeros. Frequency Response measure amplitude response variation from relative amplitude response kHz. Units decibels. Interchannel Isolation measure crosstalk between left right channels. Measured each channel converter's output with zeros input under test full-scale signal applied other channel. Units decibels. Interchannel Gain Mismatch gain difference between left right channels. Units decibels. Gain Error deviation from nominal full scale analog output full scale digital input. Gain Drift change gain value with temperature. Units ppm/°C. Offset Error deviation mid-scale transition (111.111 000.000) from ideal (AGND). Units
DS62F3
Plastic
SEATING PLANE
NOTES: POSITIONAL TOLERANCE LEADS SHALL WITHIN 0.25mm (0.010") MAXIMUM MATERIAL CONDITION, RELATION SEATING PLANE EACH OTHER. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH.
MILLIMETERS INCHES 3.94 4.32 5.08 0.155 0.170 0.200 0.51 0.76 1.02 0.020 0.030 0.040 0.36 0.46 0.56 0.014 0.018 0.022 1.02 1.27 1.65 0.040 0.050 0.065 0.20 0.25 0.38 0.008 0.010 0.015 36.45 36.83 37.21 1.435 1.450 1.465 13.72 13.97 14.22 0.540 0.550 0.560 2.41 2.54 2.67 0.095 0.100 0.105 15.24 15.87 0.600 0.625 3.18 0.150 3.81 0.125
pins
MILLIMETERS 9.91 10.16 10.41 12.45 12.70 12.95 14.99 15.24 15.50 17.53 17.78 18.03 MILLIMETERS
INCHES 0.390 0.400 0.410 0.490 0.500 0.510 0.590 0.600 0.610
0.690 0.700 0.710
INCHES
SOIC
2.41 0.127 2.29
2.54 2.67 0.095 0.100 0.105 0.300 0.005 0.012 2.41 2.54 0.090 0.095 0.100
0.33 0.46 0.51 0.013 0.018 0.020 0.203 0.280 0.381 0.008 0.011 0.015 table above
10.11 10.41 10.67 0.398 0.410 0.420 7.42 7.49 7.57 0.292 0.295 0.298
1.14 0.41
1.27
1.40 0.040 0.050 0.055 0.89 0.016 0.035
CDB4328
CS4328 Evaluation Board
Features General Description
CDB4328 evaluation board allows fast evaluation CS4328 18-bit, stereo converter. board provides analog output interface connectors both channels. Evaluation requires analog signal analyzer, digital signal source, power supply. Also included CS8412 digital audio receiver I.C., which will accept AES/EBU, S/PDIF, EIAJ-340 compatible audio data. CS8412 provide system timing necessary operate CS4328. evaluation board also configured accept external timing signals operation user application during system development.
Demonstrates recommended layout grounding arrangements
CS4328 Supports multiple input formats CS8412 Receives AES/EBU, S/PDIF,
EIAJ-340 Compatible Digital Audio
Digital Analog Patch Areas Operation with on-board CS8412
externally supplied system timing
ORDERING INFORMATION: CDB4328
Block Diagram
Digital Audio Input Digital Patch Area -15V +15V Analog Patch Area
CS8412 Digital Audio Receiver
Power Supply Regulation Conditioning
Error Info/ Channel Status
Timing Signal Selector
CS4328 Converter
AOUTR AOUTL
Offset Calibration Network SCLK SDATA MCLK
Crystal Semiconductor Corporation P.O. 17847, Austin, 78760 (512) 7222 Fax: (512) 7581 http://www.crystal.com
DS62DB2
CDB4328 Power Supply Circuitry Figure shows evaluation board power supply circuitry. Power supplied evaluation board five binding posts. analog power supply inputs converter derived from using voltage regulators digital supply converter discrete logic board provided DGND binding posts. transient suppressors which also provide protection from incorrectly connected power supply leads. C1-C8 provide general power supply filtering analog supplies. shown Figure C20-C24 provide localized decoupling converter VApins. Note that connected between VAand AGND. evaluation board uses both analog digital ground plane which connected This ground plane arrangement isolates board's digital logic from analog circuitry. Offset Calibration Reset Circuitry Figure shows offset calibration circuit provided evaluation board. Upon power-up, this circuit provides pulse Digital Analog Converter's initiating offset calibration cycle. Pressing releasing also initiates offset calibration cycle. Serial Data Interface Figure shows that there options inputing serial data into CS4328. Serial data provided SDATA connector evaluation board. connectors SCLK, serial data input clock, L/R, clock that defines channel delineates data, also provided evaluation board. This information also provided onboard CS8412. selects source SDATA, SCLK, that will provided converter. selections shown Table
0.47
+15V AGND -15V
78L05 0.22
0.47 79L05
AGND
DGND
0.22
1N6276A 1.5KE P6KE-6V8P from Thomson DGND 0.1uF 1N148
CS4328
74HC14
Figure Power Supply Reset Circuitry DS62DB2
CDB4328
Analog,
ACKO
ACKI AGND1 VAAGND2 AGND3
LRCK BICK SDATAI
Analog,
CS4328
SCLK SDATA MCLK
CMPO CMPI CALO CALI AOUTL
AOUTL
AOUTR
AOUTR
From Reset Circuit
DGND DIFO
VREF DIFI
Figure CS4328 Connections
CS4328 supports four serial data input formats. selection which made digital input format pins DIF0 DIF1. different formats control relationship SDATA edge SCLK used latch data. Consult CS4328 data sheet explanation different formats.
Position 8412 Input Option Selected SDATA,SCLK, provided external source. SDATA,SCLK, provided CS8412
System Timing master clock input CS4328 provided several sources. selects source master clock that supplied converter. When selected, master clock provided sources. 12.288 clock signal provided used master clock both CS4328 external system that provides serial data board. other option master clock that synchronized external serial data coming into board, used master clock CS4328 well. However, external
Table Selectable Options DS62DB2
CDB4328 master clock used, must removed from it's socket prevent clock signals from interfering with another. When 8412 selected JP3, master clock CS4328 provided output CS8412. CS4328 pulled either high JP2. This determines whether master clock frequency 384X 256X input word rate. Consult CS4328 data sheet common master clock frequencies table. Analog Outputs analog outputs available connectors labeled AOUTL AOUTR. remove remaining very high frequency components from left channel output signal while right channel output signal. Digital Audio Standard Interface Included evaluation board CS8412 Digital Audio Interface Receiver. This device receive decode data according AES/EBU, S/PDIF, EIAJ-340 interface standard. Figure shows schematic CS8412. input coupled device through transformer that included board. input device configured accept either professional consumer input modes. Consult CS8412 data sheet explanation input modes. LEDs, D4-D8, perform functions. When Channel Status position, LEDs display channel status information channel selected JP1. When Error Information position, LEDs D4-D6, display encoded error information that decoded consulting CS8412 data sheet. Encoded sample frequency information displayed LEDs D7-D9 provided proper clock being applied JP1. When lit, this indicates corre24
sponding located CS8412. When off, this indicates corresponding pin. Neither option should selected being driven clock signal. Serial Output Interface SDATA, SCLK, L/R, MCLK connectors also used provide serial output interface CS8412. With 8412 position, outputs from CS8412 brought board external evalution system. This data configured seven selectable formats. These formats outlined CS8412 data sheet. CDB5336/7/8/9 Interface CDB4328 Many users find informative evaluate combined system connected together yielding analog input analog output. This accomplished interconnecting CDB5326/7/8/9 CDB5336/7/8/9 CDB4328 evaluation board. following information contains several techniques accomplish this goal. There general points which need mentioned. analog input 3.68 will produce full scale digital output from CS5336/7/8/9 CS5326/7/8/9. full scale digital input CS4328 will produce full scale output resulting overall loss approximately from input output. Also recommended that power connections each board brought directly from power supply "daisy-chain" manner from board board. Connecting CDB4328 CDB5336/7/8/9 accomplished using methods:
DS62DB2
DS62DB2
8412
Error Information
Channel Status
12.288
Ca/E1 Ce/F2 74HC126 Cc/F0 CS8412 Cd/F1 SDATA Cb/E2
74HC04
VERF FSYNC C0/E0
Schott 67125450 Pulse PE65612 Digital Input CSLR/FCK
Analog 0.047 FILT DGND AGND
CDB4328
D,E,F
Figure CS8412 Digital Audio Receiver Connections
CDB4328 trace SDATA connector place jumper between SDATA CMODE master clock times sample rate. must have both internal external jumpers installed. This will route master clock EXTCLKIN ection CDB4328 MCLK. CS5336/8 installed additional modification required invert SCLK prior transmission CDB4328. This implemented follows: trace SCLK install jumper between SCLK BNC. CDB5336/7/8/9 CDB4328 Interconnection Method Shielded coaxial cables with connectors should used make following connections: L/R, SCLK SCLK, SDATA SDATA, EXTCKIN MCLK. CDB4328 Interfacing CDB5326/7/8/9 method interfacing CDB5326/7/8/9 CDB4328 requires direct interface through EXTCLKIN, SCLK, SDATA, connectors. This technique requires modifications CDB5326/7/8/9 derive proper clock frequencies. This done utilizing 12.288 clock supplying clock CDB5326/7/8/9 6.144 MHz. CDB4328 Configuration CS4328 must receive data format (DIF1 high DIF0 low). Modify jumpers located near pins CS4328. sets clock sample frequency ratio (CKS) CS4328 ratio. selects source SDATA, SCLK that will provided converter should
DS62DB2
removed access multiple clocks from CDB5326/7/8/9. Remove 12.288 oscillator (U8). CDB5326/7/8/9 Configuration Remove clock source jumper (P2). Remove 6.144 oscillator (U2) replace with 12.288 oscillator from CDB4328. Install divide function CDB5326/7/8/9 digital patch area. 74HC74 with input connected output. Connect oscillator output 74HC74 clock input. Connect output Position connect oscillator output EXTCLKIN. CDB5326/7/8/9 CDB4328 Interconnection Shielded coaxial cables with connectors should used make following connections: L/R, SCLK SCLK, SDATA SDATA, EXTCLKIN MCLK.
CDB4328
Figure Ground Plane Layer (NOT SCALE) DS62DB2
CDB4328
Figure Bottom Trace Layer (NOT SCALE) DS62DB2
CDB4328
Figure Silk Screen Layer (NOT SCALE) DS62DB2
Notes
Smart Analogis Trademark Crystal Semiconductor Corporation
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