DIGITAL VIDEO ENCODER VIDEOCD GENERAL DESCRIPTION SPCA701A design
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SPCA701A
DIGITAL VIDEO ENCODER VIDEOCD
GENERAL DESCRIPTION SPCA701A designed specifically VideoCD, video games other digital video systems, which require conversion digital YCrCb (MPEG) data analog NTSC/PAL video. device supports glue-less interface most popular MPEG decoders. SPCA701A supports worldwide video standards, including NTSC America, Japan) PAL-B, (Europe, Asia). Furthermore, SPCA701A operates with single clock powered with single 3.3V supply. composite analog video signal output simultaneously onto outputs. Therefore, allows output provide base-band composite video while other drives modulator. Alternatively, analog luminance chrominance information available interfacing S-video equipment. slave, SPCA701A automatically detects input data formats (PAL/NTSC, CCIR601) switches internally provide proper format outputs. This feature, along with on-board voltage reference single clock interface, makes SPCA701A extremely simple use. addition, over-sampling on-chip simplifies external filter design resulting reduced overall system cost.
FEATURES 8-bit 4:2:2 YCrCb inputs glue-less interface
BLOCK DIAGRAM
VBIAS VREFOUT FSADJUST
MPEG decoders NTSC/PAL composite video outputs (North
Internal VREF COMP
American NTSC Western European PAL) CVBS S-video outputs
P[7:0]
VRDAC
Upsample Latch 1.3MHz VSYNC* Mod. Mixer CVBS/C CVBS/Y
supply voltage tolerant digital data pins CCIR operation over sampling simplifies external filtering 9-bit DACs
MODE[3:0] MASTER HSYNC*
CBSWAP
SVIDEO
SLEEP
Master slave video timing Interlaced operation Automatic mode detection/switching slave mode On-board voltage reference 32-pin PLCC package APPLICATIONS VideoCD Karaoke/video games Digital Video Disk (DVD) Digital Digital
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
DESCRIPTION (Table Mnemonic DATA[7:0] 21-28 Type Description YCrCb pixel inputs. They latched rising edge CLK. YCrCb input data conform CCIR 601. VSYNC Pixel clock input. Vertical sync input/output. VSYNC latched/output following rising edge CLK. HSYNC Horizontal sync input/output. HSYNC latched/output following rising edge CLK. MASTER Master/slave mode selection. logical high master mode operation. logical slave mode operation CBSWAP pixel sequence configuration pin. logic high swap sequence. SVIDEO SVIDEO select input pin. logic high selects output. logic selects composite video output. SLEEP Power save mode. logic high this puts chip into powerdown mode. Mode[3:2] Mode[1:0] TEST VREFIN 17-18 19-20 Mode configuration pin. Useless pins. will better connect them DGND. Test pin. These pins must connected DGND. Voltage reference input. external voltage reference must supply typical 1.235V this pin. ceramic capacitor must used de-couple this input GND. decoupling capacitor must closed possible minimize length load. This connected directly VREFOUT. VREFOUT Voltage reference output. generates typical 1.2V voltage reference used drive VREFIN directly. FSADJ Full-Scale adjust control pin. Full-Scale current converters adjusted connecting resistor (RSET) between this ground. COMP Compensation pin. ceramic capacitor must used bypass this VAA. lead length must kept short possible avoid noise. CVBSY Composite/Luminance output. This high-impedance current source output. output format selected pin. CVBSY drive 37.5 Sunplus Technology Co., Ltd. load. unused, this must connected Rev.: 1999.12.07
SPCA701A
Mnemonic Type directly GND. CVBSC Composite/Chroma output. This high impedance current source Output. output format selected pin. drive 37.5 GND. VBIAS DGND AGND 3,12 bias voltage. Potential normally 0.7V less than COMP. Digital power Digital ground Analog power Analog ground load. unused, this must connected directly Description
MODE SELECTION Master mode selected when MASTER slave mode selected when MASTER pins, MODE [3:2], drive three different configuration registers. most common operating modes selected with these pins while master mode. slave mode, common operating modes automatically determined from timing incoming HSYNC* VSYNC* signals.
NOTE: term "common operating mode" refers North American NTSC Western European Table illustrates multi-functionality mode pins during master slave mode. access more exotic video formats, slave mode preferred since necessary registers always accessible.
master mode needed, less common modes still programmed first registering modes slave, then switching master. During power-up, MODE [3:2] pins configure master registers; i.e., EFIELD, PAL625, written. Also, during power-up, slave registers reset zero, i.e., YCSWAP.
Table Mode Selection Description MASTER MODE[3] YCSWAP EFIELD MODE[2] -PAL625 MODE[1] -MODE[0]
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
Table Configuration Register Settings Mode Register Name EFIELD VSYNC will output normal vertical synchronization signal. PAL625 525-line operation will select YCSWAP swap Cr/Cb VSYNC will output field signal. VSYNC even field, high field 625-line operation will select Swap Cr/Cb sequence This only used master mode -Comments This only used master mode.
CLOCK TIMING clock signal with frequency twice luminance sampling rate must present pin. setup hold timing specifications measured with respect rising edge this signal.
PIXEL INPUT TIMING PIXEL SEQUENCE Multiplexed data input through DATA[7:0] inputs. default, input sequence active video pixels must Cb0, Cr0, Cb2, Cr2, etc., accordance with CCIR-656. This pattern begins during first period after falling edge HSYNC* (regardless setting SLAVE/MASTER mode). order reversed setting CBSWAP pin. Figure illustrates timing. pixel stream input SPCA701A period, SPCA701A lock pixel stream setting YCSWAP register. This would solve problem having Cr/Cb pixels swapped.
Figure Sequence
CBSWAP(1)
CLK(2) HSYNC*(3)
P[7:0]
Cbn+2
P[7:0]
Crn+2
Notes: (1). CBSWAP (2). Pixel transitions must occur observing setup hold timing about rising edge CLK. (3). Pixel sequence will beging with clock periods following falling edge HSYNC*, when integer.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
VIDEO TIMING width analog horizontal sync pulses start color burst automatically calculated inserted each mode according CCIR-624-4. Color burst disabled appropriate scan lines.
Serration equalization pulses generated appropriate scan lines. addition, rise fall times sync, burst envelope internally controlled. Video timing figures follow text this section.
SYNC BURST TIMING Table lists resolutions clock rates various modes operation. Table lists horizontal counter values horizontal sync, start color burst, color burst, front porch, back porch, first active pixel various modes operation. front porch interval before next expected falling HSYNC* when outputs automatically blanked. horizontal sync width measured between points falling rising edges horizontal sync. start color burst measured between point falling edge horizontal sync first point color burst amplitude (nominally NTSC PAL-B, above blanking level). color burst measured between point falling edge horizontal sync last point color burst envelope (nominally NTSC PAL-B, above blanking level).
Table Field Resolutions Clock Rates Various Modes Operation Operating Mode NTSC CCIR601 PAL-B,D,G,H,I Active pixels Total Pixels Frequency (MHz)
Table Horizontal Counter Values Various Video Timings Operation Mode NTSC CCIR601 PAL-B CCIR601 Front porch Horizontal Sync Width Start Burst Duration Burst Back porch
Notes: unit number luminance pixel.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
MASTER MODE Horizontal sync (HSYNC*) vertical sync (VSYNC*) generated from internal timing optional software bits. HSYNC*, VSYNC* output following rising edge CLK. horizontal counter
incremented every other rising edge CLK. After reaching appropriate value (determined mode operation), reset one, indicating start line. vertical counter incremented start each line. After reaching appropriate value, determined mode operation, reset one, indicating start field. VSYNC* asserted scan lines 262/525 line 312/625 line, respectively.
SLAVE MODE Horizontal sync (HSYNC*) vertical sync (VSYNC*) inputs that registered rising edge CLOCK. horizontal counter incremented rising edge CLOCK. clock cycles after falling edge HSYNC*, counter reset one, indicating start line. vertical counter
incremented falling edge HSYNC*. falling edge VSYNC* resets one, indicating start field. falling edge VSYNC* occurring within ±1/4 scan line from falling edge HSYNC* cycle time (line time) indicates beginning Field falling edge VSYNC* occurring within ±1/4 scan line from mid-point line indicates beginning Field
operating mode (NTSC/PAL) programmed with MODE[3:2] bits when SETMODE (MASTER pin) high. Alternatively, when SETMODE low, mode automatically detected slave mode. example, 525-line operation assumed, 625-line operation detected number HSYNC* edges between VSYNC* edges. frequency operation (CCIR-601) both NTSC detected counting number clocks line. pixel rate assumed 13.5 MHz, count which detected between successive falling edges HSYNC*.
BURST BLANKING NTSC, color burst information automatically disabled scan lines 264-272, inclusive. (SMPTE line numbering convention.) PAL-B, color burst information automatically disabled scan lines 1-6, 310-318, 623-625, inclusive, fields During fields color burst information disabled scan lines 1-5, 311-319, 622-625, inclusive.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
VERTICAL BLANKING INTERVALS NTSC, scan lines 263-272, inclusive, always blanked. There setup scan lines 10-21 273-284 inclusive. displayed lines vertical blanking interval (10-21 273-284 interlaced NTSC; 7-13 320-335 interlaced PAL-B, forced blank. PAL-B, scan lines 1-6, 311-318, 624-625, inclusive, during fields always blanked. During fields scan lines 1-5, 311-319, 624-625, inclusive, always blanked.
DIGITAL PROCESSING Once input data converted into internal format, components low-pass filtered with filter. filtered components up-sampled frequency digital filter.
SUBCARRIER GENERATION maintain synchronous sub-carrier relative HSYNC*, sub-carrier phase reset every frame NTSC every fields PAL. phase non-zero depends upon clock frequency video format. perfect clock input, burst frequency 4.43361875 PAL-B, 3.579545 NTSC interlaced.
POWER-DOWN MODE power-down mode (SLEEP internal clock stopped also internal reset forced DACs powered down. When returned high, device starts from reset state (horizontal vertical counters which start VSYNC Field This mode should when SPCA701A subjected clock frequencies outside functional range. Master HSYNC* VSYNC* pins remain driven value previously output before SLEEP activated power down current dependent loading HSYNC* VSYNC* pins.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
Figure Interlaced 525-Line (NTSC) Video Timing
Analog Field
Start YSYNC
Burst Phase Analog Field
Analog Field
Analog Field
Burst Phase
Burst Begins with Positive Half-Cycle Burst Phase Reference Phase Relative Burst Begins with Negative Half-Cycle Burst Phase Reference Phase Relative Note: SMPTE line numbering convention rather than CCIR-624 used.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
Figure Interlaced 625-Line (PAL) Video Timing
Start VSYNC
Analog Field
Phase Analog Field
Analog Field
Analog Field
Field Burst Blanking Intervals Field Field Three Field Four
Burst Phase Reference Phase Relative Switch Component Burst Phase Reference Phase 2250 Relative Switch Component
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
Figure Interlaced 625-Line Video Timing
Start VSYNC
Analog Field
Phase Analog Field
Analog Field
Analog Field
Field Five Burst Blanking Intervals Field Field Seven Field Eight
Burst Phase Reference Phase Relative Switch Component Burst Phase Reference Phase 2250 Relative Switch Component
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
PIXEL INPUT RANGES COLORSPACE CONVERSION INPUTS (4:2:2 YCRCB) nominal range 16-235; have nominal range 16-240, with equal zero. Values interpreted respectively. values 1-15 236-254, CrCb values 1-15 241-254, interpreted valid linear values. NTSC mode with setup disabled less black-to-white range than NTSC mode with setup enabled.
CODING White represented code 400. PAL-B, standard blanking level represented code 120. NTSC, standard blanking level represented code 114, equivalent code 2.857.
OUTPUTS digital-to-analog converters designed drive standard video levels into equivalent 37.5 load.
Unused outputs should connected directly ground minimize supply switching currents. Either composite video outputs S-Video outputs available (selectable SVIDEO pin). SLEEP high, DACs essentially turned only leakage current present.
COMPOSITE LUMINANCE (CVBS/Y)ANALOG OUTPUT When SVIDEO logical zero, digital composite video information drives 9-bit converter that generates CVBS output. When SVIDEO logical one, digital luminance information drives that generates analog video output.
COMPOSITE CHROMINANCE (CVBS/C) ANALOG OUTPUT When SVIDEO logical zero, digital composite video information drives 9-bit converter that generates CVBS output. When SVIDEO logical one, digital chrominance information drives 9-bit converter that generates analog video output.
BOARD CONSIDERATIONS layout should optimized lowest noise power ground planes providing good decoupling. trace length between groups pins should short possible minimize inductive ringing. well-designed power distribution network critical eliminate digital switching noise. ground plane must provide low-impedance return path digital circuits. board with minimum four layers recommended, with layers (top) (bottom) signals layers ground power, respectively.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
COMPONENT PLACEMENT Components should placed close possible associated pin. optimum layout enables SPCA701A located close possible power supply connector video output connector.
POWER GROUND PLANES optimum performance, common digital analog ground plane recommended. Separate digital analog power planes recommended. digital power plane should provide power digital logic board, analog power plane should provide power SPCA701A power pins, VREF circuitry, COMP decoupling. least 1/8-inch required between digital power plane analog power plane. analog power plane should connected digital power plane (VCC) single point through ferrite bead, illustrated Figure Table This bead should located within inches SPCA701A. bead provides resistance switching-currents, acting resistance high frequencies. low-
resistance bead should used, such Ferroxcube 5659065-3B, Fair-Rite 2723021447, BF45-4001.
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
Figure Typical Connection Diagram (Internal Voltage Reference)
Analog Power Plane SPCA701A +3.3V (VCC)
C2,C3
COMP VREFIN VREFOUT
Ground (Power Supply Connector) 2.0K Buffer Audio
FSADJUST CVBS/Y CVBS/C Buffer Buffer Video Connector
Schottky Diodes Filter Schottky Diodes 22pF Regulated
Output
22pF
330pF
330pF
Modulator
270pF
270pF
TRAP
Notes: (1). Some modulators require coupling capacitors (2). Optional chroma boost. (3). VREF must connected either VREF_OUT VBIAS.
Sunplus Technology Co., Ltd.
3.3K
RESET
Rev.:
1999.12.07
SPCA701A
Table Typical Parts List (Internal Voltage Reference) Locations RESET TRAP Description Ceramic Capacitor Capacitor Ferrite Bead Surface Mount Ferrite Bead(z 5MHz) Vendor Part Number Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743021447 LCB0805, Taiyo Yuden BK2125LM182 Dale CMF-55C Murata TPSx.xMJ (where sound carrier frequency MHz) Schottky Diodes BAT85 (BAT54F Dual) 5082-2305 (1N6263) Siemens 64-04 (Dual) Note: Vendor numbers listed only guide. Substitution devices with similar characteristics will affect SPCA701A performance.
Metal Film Resistor Ceramic Resonator
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
PACKAGE INFORMATION
Model Number SPCA701A
Package 32-pin PLCC
Ambient Temperature Range
NOTE: SUNPLUS TECHNOLOGY CO., reserves right make changes time without notice order improve design performance supply best possible product
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
SPCA701A
inches Symbol Min. 0.06 0.013 0.026 0.485 0.447 0.39 0.585 0.547 0.49 Typ. 0.05 Max. 0.14 0.09 0.02 0.03 0.49 0.45 0.43 0.59 0.55 0.53 Min. 2.54 1.52 0.33 0.66 12.3 11.3 9.91 14.8 13.8 12.5
Typ. 1.27 Max. 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.1 13.46
DISCLAIMER information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. SUNPLUS reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. reference purposes only. Please note that application circuits illustrated this document
Sunplus Technology Co., Ltd.
Rev.:
1999.12.07
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