SST49LF004B SST49LF004B4Mb Firmware memory FEATURES: SS

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SST49LF004B SST49LF004B4Mb Firmware memory FEATURES: SS

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Mbit Firmware Flash
SST49LF004B
SST49LF004B4Mb Firmware memory
FEATURES:
SST49LF004B: 512K Mbit) Conforms Intel Interface Specification Supports Single-Byte Memory Firmware Memory Cycle Types Flexible Erase Capability Uniform KByte sectors Uniform KByte overlay blocks Chip-Erase Mode Only Single 3.0-3.6V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption Active Read Current: (typical) Standby Current: (typical) Fast Sector-Erase/Byte-Program Operation Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) Operational Modes Count (LPC) interface mode in-system operation Parallel Programming (PP) mode fast production programming Interface Mode 5-signal interface supporting byte Read Write clock frequency operation TBL# pins provide hardware write protect entire chip and/or Boot Block Block Locking Registers individual block write-lock lock-down protection JEDEC Standard Command Data# Polling Toggle End-of-Write detection pins system design flexibility pins multi-chip selection Parallel Programming (PP) Mode 11-pin multiplexed address 8-pin data interface Supports fast programming in-system programmer equipment CMOS Compatibility Packages Available 32-lead PLCC 40-lead TSOP (10mm 20mm)
PRODUCT DESCRIPTION
SST49LF004B flash memory device designed interface with host controllers (chipsets) that support lowpin-count (LPC) interface BIOS applications. SST49LF004B device complies with Intel's Interface Specification 1.1, supporting single-byte Firmware Memory Memory cycle types. SST49LF004B backward compatible SST49LF00xA Firmware SST49LF0x0A Flash. this document, mode SST49LF00xA specification referenced Firmware Memory Read/ Write cycle mode SST49LF0x0A specification referenced Memory Read/Write cycle. interface modes supported SST49LF004B: mode (Firmware Memory Memory cycle types) in-system operations Parallel Programming (PP) mode interface with programming equipment. SST49LF004B flash memory device manufactured with SST's proprietary, high-performance SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain greater reliability manufacturability com©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03
pared with alternative approaches. SST49LF004B device significantly improves performance reliability, while lowering power consumption. SST49LF004B device writes (Program Erase) with single 3.0-3.6V power supply. SST49LF004B provides maximum Byte-Program time µsec. entire memory erased programmed byte-by-byte seconds when using status detection features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent writes, SST49LF004B device on-chip hardware software write protection schemes. offered with typical endurance 100,000 cycles. Data retention rated greater than years. SST49LF004B uses less energy during Erase Program than alternative flash memory technologies. total energy consumed function applied voltage, current time application. Since given voltage range SuperFlash technology uses less current pro-
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Intel registered trademark Intel Corporation. These specifications subject change without notice.
Mbit Firmware Flash SST49LF004B
Data Sheet gram shorter erase time, total energy consumed during Erase Program operation less than alternative flash memory technologies. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. This means system software hardware does have calibrated correlated cumulative number Erase cycles necessary with alternative flash memory technologies, whose Erase Program times increase with accumulated Erase/Program cycles.
TABLE CONTENTS
PRODUCT DESCRIPTION LIST FIGURES LIST TABLES. FUNCTIONAL BLOCKS ASSIGNMENTS DESCRIPTIONS Clock Input/Output Communications Input Communication Frame. Interface Mode Select Reset. Identification Inputs General Purpose Inputs Write Protect Block Lock Column Select Output Enable Write Enable Connection DEVICE MEMORY DESIGN CONSIDERATIONS PRODUCT IDENTIFICATION MODE SELECTION
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet MODE Device Operation Firmware Memory Read Cycle Firmware Memory Write Cycle Memory Read Cycle Memory Write Cycle Abort Mechanism Response Invalid Fields Firmware Memory Cycle. Response Invalid Fields Memory Cycle Multiple Device Selection Write Operation Status Detection Registers. PARALLEL PROGRAMMING MODE Device Operation Write Operation Status Detection Data Protection Mode) SOFTWARE COMMAND SEQUENCE ELECTRICAL SPECIFICATIONS Characteristics Characteristics (LPC Mode) Characteristics Mode) PRODUCT ORDERING INFORMATION. PACKAGING DIAGRAMS
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
LIST FIGURES
FIGURE Assignments 32-lead PLCC FIGURE Assignments 40-lead TSOP (10mm 20mm) FIGURE Device Memory FIGURE Firmware Memory Read Cycle Waveform FIGURE Firmware Memory Write Cycle Waveform FIGURE Memory Read Cycle Waveform FIGURE Memory Write Cycle Waveform FIGURE LCLK Waveform (LPC Mode) FIGURE Output Timing Parameters (LPC Mode) FIGURE Input Timing Parameters (LPC Mode) FIGURE Reset Timing Diagram (LPC Mode). FIGURE Reset Timing Diagram Mode) FIGURE Read Cycle Timing Diagram Mode) FIGURE Write Cycle Timing Diagram Mode) FIGURE Data# Polling Timing Diagram Mode) FIGURE Toggle Timing Diagram Mode) FIGURE Byte-Program Timing Diagram Mode) FIGURE Sector-Erase Timing Diagram Mode) FIGURE Block-Erase Timing Diagram Mode) FIGURE Chip-Erase Timing Diagram Mode) FIGURE Software Entry Read Mode) FIGURE Software Exit Mode) FIGURE Input/Output Reference Waveforms FIGURE Test Load Example.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
LIST TABLES
TABLE Description. TABLE Product Identification TABLE Firmware Memory Cycles START Field Definition TABLE Firmware Memory Read Cycle Field Definitions TABLE Firmware Memory Write Cycle. TABLE Memory Read Cycle Field Definitions TABLE Memory Write Cycle Field Definitions TABLE Firmware Memory Multiple Device Selection Configuration TABLE Memory Multiple Device Selection Configuration TABLE Block Locking Registers. TABLE Block Locking Register Bits TABLE Operation Modes Selection Mode) TABLE Software Command Sequence TABLE Operating Characteristics (All Interfaces) TABLE Recommended System Power-up Timings TABLE Capacitance. TABLE Reliability Characteristics. TABLE Clock Timing Parameters (LPC Mode) TABLE Read/Write Cycle Timing Parameters (LPC Mode) TABLE Input/Output Specifications (LPC Mode) TABLE Interface Measurement Condition Parameters (LPC Mode) TABLE Reset Timing Parameters (LPC Mode) TABLE Reset Timing Parameters Mode) TABLE Read Cycle Timing Parameters Mode). TABLE Program/Erase Cycle Timing Parameters Mode) TABLE Revision History
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
TBL# INIT# X-Decoder LAD[3:0] LCLK LFRAME# ID[3:0] GPI[4:0] R/C# A[10:0] DQ[7:0] Control Logic Programmer Interface Buffers Data Latches FWH/LPC Interface Address Buffers Latches Y-Decoder SuperFlash Memory
MODE RST#
1232 B1.0
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
ASSIGNMENTS
RST# (RST#)
(VDD)
R/C# (LCLK)
(GPI2)
(GPI3)
A7(GPI1) (GPI0) (WP#) (TBL#) (ID3) (ID2) (ID1) (ID0) (LAD0)
(GPI4)
MODE (MODE) (VSS) (VDD) (INIT#) (LFRAME#) (RES)
32-lead PLCC View
(LAD1) (LAD2) (LAD3) (RES) (RES) (RES) (VSS)
Designates Mode
1232 32-plcc P1.0
FIGURE ASSIGNMENTS 32-LEAD PLCC
(NC) MODE (MODE) (NC) (NC) (NC) (NC) (GPI4) (NC) R/C# (LCLK) (NC) RST# (RST#) (NC) (NC) (GPI3) (GPI2) (GPI1) (GPI0) (WP#) (TBL#)
Standard Pinout View
(LFRAME#) (INIT#) (NC) (RES) (RES) (RES) (RES) (NC) (LAD3) (LAD2) (LAD1) (LAD0) (ID0) (ID1) (ID2) (ID3)
1232 40-tsop P2.0 Designates Mode
FIGURE ASSIGNMENTS 40-LEAD TSOP (10MM
20MM)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
DESCRIPTIONS
TABLE DESCRIPTION
Interface Symbol LCLK LAD[3:0] Name Clock Address Data LFRAME# Frame MODE Interface Mode Select Type1 Functions provide clock input control unit provide information such addresses command inputs/outputs data. indicate start data transfer operation; also used abort cycle progress. This determines which interface operational. When held high, programmer mode enabled when held low, mode enabled. This must power-up before returning from reset must change during device operation. This must held high (VIH) mode (VIL) mode. This internally pulled-down with resistor between 20100 reset operation device This second reset in-system use. This functions identically RST#. These four pins part mechanism that allows multiple parts attached same bus. strapping these pins used identify component. boot device must have ID[3:0]=0000, subsequent devices should sequential count-up strapping. These pins internally pulled-down with resistor between 20-100 These individual inputs used additional board flexibility. state these pins read through registers. These inputs should their desired state before start clock cycle during which read attempted, should remain place until Read cycle. Unused pins must floated. When low, prevents programming boot block sectors device memory. When TBL# high disables hardware write protection block sectors. This cannot left unconnected. When low, prevents programming highest addressable blocks. When high disables hardware write protection these blocks. This cannot left unconnected. Select Programming interface, this determines whether address pins pointing addresses, column addresses. Inputs low-order addresses during Read Write operations. Addresses internally latched during Write cycle. programming interface, these addresses latched R/C# share same pins highorder address inputs. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. gate data output buffers. control Write operations. These pins must left unconnected. provide power supply (3.0-3.6V) Circuit ground reference) Unconnected pins.
T1.0 1232
RST# INIT# ID[3:0]
Reset Initialize Identification Inputs
GPI[4:0]
General Purpose Inputs
TBL#
Block Lock
Write Protect
R/C# A10-A0
Row/Column Select Address
DQ7-DQ0
Data
Output Enable Write Enable Reserved Power Supply Ground Connection
Input, Output
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Clock
LCLK accepts clock input from host controller.
General Purpose Inputs
General Purpose Inputs (GPI[4:0]) used digital inputs read. register holds values these pins. data pins must stable before start register Read remain stable until Read cycle complete. pins must driven low, VIL, high, left unconnected (float).
Input/Output Communications
LAD[3:0] pins used serially communicate cycle information such cycle type, cycle direction, selection, address, data, sync fields.
Input Communication Frame
LFRAME# used indicate start cycle. also used abort cycle progress.
Write Protect Block Lock
Boot Lock (TBL#) Write Protect (WP#) pins provided hardware write protection device memory SST49LF004B. TBL# used write protect KByte highest memory address range SST49LF004B. write protects remaining sectors flash memory. active signal TBL# prevents Program Erase operations boot block. When TBL# held high, hardware write protection boot block disabled. serves same function remaining blocks device memory. TBL# pins write protection functions operate independently another. Both TBL# pins must their required protection states prior starting Program Erase operation. logic level change occurring TBL# during Program Erase operation could cause unpredictable results.
Interface Mode Select
MODE used interface mode. mode logic high, device mode. mode low, device mode. mode selection must configured prior device operation. mode internally pulled down left unconnected.
Reset
INIT# RST# initiates device reset. INIT# RST# pins have same function internally. required drive INIT# RST# pins during system reset ensure proper initialization. During Read operation, driving INIT# RST# pins deselects device places output drivers, LAD[3:0], high impedance state. reset signal must held minimum time TRSTP reset latency occurs reset pro. cedure performed during Program Erase operation. Table Table Reset Timing Parameters, more information. device reset during active Program Erase operation will abort operation memory contents become invalid data being altered corrupted from incomplete Erase Program operation.
Column Select
R/C# used control multiplex address inputs Parallel Programming (PP) mode. column addresses mapped higher internal addresses (A18-11), addresses mapped lower internal address (A10-0).
Output Enable
used gate output data buffers mode.
Identification Inputs
These pins part mechanism that allows multiple devices attached same bus. strapping these pins used identify component. boot device must have ID[3:0] subsequent devices should sequential count-up strapping. These pins internally pulled-down with resistor between 20-100
Write Enable
used control write operations mode.
Connection
These pins connected internally.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
DEVICE MEMORY
TBL#
7FFFFH Block 70000H 6FFFFH Block 60000H 5FFFFH Block 50000H 4FFFFH Block 40000H 3FFFFH Block
Boot Block
30000H 2FFFFH Block 20000H 1FFFFH Block 10000H 0F000H 0EFFFH 03000H 02000H 01000H 00000H
KByte Sector
Block KByte)
KByte Sector KByte Sector KByte Sector
1232 F02.0
FIGURE DEVICE MEMORY
DESIGN CONSIDERATIONS
recommends high frequency ceramic capacitor placed close possible between less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin. socket used programming purposes, additional 1-10 should added next each socket. RST# INIT# pins must remain stable entire duration Erase Program operation. must remain stable entire duration Erase Program operations non-Boot Block sectors. write data Boot Block sectors, TBL# must also remain stable entire duration Erase Program operations.
PRODUCT IDENTIFICATION
Product Identification mode identifies device SST49LF004B manufacturer SST. TABLE PRODUCT IDENTIFICATION
Address Mode Manufacturer's Device SST49LF004B 0001H FFBC 0001H 60H2
T2.0 1232
Data
Mode1 FFBC 0000H
0000H
Address shown this column boot device only. Address locations should appear elsewhere GByte system memory depending strapping values ID[3:0] pins when multiple memory devices used system. device SST49LF004B same SST49LF004A.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
MODE SELECTION
SST49LF004B flash memory device operates distinct interface modes: mode Parallel Programming (PP) mode. mode, communication between Host SST49LF004B occurs 4bit communication signals, LAD[3:0], LFRAME#. mode, device controlled addresses, A10-A0, I/O, DQ7-DQ0, signals. address inputs multiplexed column selected control signal R/C# pin. addresses mapped lower internal addresses (A10-0), column addresses mapped higher internal addresses (A18-11). Figure Device Memory Map, address assignments.
MODE Device Operation
mode uses 5-signal communication interface consisting control line, LFRAME#, which driven host start abort cycle, 4-bit data bus, LAD[3:0], which used communicate cycle type, cycle direction, selection, address, data sync fields. device enters standby mode when LFRAME# high internal operation progress. SST49LF004B supports both single-byte Firmware Memory Read/Write cycles single-byte Memory Read/Write cycles defined Intel's Low-Pin-Count Interface Specification, Revision 1.1. host drives LFRAME# more clock cycles initiate cycle. last latched value LAD[3:0] before LFRAME# START value. START value determines whether SST49LF004B will respond Firmware Memory Read/Write cycle Memory Read/ Write cycle defined Table TABLE FIRMWARE MEMORY CYCLES START FIELD DEFINITION
START Value Definition 0000 Start memory cycle. direction (Read Write) determined second field cycle. Start Firmware Memory Read cycle Start Firmware Memory Write cycle
T3.0 1232
1101 1110
following sections details Firmware Memory Memory cycle types. JEDEC standard (Software Data Protection) Program Erase command sequences used initiate Firmware Memory Program Erase operations. Table listing Program Erase commands. Chip-Erase only available mode.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Firmware Memory Read Cycle
TABLE FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS
Clock Cycle Field Name START Field Contents LAD[3:0]1 1101 LAD[3:0] Direction Comments LFRAME# must active (low) device respond. Only last field latched before LFRAME# transitions high will recognized. START field contents (1101b) indicate Firmware Memory Read cycle. Indicates which SST49LF004B device should respond. IDSEL select) field matches value ID[3:0], device will respond cycle. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. MSIZE field indicates many bytes will transferred during multi-byte operations. SST49LF004B only supports single-byte operation. MSIZE=0000b this clock cycle, master (Intel ICH) driven `1's then floats bus, prior next clock cycle. This first part "turnaround cycle." SST49LF004B takes control during this cycle. During this clock cycle, device generates "ready sync" (RSYNC) indicating that device received input data. ZZZZ least-significant nibble data byte. ZZZZ most-significant nibble data byte. this clock cycle, SST49LF004B drives ones then floats prior next clock cycle. This first part "turnaround cycle." host resumes control during this cycle.
T4.0 1232
IDSEL
0000 1111
MADDR
YYYY
MSIZE
0000 Byte)
TAR0
1111
then Float
TAR1 RSYNC
1111 (float) 0000 (READY)
Float then
DATA DATA TAR0
ZZZZ ZZZZ 1111
then Float Float then
TAR1
1111 (float)
Field contents valid rising edge present clock cycle.
LCLK
LFRAME#
Start IDSEL 0000b MADDR A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] MSIZE 0000b TAR0 1111b TAR1 Tri-State RSYNC 0000b DATA D[3:0] D[7:4]
LAD[3:0]
1101b
1232 F03.0
FIGURE FIRMWARE MEMORY READ CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Firmware Memory Write Cycle
TABLE FIRMWARE MEMORY WRITE CYCLE
Clock Cycle Field Name START Field Contents LAD[3:0]1 1110 LAD[3:0] Direction Comments LFRAME# must active (low) device respond. Only last field latched before LFRAME# transitions high will recognized. START field contents (1110b) indicate Firmware Memory Write cycle. Indicates which SST49LF004B device should respond. IDSEL select) field matches value ID[3:0], device will respond memory cycle. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. MSIZE field indicates many bytes will transferred during multi-byte operations. device only supports single-byte writes. MSIZE=0000b ZZZZ least-significant nibble data byte. ZZZZ most-significant nibble data byte. this clock cycle, host drives '1's then floats prior next clock cycle. This first part "turnaround cycle." SST49LF004B takes control during this cycle. During this clock cycle, device generates "ready sync" (RSYNC) indicating that device received input data. this clock cycle, SST49LF004B drives '1's then floats prior next clock cycle. This first part "turnaround cycle." host resumes control during this cycle.
T5.0 1232
IDSEL
0000 1111
MADDR
YYYY
MSIZE
0000 Byte)
DATA DATA TAR0
ZZZZ ZZZZ 1111
then Float
TAR1 RSYNC
1111 (float) 0000
Float then
TAR0
1111
then Float
TAR1
1111 (float)
Float then
Field contents valid rising edge present clock cycle.
LCLK
LFRAME#
Start IDSEL 0000b MADDR A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] MSIZE 0000b DATA D[3:0] D[7:4] TAR0 1111b TAR1 Tri-State RSYNC 0000b
LAD[3:0]
1110b
1232 F04.0
FIGURE FIRMWARE MEMORY WRITE CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Memory Read Cycle
TABLE MEMORY READ CYCLE FIELD DEFINITIONS
Clock Cycle Field Name START Field Contents LAD[3:0]1 0000 LAD[3:0] Direction Comments LFRAME# must active (low) device respond. Only last field latched before LFRAME# transitions high will recognized. START field contents (0000b) indicate Memory cycle. Indicates type Memory cycle. Bits must "01b" memory cycle. indicates type transfer Read. reserved. Address Phase Memory Cycle. protocol supports 32bit address phase. YYYY nibble entire address. Addresses transferred most-significant nibble first. this clock cycle, host drives then floats bus. This first part "turnaround cycle." SST49LF004B takes control during this cycle. SST49LF004B outputs value 0000b indicating that received data. ZZZZ least-significant nibble data byte. ZZZZ most-significant nibble data byte. this clock cycle, host drives then floats bus. This first part "turnaround cycle." SST49LF004B takes control during this cycle.
T6.0 1232
CYCTYPE ADDR
010X
3-10
YYYY
TAR0 TAR1 SYNC DATA DATA TAR0 TAR1
1111 1111 (float) 0000 ZZZZ ZZZZ 1111 1111 (float)
then Float Float then then Float Float then
Field contents valid rising edge present clock cycle.
LCLK
LFRAME#
Start CYCTYPE 010Xb Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] Load Address Clocks A[11:8] A[7:4] A[3:0] TAR0 1111b TAR1 Tri-State Sync 0000b D[3:0] Data D[7:4]
LAD[3:0]
0000b
Clock Clock
Clocks
Clock Data Clocks 1232 F05.1
FIGURE MEMORY READ CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Memory Write Cycle
TABLE MEMORY WRITE CYCLE FIELD DEFINITIONS
Clock Cycle Field Name START Field Contents LAD[3:0]1 0000 LAD[3:0] Direction Comments LFRAME# must active (low) device respond. Only last field latched before LFRAME# transitions high will recognized. START field contents (0000b) indicate Memory cycle. Indicates type Memory cycle. Bits must "01b" memory cycle. indicates type transfer Write. reserved. Address Phase Memory Cycle. protocol supports 32-bit address phase. YYYY nibble entire address. Addresses transferred most significant nibble first. ZZZZ least-significant nibble data byte. ZZZZ most-significant nibble data byte. this clock cycle, host drives '1's then floats bus. This first part "turnaround cycle." SST49LF004B takes control during this cycle. SST49LF004B outputs values 0000, indicating that received data flash command. this clock cycle, SST49LF004B drives '1's then floats bus. This first part "turnaround cycle." Host resumes control during this cycle.
T7.0 1232
CYCTYPE ADDR
011X
3-10
YYYY
DATA DATA TAR0
ZZZZ ZZZZ 1111
TAR1 SYNC TAR0
1111 (float) 0000 1111
Float then then Float
TAR1
1111 (float)
Float then
Field contents valid rising edge present clock cycle.
LCLK
LFRAME#
Start CYCTYPE 011Xb Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] Load Address Clocks A[11:8] A[7:4] A[3:0] Data D[3:0] Data D[7:4] TAR0 TAR1 Sync 0000b Clock 1232 F06.1
LAD[3:0]
0000b
1111b Tri-State Clocks
Clock Clock
Load Data Clocks
FIGURE MEMORY WRITE CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Abort Mechanism
LFRAME# driven more clock cycles after start cycle, cycle will terminated. host drive LAD[3:0] with '1111b' (ABORT nibble) return interface ready mode. ABORT only affects current cycle. multi-cycle command sequence, such Erase Program commands, ABORT doesn't interrupt entire command sequence, only current cycle command sequence. host re-send cycle aborted command continue command sequence after device ready again.
Response Invalid Fields Memory Cycle
mismatch: information included address bits every Memory cycle. Address bits A23, A21:A19 used select device with proper IDs. SST49LF004B will compare bits address field with ID[3:0]. bits address correspond hardware pins device will ignore cycle. Multiple Device Selection section details. Address range: address sequence fields long bits). Address bits A23, A21:A19 used select device with proper IDs. SST49LF004B responds address range FFFF FFFFH FF80 0000H 000F FFFFH 000E 0000H during memory cycle transfers. Address special function directing reads writes flash core (A22=1) register space (A22=0). Once valid START, CYCTYPE DIR, address range (including bits) received, SST49LF004B will always complete cycle. However, device busy performing flash Erase Program operation, internal Write command (memory Write register Write) will executed. long states LAD[3:0] LFRAME# known, response SST49LF004B signals received during cycle should predictable.
Response Invalid Fields Firmware Memory Cycle
SST49LF004B will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows: mismatch: IDSEL field does match ID[3:0], device will ignore cycle. Multiple Device Selection section details. Address range: address sequence fields long bits) Firmware Memory cycles, only A18:A0 will decoded SST49LF004B. Address special function directing reads writes flash core (A22=1) register space (A22=0). Invalid MSIZE field: device receives invalid MSIZE field during Firmware Memory Read Write cycle, device will reset operation will attempted. SST49LF004B will generate kind response this situation. Invalid size fields Firmware Memory cycle data other than 0000b. Once valid START, IDSEL, MSIZE fields received, SST49LF004B will always complete cycle. However, device busy performing flash Erase Program operation, Write command (memory write register write) will executed.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Multiple Device Selection
Multiple flash devices strapped increase memory densities system. four pins, ID[3:0], allow devices attached same using different strapping system. BIOS support, loading, attaching bridge limit this number. boot device must have 0000b (determined ID[3:0]); subsequent devices incremental numbering. Equal density must used with multiple devices. Multiple Device Selection Firmware Memory Cycle Firmware Memory Read/Write cycles, hardware strapping values ID[3:0] must match values IDSEL field. Table multiple device selection configurations. SST49LF004B will compare IDSEL field with ID[3:0]'s strapping values. there mismatch, device will ignore reminder cycle. TABLE FIRMWARE MEMORY MULTIPLE DEVICE SELECTION CONFIGURATION
Device (Boot device) ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
T8.0 1232
Multiple Device Selection Memory Cycle Memory Read/Write cycles, information included address bits every cycle. bits address field inverse hardware strapping. address bits (A23, A21:A19) used select device with proper IDs. Table multiple device selection configurations. SST49LF004B will compare these bits with ID[3:0]'s strapping values. there mismatch, device will ignore remainder cycle. TABLE MEMORY MULTIPLE DEVICE SELECTION CONFIGURATION
Device (Boot device) ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A23, A21:A19 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
T9.0 1232
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Write Operation Status Detection
SST49LF004B device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling, D[7], Toggle Bit, D[6]. End-of-Write detection mode incorporated into Firmware Memory Memory Read cycles. actual completion nonvolatile write asynchronous with system. Therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either D[7] D[6]. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling When SST49LF004B device internal Program operation, attempt read D[7] will produce complement true data. Once Program operation completed, D[7] will produce true data. Note that even though D[7] have valid data immediately following completion internal Write operation, remaining data outputs still invalid. Valid data will appear entire data subsequent successive Read cycles after interval During internal Erase operation, attempt read D[7] will produce '0'. Once internal Erase operation completed, D[7] will produce '1'. Proper status will given using Data# Polling address invalid range. Toggle During internal Program Erase operation, consecutive attempts read D[6] will produce alternating i.e., toggling between When internal Program Erase operation completed, toggling will stop. Note that even though D[6] have valid data immediately following completion internal Write operation, remaining data outputs still invalid. Valid data will appear entire data subsequent successive Read cycles after interval Proper status will given using Toggle address invalid range.
isters appear their respective address location GByte system memory map. Unused register locations will read 00H. attempt read write register during internal Write operation will ignored. General Purpose Inputs Register GPI_REG (General Purpose Inputs Register) passes state GPI[4:0] outputs. recommended that GPI[4:0] pins desired state before LFRAME# brought beginning cycle, remain that state until cycle. There default value since this pass-through register. register boot device appears FFBC0100H GByte system memory map, will appear elsewhere device boot device. register available read when device Erase/Program operation. Block Locking Registers SST49LF004B provides software controlled lock protection through Block Locking registers. Block Locking registers Read/Write registers accessible through standard addressable memory locations specified Table Table Unused register locations will read 00H. Write Lock: Write-Lock bit, controls lock state. default Write status blocks after power write locked. When Block Locking register set, Program Erase operations corresponding block prevented. Clearing Write-Lock will unprotect block. Write-Lock must cleared prior starting Program Erase operation since sampled beginning operation. Write-Lock functions conjunction with hardware Write Lock TBL# Boot Block. When TBL# low, overrides software locking scheme. Boot Block Locking register does indicate state TBL# pin. Write-Lock functions conjunction with hardware blocks When low, overrides software locking scheme. Block Locking registers indicate state pin. Lock Down: Lock-Down bit, controls Block Locking registers. default Lock Down status blocks upon power-up locked down. Once LockDown set, future attempted changes that Block Locking register will ignored. Lock-Down only cleared upon device reset with RST# INIT# power down. Current Lock Down status particular block determined reading corresponding Lock-Down bit.
Registers
There three types registers available SST49LF004B, General Purpose Inputs register, Block Locking registers, JEDEC registers. These reg-
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet TABLE BLOCK LOCKING REGISTERS
Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK Block Size Protected Memory Address Package 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 000000H Memory Register Address FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H
T10.0 1232
TABLE BLOCK LOCKING REGISTER BITS
Reserved [7.2] 000000 000000 000000 000000 Lock-Down Write-Lock Lock Status Full Access Write Locked (Default State Power-Up) Locked Open (Full Access Locked Down) Write Locked Down
T11.0 1232
JEDEC Registers JEDEC registers provide access manufacturer device information with single Read cycle. JEDEC registers boot device appear FFBC0000H FFBC0001H GByte system memory map, will appear elsewhere device boot device. Registers available read when device Erase/Program operation. Refer Table product identification information.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
PARALLEL PROGRAMMING MODE Device Operation
Commands used initiate memory operation functions device. data portion software command sequence latched rising edge WE#. During software command sequence address latched falling edge R/C# column address latched rising edge R/C#. Read Read operation SST49LF004B device controlled OE#. output control used gate data from output pins. Refer Read cycle timing diagram, Figure further details. Reset RST# initiates device reset. Byte-Program Operation SST49LF004B device programmed byte-bybyte basis. Before programming, must ensure that byte that being programmed fully erased. ByteProgram operation initiated executing four-byte command load sequence Software Data Protection with address (PA) data last cycle. During Byte-Program operation, address (A10-A0) latched falling edge R/C# column Address (A21-A11) latched rising edge R/C#. data latched rising edge WE#. Program operation, once initiated, will completed, within Figure timing waveforms. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored. Sector-Erase Operation Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. SectorErase operation initiated executing six-byte command load sequence Software Data Protection with Sector-Erase command (30H) sector address (SA) last cycle. internal Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure Sector-Erase timing waveforms. commands written during Sector-Erase operation will ignored. Block-Erase Operation Block-Erase Operation allows system erase uniform KByte blocks. Block- Erase operation initiated executing six-byte command load sequence Software Data Protection with Block-Erase command (50H) block address (BA) last cycle. internal Block-Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Block- Erase operation will ignored. Chip-Erase Operation SST49LF004B device provides Chip-Erase operation only mode, which allows user erase entire memory array '1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing six- byte Software Data Protection command sequence with Chip- Erase command (10H) with address 5555H last cycle. internal Erase operation begins with rising edge sixth WE#. During internal Erase operation, only valid reads Toggle Data# Polling. Table command sequence, Figure timing diagram. commands written during Chip-Erase operation will ignored.
Write Operation Status Detection
SST49LF004B device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, device completed Write cycle, otherwise rejection valid.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet TABLE OPERATION MODES SELECTION MODE)
Mode Read Program Erase Reset Write Inhibit Product Identification RST# DOUT High High Z/DOUT Manufacturer's (BFH) Device (60H) Address Sector Block address, Chip-Erase VIL, VIL,
T12.0 1232
VIH, other value.
Data# Polling (DQ7) When SST49LF004B device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid. Valid data will appear entire data subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce '0'. Once internal Erase operation completed, will produce '1'. Data# Polling valid after rising edge fourth pulse Program operation. Sector-Erase, BlockErase, Chip-Erase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram. Proper status will given using Data# Polling address invalid range. Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating '0's '1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth pulse Program operation. Sector-Erase, BlockErase Chip-Erase, Toggle valid after rising edge sixth pulse. Figure Toggle timing diagram.
Data Protection Mode)
SST49LF004B device provides both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST49LF004B provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power down. Erase operation requires inclusion five-byte load sequence.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
SOFTWARE COMMAND SEQUENCE
TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase6 Software Entry Software Exit8 Software Exit8 1st1 Cycle
Addr2
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H
2nd1 Cycle
Data
3rd1 Cycle
Data
4th1 Cycle
Data
5th1 Cycle
Data
Data YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH
6th1 Cycle
Data Addr2
SAX4 BAX5 YYYY 5555H
Addr2
YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH
Addr2
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H
Addr2
YYYY 5555H YYYY 5555H YYYY 5555H Read
Addr2
Data
XXXX XXXXH
YYYY 5555H
YYYY 2AAAH
YYYY 5555H
T13.0 1232
mode consecutive Write cycles complete command sequence; mode consecutive cycles complete command sequence. YYYY A[31:16]. mode, during command sequence, YYYY must within valid memory address range, Address range section details. mode, YYYY VIH, other value. Program Byte address Sector-Erase Address Block-Erase Address Chip-Erase supported mode only Manufacturer's BFH, read with A18-A0 SST49LF004B Device 60H, read with A18-A1 Both Software Exit operations equivalent
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
ELECTRICAL SPECIFICATIONS
specifications interface signals (LA0[3:0], LFRAME, LCLCK RST#) defined Section 4.2.2.4 local specification, Rev. 2.1. Refer Table voltage current specifications. Refer Tables through timing specifications Clock, Read, Write, Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C D.C. Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Package Power Dissipation Capability (Ta=25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Ambient Temp +85°C
3.0-3.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Characteristics
TABLE OPERATING CHARACTERISTICS (ALL INTERFACES)
Limits Symbol Parameter IDD1 Active Current Units Test Conditions LCLK (LPC mode) Address Input mode)=VILT/VIHT f=33 (LPC mode) 1/TRC mode) other inputs=VIL outputs open, VDD=VDD Note LCLK (LPC mode) Address Input mode)=VILT/VIHT f=33 (LPC mode) 1/TRC mode) LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD, VDD=VDD Max, other inputs LCLK (LPC mode) Address Input mode)=VILT/VIHT f=33 (LPC mode) 1/TRC mode) LFRAME#=VIL, f=33 MHz, VDD=VDD other inputs VIN=GND VDD, VDD=VDD
Read Write2 Standby Current (LPC Interface)
IRY3
Input Current Mode ID[3:0] pins Input Leakage Current Mode ID[3:0] pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage -0.5 -0.5
VIHI VILI
VDD+0.5 VDD+0.5
VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD
T14.2 1232
active while Read Write (Program Erase) operation progress. mode: VIH; mode: 1/TRC min, LFRAME# VIH. device Ready mode when activity bus.
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T15.0 1232
This parameter measured only initial qualification after design process change that could affect this parameter
TABLE CAPACITANCE
Parameter CI/O
(VDD=3.3V, Ta=25 Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O=0V VIN=0V
Maximum
T16.0 1232
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet TABLE RELIABILITY CHARACTERISTICS
Symbol NEND
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T17.0 1232
ILTH1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CLOCK TIMING PARAMETERS (LPC MODE)
Symbol TCYC THIGH TLOW Parameter LCLK Cycle Time LCLK High Time LCLK Time LCLK Slew Rate (peak-to-peak) RST# INIT# Slew Rate Units V/ns mV/ns
T18.0 1232
Tcyc Thigh Tlow
1232 F07.0
p-to-p (minimum)
FIGURE LCLK WAVEFORM (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Characteristics (LPC Mode)
TABLE READ/WRITE CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (LPC MODE)
Symbol TCYC TVAL1 TOFF Parameter Clock Cycle Time Data Time Clock Rising Clock Rising Data Hold Time Clock Rising Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Clock Rising Active (Float Active Delay) Clock Rising Inactive (Active Float Delay) Units
T19.0 1232
Minimum maximum times have different loads. spec
TABLE INPUT/OUTPUT SPECIFICATIONS (LPC MODE)
Symbol IOH(AC) Parameter Switching Current High -17.1(VDD-VOUT) Equation (Test Point) IOL(AC) Switching Current 26.7 VOUT Equation V/ns V/ns Units Conditions VOUT 0.3VDD 0.3VDD VOUT 0.9VDD 0.7VDD VOUT VOUT 0.7VDD >VOUT 0.6VDD 0.6VDD VOUT 0.1VDD 0.18VDD VOUT VOUT 0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load
T20.0 1232
(Test Point) slewr slewf Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015
spec.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
LCLK VTEST TVAL [3:0] (Valid Output Data)
[3:0] (Float Output Data)
TOFF
1232 F09.0
FIGURE OUTPUT TIMING PARAMETERS (LPC MODE)
LCLK [3:0] (Valid Input Data) Inputs Valid VTEST
VMAX
1232 F10.0
FIGURE INPUT TIMING PARAMETERS (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet TABLE INTERFACE MEASUREMENT CONDITION PARAMETERS (LPC MODE)
Symbol VTH1
Value
Units V/ns
T21.0 1232
VTEST VMAX
Input Signal Edge Rate
input test environment done with overdrive over VIL. Timing parameters must with more overdrive than this. VMAX specifies maximum peak-to-peak waveform allowed measuring input timing. Production testing different voltage values, must correlate results back these parameters.
TABLE RESET TIMING PARAMETERS, VDD=3.0-3.6V (LPC MODE)
Symbol TPRST TKRST TRSTP TRSTF TRST1 TRSTE Parameter stable Reset Clock Stable Reset RST# Pulse Width RST# Output Float RST# High LFRAME# RST# reset during Sector-/Block-Erase Program Units
T22.0 1232
There will latency TRSTE reset procedure performed during Program Erase operation,
TPRST
TKRST RST#/INIT# TRSTP TRSTE TRSTF LAD[3:0] TRST
Sector-/Block-Erase Program operation aborted
LFRAME#
1232 F08.0
FIGURE RESET TIMING DIAGRAM (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Data Sheet TABLE RESET TIMING PARAMETERS, VDD=3.0-3.6V MODE)
Symbol TPRST TRSTP TRSTF TRST1 TRSTE TRSTC Parameter stable Reset RST# Pulse Width RST# Output Float RST# High Address Setup RST# reset during Sector-/Block-Erase Program RST# reset during Chip-Erase Units
T23.0 1232
There will reset latency TRSTE TRSTC reset procedure performed during programming erase operational.
TPRST
Addresses
Address
R/C#
RST#
TRSTP
TRSTE Sector-/Block-Erase Program operation aborted Chip-Erase aborted
TRSTC TRSTF TRST
DQ7-0
1232 F11.0
FIGURE RESET TIMING DIAGRAM MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Characteristics Mode)
TABLE READ CYCLE TIMING PARAMETERS, VDD=3.0-3.6V MODE)
Symbol TRST TOLZ TOHZ Parameter Read Cycle Time RST# High Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time Active Output High High-Z Output Output Hold from Address Change Units
T24.0 1232
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS, VDD=3.0-3.6V MODE)
Symbol TRST TCWH TOES TOEH TOEP TOET TWPH TIDA TSCE Parameter RST# High Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# Write Enable High Time High Setup Time High Hold Time Data# Polling Delay Toggle Delay Pulse Width Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time Units
T25.0 1232
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
RST# Addresses
TRST Address
Column Address Address Column Address
R/C#
TOLZ High-Z TOHZ Data Valid High-Z
DQ7-0
1232 F12.0
FIGURE READ CYCLE TIMING DIAGRAM MODE)
TRST RST# Addresses Address R/C# TCWH DQ7-0 Data Valid
1232 F13.0
Column Address TOEH TWPH
TOES
FIGURE WRITE CYCLE TIMING DIAGRAM MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
Addresses
Column
R/C#
TOEP
1232 F15.0
FIGURE DATA# POLLING TIMING DIAGRAM MODE)
Addresses
Column
R/C#
TOET
1232 F15.0
FIGURE TOGGLE TIMING DIAGRAM MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
A14-0 (Internal AMS-0) R/C# DQ7-0
5555
2AAA
5555
Internal Program Starts DATA
Byte-Program Address Most Significant Address
1232 F16.0
FIGURE BYTE-PROGRAM TIMING DIAGRAM MODE)
A14-0 (Internal AMS-0) R/C#
5555
2AAA
5555
5555
2AAA
Internal Erase Starts DQ7-0 Sector Address
1232 F17.0
FIGURE SECTOR-ERASE TIMING DIAGRAM MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
A14-0 (Internal AMS-0) R/C#
5555
2AAA
5555
5555
2AAA
Internal Erase Starts DQ7-0 Block Address
1232 F18.0
FIGURE BLOCK-ERASE TIMING DIAGRAM MODE)
A14-0 (Internal AMS-0) R/C#
5555
2AAA
5555
5555
2AAA
5555
Internal Erase Starts DQ7-0
1232 F19.0
FIGURE CHIP-ERASE TIMING DIAGRAM MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
A14-0 (Internal AMS-0) R/C#
5555
2AAA
5555
0000
0001
DQ7-0 TWPH TIDA Device
1232 F20.0
FIGURE SOFTWARE ENTRY
READ MODE)
A14-0 (Internal AMS-0) R/C# DQ7-0
5555
2AAA
5555
TIDA
1232 F21.0
FIGURE SOFTWARE EXIT MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1232 F22.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1232 F23.0
FIGURE TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Environmental Attribute non-Pb Package Modifier leads leads Package Type PLCC TSOP (type 10mm 20mm) Operating Temperature Commercial +85°C Minimum Endurance 10,000 cycles Serial Access Clock Frequency Device Density Mbit Voltage Range 3.0-3.6V Product Series Firmware Memories
SST49LF004B
Valid combinations SST49LF004B SST49LF004B-33-4C-EI SST49LF004B-33-4C-EIE SST49LF004B-33-4C-NH SST49LF004B-33-4C-NHE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Mbit Firmware Flash SST49LF004B
1.05 0.95 Identifier 0.50
10.10 9.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
40-tsop-EI-7
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM PACKAGE CODE:
20MM
TABLE REVISION HISTORY
Number Description Date 2003 2003
Initial release Added footnote Table page Removed signal from Figures Changes Table page Changed VIHI values Updated Test Conditions 2004 Data Book Updated status "Data Sheet"
2003
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03

SST49LF004B SST49LF004B4Mb Firmware memory FEATURES: SS

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