SST34HF32A4 SST34HF32x4x32Mb 4/8/16 SRAM (x16) ComboMemory F

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SST34HF32A4 SST34HF32x4x32Mb 4/8/16 SRAM (x16) ComboMemory F

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Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory
SST34HF32A4
SST34HF32x4x32Mb 4/8/16 SRAM (x16) ComboMemory
FEATURES:
Flash Organization: Dual-Bank Architecture Concurrent Read/Write Operation Mbit Sector Protection Mbit: Mbit 24Mbit PSRAM Organization: Mbit: 1024K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Hardware Sector Protection (WP#) Protects KWord smaller bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array Byte Selection Flash (CIOF pin) Selects 8-bit 16-bit mode (56-ball package only) Sector-Erase Capability Uniform KWord sectors Flash Chip-Erase Capability Block-Erase Capability Uniform KWord blocks Erase-Suspend Erase-Resume Capabilities Read Access Time Flash: PSRAM: Security Feature SST: bits User: bits Latched Address Data Fast Erase Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Program Time: Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility JEDEC Standard Command Packages Available 56-ball LFBGA (8mm 10mm) 62-ball LFBGA (8mm 10mm) non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST34HF32A4 ComboMemory devices integrate either CMOS flash memory bank with 1024K CMOS pseudo SRAM (PSRAM) memory bank multi-chip package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF32A4 devices ideal applications such cellular phones, devices, PDAs, other portable electronic devices power small form factor system. SST34HF32A4 feature dual flash memory bank architecture allowing concurrent operations between flash memory banks PSRAM. devices read data from either bank while Erase Program operation progress opposite bank. flash memory banks partitioned into Mbit Mbit with sector protection options storing boot code, program code, configuration/parameter data user data. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF32A4 devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high-performance Program operations, flash memory banks provide typical Program time µsec. entire flash memory bank erased programmed word-by-word typically seconds SST34HF32A4, when using interface features such Toggle Bit, Data# Polling, RY/BY# indicate
©2006 Silicon Storage Technology, Inc. S71313-00-000 2/06
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Intel registered trademark Intel Corporation. ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information completion Program operation. protect against inadvertent flash write, SST34HF32A4 devices contain onchip hardware software data protection schemes. flash PSRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. PSRAM bank enable signals, BES1# BES2, select PSRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. Designed, manufactured, tested applications requiring power small form factor, SST34HF32A4 offered both commercial extended temperatures small footprint package meet board space constraint requirements. Figure assignments.
Concurrent Read/Write Operation
Dual bank architecture SST34HF32A4 devices allows Concurrent Read/Write operation whereby user read from bank while programming erasing other bank. This operation used when user needs read system code bank while updating data other bank. Table dual-bank memory organization. Concurrent Read/Write States
Flash Bank Read Write Write Operation Write Operation Bank Write Read Operation Write Operation Write PSRAM Operation Operation Read Read Write Write
Device Operation
SST34HF32A4 uses BES1#, BES2 BEF# control operation either flash PSRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high PSRAM activated Read Write operation. BEF# BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash PSRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES1# bank enables raised VIHC (Logic High) when BEF# high BES2 low.
Note: purposes this table, write means perform Block-/Sector-Erase Program operations applicable appropriate bank.
Flash Read Operation
Read operation SST34HF32A4 controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram Figure details.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Flash Program Operation
These devices programmed word-by-word byte-by-byte basis depending state CIOF pin. Before programming, must ensure that sector being programmed fully erased. Program operation accomplished three steps: Software Data Protection initiated using three-byte load sequence. Address data loaded. During Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. internal Program operation initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Flash Chip-Erase Operation
SST34HF32A4 provide Chip-Erase operation, which allows user erase flash sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. When low, attempt Chip-Erase will ignored.
Flash Erase-Suspend/-Resume Operations
Erase-Suspend operation temporarily suspends Sector- Block-Erase operation thus allowing data read from memory location, program data into sector/block that suspended Erase operation. operation executed issuing one-byte command sequence with Erase-Suspend command (B0H). device automatically enters read mode within after Erase-Suspend command been issued. Valid data read from sector block that suspended from Erase operation. Reading address location within erase-suspended sectors/blocks will output toggling "1". While Erase-Suspend mode, Program operation allowed except sector block selected Erase-Suspend. resume Sector-Erase Block-Erase operation which been suspended, system must issue Erase-Resume command. operation executed issuing one-byte command sequence with Erase Resume command (30H) address one-byte sequence.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase Block-Erase operations. These operations allow system erase devices sector-by-sector block-by-block) basis. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. Sector-Erase operation initiated executing six-byte command sequence with Sector-Erase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (30H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. commands issued during Block- SectorErase operation ignored except Erase-Suspend Erase-Resume. Figures timing waveforms.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Flash Write Operation Status Detection
SST34HF32A4 provide hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/ Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Byte/Word (CIOF)
This function, found only 56-ball package, includes CIOF control whether device data pins operate x16. CIOF logic (VIH) device data configuration: data pins DQ0-DQ15 active controlled BEF# OE#. CIOF logic "0", device data configuration: only data pins DQ0-DQ7 active controlled BEF# OE#. remaining data pins DQ8DQ14 Hi-Z, while DQ15 used address input Least Significant address bus.
Flash Data# Polling (DQ7)
When devices internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart.
Ready/Busy# (RY/BY#)
SST34HF32A4 include Ready/Busy# (RY/BY#) output signal. RY/BY# open drain output that indicates whether Erase Program operation progress. Since RY/BY# open drain output, allows several devices tied parallel external pull-up resistor. After rising edge final pulse command sequence, RY/BY# status valid. When RY/BY# actively pulled low, indicates that Erase Program operation progress. When RY/BY# high (Ready), devices read left standby mode.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Toggle Bits (DQ6 DQ2)
During internal Program Erase operation, consecutive attempts read will produce alternating "1"s "0"s, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. toggle valid after rising edge fourth BEF#) pulse Program operations. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth BEF#) pulse. will Read operation attempted Erase-suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last BEF#) pulse Write operation. Figure Toggle timing diagram Figure flowchart. TABLE Write Operation Status
Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program DQ7# Toggle Toggle Toggle Toggle Toggle RY/BY#
Data Protection
SST34HF32A4 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Hardware Block Protection
SST34HF32A4 provide hardware block protection which protects outermost KWord Bank block protected when held low. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed.
Hardware Reset (RST#)
Data
Data
Data
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 19). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 18). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity. Figures timing diagrams.
DQ7#
Toggle
Toggle
T1.1 1313
Note: DQ7, DQ6, require valid address when reading status information. address must bank where operation progress order read operation status. address pointing different bank (not busy), device will output array data.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Software Data Protection (SDP)
SST34HF32A4 provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF32A4 shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 "Don't Care" during command sequence.
Sec-ID command (88H) address 555H last byte sequence. exit this mode, Exit-Sec-ID command should executed. Refer Table more details.
Product Identification
Product Identification mode identifies device SST34HF32A4 manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash PSRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure Software Entry Read timing diagram Figure Entry command sequence flowchart. TABLE Product Identification
ADDRESS Manufacturer's Device SST34HF32A4 BK0001H 7353H
T2.0 1313
Common Flash Memory Interface (CFI)
These devices also contain information describe characteristics devices. order enter Query mode, system must write three-byte sequence, same Software Entry command with (CFI Query command) address BKX555H last byte sequence. order enter Query mode, system also one-byte sequence with BKX55H Address Data Bus. Figure Entry Read timing diagram. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
DATA 00BFH
BK0000H
Note: Bank Address (A20-A18)
Product Identification Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Security
SST34HF32A4 devices offer 136-bit Security space. Secure space divided into segments-one 128-bit factory programmed segment 128-word (256-byte) user-programmed segment. first segment programmed locked with unique, 128-bit number. user segment left un-programmed customer program desired. program user segment Security user must Security Program command. End-of-Write status checked reading toggle bits. Data# Polling used Security End-of-Write detection. Once programming complete, should locked using User-Sec-ID-Program-Lock-Out. This disables future corruption this space. Note that regardless whether locked, neither segment erased. Secure space queried executing three-byte command sequence with Query-
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
PSRAM Operation
With BES1# low, BES2 BEF# high, SST34HF32A4 operate 1024K CMOS PSRAM, with fully static operation requiring external clocks timing strobes. SST34HF32A4 PSRAM mapped into first 1024 KWord address space. When BES1#, BEF# high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table Read Write data byte control modes operation.
PSRAM Read
PSRAM Read operation SST34HF32A4 controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used PSRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details.
PSRAM Write
PSRAM Write operation SST34HF32A4 controlled BES1#, both have low, BES2 must high system write PSRAM. During Word-Write operation, addresses data referenced rising edge either BES1#, WE#, falling edge BES2 whichever occurs first. write time measured from last falling edge BES#1 rising edge BES2 first rising edge BES1#, falling edge BES2. Refer Write cycle timing diagrams, Figures further details.
PSRAM Deep Power-Down Mode
This mode used lower power consumption PSRAM SST34HF32A4 device only. Deep power-down occurs after being enabled driving BES2 low. Normal operation occurs 500µs after BES2 driven high. deep power-down mode, PSRAM data lost.For details, Figure
Power
Power-up Sequence
BES1# VIL, BES2
Initial State (Wait
Active
Deep Power-down Exit Sequence
BES1# VIL, BES2 BES2 VIH, BES1# VIL, LBS# VIH, BES2 VIH, BES1# UBS# UBS# LBS# and/or LBS#
BES2
Deep Power-down Mode
BES2
Standby Mode
1313 DPDFlwCht.0
FIGURE Deep Power-Down State Diagram
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
A20-
Address Buffers SuperFlash Memory (Bank CIOF RST# BEF# LBS# UBS# BES1# BES2 RY/BY#
SuperFlash Memory (Bank Control Logic Buffers DQ15/A-1
Address Buffers
Mbit PSRAM
Notes: package only:
WEF# and/or WES# OEF# and/or OES#
1313 B1.0
FIGURE Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Dual-Bank Memory Organization
SST34HF32A4 Block BA63 BA62 BA61 BA60 BA59 BA58 BA57 Bank BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 Bank BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 Block Size Address Range 3FC000H-3FFFFFH 3F0000H-3FBFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2FFFFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH Address Range 1FE000H-1FFFFFH 1F8000H-1FDFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Dual-Bank Memory Organization (Continued)
SST34HF32A4 Block BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank BA11 BA10 Block Size Address Range 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH Address Range 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 000000H-007FFFH
T3.0 1313
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
DESCRIPTION
VIEW (balls facing down)
CIOF
DQ15/A-1 DQ14 DQ13 DQ12 VDDS VDDF DQ11 DQ10
1313 56-lfbga P1.0
BES2
RST# RY/BY# LBS# UBS#
BEF# BES1#
FIGURE Assignments 56-ball LFBGA (8mm 10mm
VIEW (balls facing down)
VSSF
DQ15 WES# DQ14 DQ13
WEF# RY/BY#
VSSS RST# DQ12 BES2 VDDS VDDF DQ11 DQ10 BES1#
1313 62-lfbga P2.0
LBS# UBS# OES#
BEF# VSSF OEF#
FIGURE Assignment 62-Ball LFBGA (8mm 10mm)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Description
Symbol Name Address Inputs Functions provide flash address, A20-A0. provide PSRAM address, A19-A0 output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when high BES1# high BES2 BEF# high. DQ15 used data when mode (CIOF "1") used address when mode (CIOF "0") activate Flash memory bank when BEF# activate PSRAM memory bank when BES1# activate PSRAM memory deep power-down mode when BES2 low. gate data output buffers control Write operations When low, select Byte mode. When high, select Word mode. enable DQ15-DQ8 enable DQ7-DQ0 protect unprotect bottom KWord sectors) from Erase Program operation Reset return device Read mode output status Program Erase Operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. Flash only PSRAM only 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply PSRAM only Unconnected pins
T4.0 1313
DQ14-DQ0 Data Inputs/Outputs
DQ15/A-1 BEF# BES1# BES2 CIOF UBS# LBS# RST# RY/BY#
Data Input/Output Address Flash Memory Bank Enable PSRAM Memory Bank Enable PSRAM Deep Power-down Enable Output Enable Write Enable Byte Selection Flash Upper Byte Control (PSRAM) Lower Byte Control (PSRAM) Write Protect Reset Ready/Busy#
VSSF1 VSSS
Ground Ground Ground Power Supply (Flash) Power Supply (PSRAM) Connection
VDDF VDDS
package only
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE OPERATIONAL MODES SELECTION
Mode Full Standby PSRAM Deep Power-down4 Output Disable Flash Read Flash Write Flash Erase PSRAM Read BEF#,1 BES1#1,1 BES21 OE#2,3 WE#2 LBS#2 PSRAM Write Product Identification5 UBS#2 DQ7-0 HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DOUT HIGH-Z DOUT HIGH-Z DQ15-8 HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DOUT DOUT HIGH-Z HIGH-Z
Manufacturer's Device
T5.0 1313
apply BEF# VIL, BES1# BES2 same time. VIH, other value. OEF# OES# WEF# WES# package only PSRAM Deep power-down, PSRAM data lost. Software mode only With A19-A18 VIL;SST Manufacturer's BFH, read with A0=0, SST32HF32A4 Device =7353H, read with A0=1,
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Software Command Sequence
Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query User Security Program User Security Program Lock-out7 Software Entry8 Query Entry9 Query Entry9 Software Exit/ Exit/ Exit10,11 Software Exit/ Exit/ Exit10,11 Write Cycle Addr1
555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H BKX4 555H
Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
Write Cycle Addr1
555H 555H 555H 555H
Write Cycle Addr1
555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH
Write Cycle Addr1
SAX4
Data2
Data2
Data2
Data2
Data
Data2
Data2
555H
2AAH 2AAH 2AAH 2AAH 2AAH
555H 555H 555H BKX4 555H BKX4 555H
SIWA6 Data 0000H
2AAH
555H
T6.0 1313
Address format A10-A0 (Hex), Addresses A20-A11 VIH, other value, command sequence when mode. When mode, Addresses A20-A12, Address DQ14-DQ8 VIH, other value, command sequence. DQ15-DQ8 VIH, other value, command sequence Program Word/Byte address Sector-Erase; uses A20-A11 address lines Block-Erase; uses A20-A15 address lines Bank Address; uses A20-A18 address lines SST34HF32A4 Security Address Range (x16 mode) 0FF000H 0FF087H, mode) 000000H 00010FH read Address Range (x16 mode) 000000H 000007H mode) 000000H 0000FFH User read Address Range (x16 mode) 000008H 000087H mode) 000100H 00010FH Lock Status read Address 0000FFH (x16) 0001FFH (x8). Unlocked: Locked: SIWA User Security Program Word/Byte address SST34HF32A4, valid Address Range (x16 mode) 000008H-000087H mode) 000010H-00010FH. cycles User Security Program Program Lock-out must completed before going back Read-Array mode. User Security Program Lock-out command must executed mode (BYTE#=VIH). device does remain Software Product Identification mode powered down. Both Software Exit operations equivalent users never lock after programming, User programmed over previously unprogrammed bits (data=1) using User mode again (the programmed bits cannot reversed "1").
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE QUERY IDENTIFICATION STRING1
Address Mode Address Mode Data2 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T7.1 1313
Refer publication more details. mode, only lower byte data output.
TABLE SYSTEM INTERFACE INFORMATION
Address Mode Address Mode Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Program times typical Maximum time buffer program times typical Maximum time individual Sector-/Block-Erase times typical Maximum time Chip-Erase times typical
T8.0 1313
mode, only lower byte data output.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE DEVICE GEOMETRY INFORMATION
Address Mode Address Mode Data1 0016H 0002H 0000H 0000H 0000H 0002H 003FH 0000H 0000H 0001H 00FFH 0003H 0010H 0000H Description Device size Bytes (16H MByte) Flash Device Interface description; 0002H x8/x16 asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Block Information Number blocks; 256B block size) blocks (003FH Bytes KByte/block (0100H 256) Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FFH 1023) Bytes KByte/sector (0010H
T9.2 1313
mode, only lower byte data output.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential .-0.5V VDD1+0.3V Transient Voltage (<20 Ground Potential -1.0V VDD1+1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current2
VDDF VDDS Outputs shorted more than second. more than output shorted time.
Operating Range
Range Extended Ambient Temp -20°C +85°C 2.7-3.3V
Conditions Test
Input Rise/Fall Time Output Load Figures
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Operating Characteristics (VDD VDDF VDDS 2.7-3.3V)
Limits Symbol IDD1 Parameter Active Current Read Flash PSRAM Concurrent Operation Write2 Flash PSRAM ILIW VILC VIHC VOLF VOHF VOLS VOHS Standby Current Reset Current Input Leakage Current Input Leakage Current RST# Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage PSRAM Output Voltage PSRAM Output High Voltage PSRAM FLASH Units Test Conditions Address input VILT/VIHT, MHz, VDD=VDD Max, open OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH, BES2=VIL BEF#=VIH, BES1#=VIL BES2=VIH BEF#=VIH, BES1#=VIL BES2=VIH WE#=VIL BEF#=VIL, BES1#=VIH, BES2=VIL, OE#=VIH BEF#=VIH, BES1#=VIL BES2=VIH Max, BEF#=BES1#=VIHC, BES2=VILC, RST# VIHC RST#=GND VIN=GND VDD, VDD=VDD WP#=GND VDD, VDD=VDD RST#=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD VDD=VDD =-500 VDD=VDD
T10.0 1313
VDD-0.3 VDD-0.2
Address input VILT/VIHT, VDD=VDD (See Figure active while Erase Program progress.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
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Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T11.0 1313
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T12.0 1313
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Flash Reliability Characteristics
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T13.0 1313
This parameter measured only initial qualification after design process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
CHARACTERISTICS
TABLE PSRAM Read Cycle Timing Parameters
TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
Units
Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output
T14.0 1313
TOHZS1 TBYHZS TOHS
UBS#, LBS# High-Z Output Output Hold from Address Change
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PSRAM Write Cycle Timing Parameters
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time Units
T15.0 1313
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information TABLE Flash Read Cycle Timing Parameters 2.7-3.3V
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Read
Units
T16.0 1313
TRHR1
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase.
TABLE Flash Program/Erase Cycle Timing Parameters
Symbol TOES TOEH TWPH1 TCPH1 TBY1,2 TBR1 TSCE
Parameter Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Erase-Suspend Latency RY/BY# Delay Time Recovery Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T17.1 1313
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase operations.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TBLZS TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID
1313 F01.0
TOHS
TBHZS TOES TOHZS TBYES TBYHZS
Note: AMSS Most Significant Address AMSS SST34HF32A4
FIGURE PSRAM Read Cycle Timing Diagram
TWCS ADDRESSES AMSS3-0
TAWS
TASTS
TWPS
TWRS
TBWS
BES1# TBYWS TODWS DQ15-8, DQ7-0
NOTE
UBS#, LBS#
TDSS
TOEWS TDHS
NOTE
1313 F02.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. BES1# goes BES2 goes high coincident with after goes Low, output will remain high impedance. BES1# goes High BES2 goes coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant PSRAM Address AMSS SST34HF32A4
FIGURE PSRAM Write Cycle Timing Diagram (WE# Controlled)1
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
TWCS ADDRESSES AMSS3-0 TWPS TBWS BES1# TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0
NOTE
TWRS
TBYWS
TDHS
NOTE
1313 F03.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant PSRAM Address AMSS SST34HF32A4
FIGURE PSRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
ADDRESS A20-0 BEF# TCLZ DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
1313 F04.0
DQ15-0
HIGH-Z
FIGURE Flash Read Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
ADDRESS A20-0 BEF# TCS? RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
1313 F05.0
ADDR
TWPH
FIGURE Flash Controlled Program Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
ADDRESS A20-0 BEF# TCS? RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID TCPH ADDR
1313 F06.0
FIGURE Flash BEF# Controlled Program Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
ADDRESS A20-0 BEF# TOEH RY/BY# DATA DATA# DATA# DATA
1313 F07.0
TOES
FIGURE Flash Data# Polling Timing Diagram Word Mode (For Byte Mode Address Input)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
ADDRESS A20-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS
VALID DATA
1313 F08.0
FIGURE Flash Toggle Timing Diagram Word Mode (For Byte Mode Don't Care)
SIX-BYTE CODE CHIP-ERASE ADDRESS A20-0
TSCE
BEF#
RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID
1313 F09.0
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 17.) VIH, other value.
FIGURE Flash Controlled Chip-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
SIX-BYTE CODE BLOCK-ERASE ADDRESS A20-0 BEF# RY/BY# XXAA DQ15-0 XX55 XX80 XXAA XX55 XX30
VALID
1313 F10.0
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 17.) Block Address VIH, other value.
FIGURE Flash Controlled Block-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
SIX-BYTE CODE SECTOR-ERASE ADDRESS A20-0 BEF# RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50
VALID
1313 F11.0
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 17.) Sector Address VIH, other value.
FIGURE Flash Controlled Sector-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Three-Byte Sequence Software Entry 0000 0001
ADDRESS A20-0
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
1313 F12.0
TIDA
Note: VIH, other value. Device 7353H SST34HF32A4
FIGURE Flash Software Entry Read (For Byte Mode
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESSES
TWPH DQ15-0 XXAA XX55 XX98
1313 F24.0
TIDA
Note: VIH, other value.
FIGURE Entry Read
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
RY/BY# RST#
BEF#/OE# TRHR
1313 F13.0
FIGURE RST# Timing (when internal operation progress)
RY/BY#
RST# BEF#
1313 F14.0
FIGURE RST# Timing (during Sector- Block-Erase operation)
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
VIHT INPUT? VILT
1313 F15.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1313 F16.0
FIGURE Test Load Example
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait Program (TBP,? Data# Polling bit, Toggle operation) Program Completed
1313 F17.0
Note: VIH, other value.
FIGURE Program Algorithm
©2006 Silicon Storage Technology, Inc.
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2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte/word
Read
Program/Erase Completed
Read same byte/word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1313 F18.0
FIGURE Wait Options
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Software Product Entry Command Sequence
Query Entry Command Sequence Load data: XXAAH Address: 555H
Software Exit/ Exit Command Sequence
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address: 555H
Load data: XX98H Address: 555H
Load data: XXF0H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read Software
Read data
Return normal operation
1313 F19.0
Note: VIH, other value.
FIGURE Software Product ID/CFI Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Query Entry Command Sequence
Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address:
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Wait TIDA
Load data: XX88H Address: 555H
Load data: XXF0H Address: 555H
Return normal operation
Wait TIDA
Wait TIDA
Read
Return normal operation
VIH, other value
1313 F20.0
FIGURE Software ID/CFI Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX50H Address:
Load data: XX30H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
Note: VIH, other value.
1313 F21.0
FIGURE Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 XXXX Environmental Attribute non-Pb Package Modifier balls Package Type LFBGA (8mm 10mm 1.4mm, 0.45mm ball size) Temperature Range Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Version blank PSRAM Boot Block Protection Boot Block PSRAM Density Mbit Flash Density Mbit Voltage 2.7-3.3V Product Series Concurrent SuperFlash PSRAM ComboMemory
SST34HF32x4X-
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
Advance Information Valid combinations SST34HF32A4 SST34HF32A4-70-4E-L1PE SST34HF32A4-70-4E-LSE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
PACKAGING DIAGRAMS
VIEW
10.00 0.20
BOTTOM VIEW
5.60 0.80
0.80 CORNER 1.30 0.10 8.00 0.20 5.60
0.45 0.05 (56X) CORNER
SIDE VIEW
SEATING PLANE 0.35 0.05 Note:
0.12
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 56-lfbga-L1P-8x10-450mic-4
FIGURE 56-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 10mm Package Code:
©2006 Silicon Storage Technology, Inc.
S71313-00-000
2/06
Mbit Concurrent SuperFlash Mbit PSRAM ComboMemory SST34HF32A4
VIEW
10.00 0.20
BOTTOM VIEW
7.20 0.80
0.80 CORNER 8.00 0.20 5.60
0.40 0.05 (62X) CORNER
SIDE VIEW
1.30 0.10
0.12 SEATING PLANE 0.32 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 62-lfbga-LS-8x10-400mic-4 Ball opening size 0.32 0.05
FIGURE 62-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 10mm Package Code: TABLE Revision History
Number Description Date 2006
Initial Release
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2006 Silicon Storage Technology, Inc. S71313-00-000 2/06

SST34HF32A4 SST34HF32x4x32Mb 4/8/16 SRAM (x16) ComboMemory F

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