PALCE20V8 Family CMOS 24-Pin Universal Programmable Array Logic

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PALCE20V8 Family CMOS 24-Pin Universal Programmable Array Logic

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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
function compatible with
Advanced Micro Devices
Peripheral Component Interconnect (PCI)
20V8/As Electrically erasable CMOS technology provides reconfigurable logic full testability High-speed CMOS technology 5-ns propagation delay "-5" version 7.5-ns propagation delay "-7" version Direct plug-in replacement wide range 24-pin devices Programmable enable/disable control Outputs individually programmable registered combinatorial
compliant
Preloadable output registers testability Automatic register reset power-up Cost-effective 24-pin plastic SKINNYDIP
28-pin PLCC packages
Extensive third-party software programmer
support through FusionPLD partners
Fully tested 100% programming func-
tional yields high reliability
Programmable output polarity 5-ns version utilizes split leadframe
improved performance
GENERAL DESCRIPTION
PALCE20V8 advanced device built with low-power, high-speed, electrically-erasable CMOS technology. macrocells provide universal device architecture. PALCE20V8 fully compatible with GAL20V8 directly replace PAL20R8 series devices most 24-pin combinatorial devices. Device logic automatically configured according user's design specification. design implemented using number popular design software packages, allowing automatic creation programming file based Boolean state equations. Design software also verifies design provide test vectors finished device. Programming accomplished standard device programmers. PALCE20V8 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floatinggate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with active-high active-low output. output configuration determined global bits local controlling four multiplexers each macrocell.
BLOCK DIAGRAM
CLK/I0
Programmable Array
Input Mux.
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
Input Mux.
OE/I11
Publication# 16491 Rev. Issue Date: February 1996
I/O0
I/O1
I/O2
I/O4
I/O4
I/O5
I/O6
I/O7
16491D-1
Amendment
2-155
CONNECTION DIAGRAMS (Top View) SKINNYDIP
CLK/I0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I11
16491D-2
PLCC/LCC
CLK/I0 I/O7 OE/I11 I/O0
16491D-3
I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
Note: marked orientation.
DESIGNATIONS
Clock Ground Input Input/Output Connect Output Enable Supply Voltage
2-156
PALCE20V8 Family
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER FLIP-FLOPS POWER Half Power (90-125 ICC) Quarter Power ICC) SPEED
PROGRAMMING DESIGNATOR Blank Initial Algorithm First Revision Second Revision (Same algorithm OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C)
PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE20V8H-5 PALCE20V8H-7 Blank, PALCE20V8H-10 PALCE20V8Q-10 PALCE20V8H-15 PALCE20V8Q-15 Blank, PALCE20V8Q-20 PALCE20V8H-25 PALCE20V8Q-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com'l) PALCE20V8H-15/25, Q-20/25 (Ind)
2-157
FUNCTIONAL DESCRIPTION
PALCE20V8 universal device. eight independently configurable macrocells (MC0.MC7). Each macrocell configured registered output, combinatorial output, combinatorial I/O, dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE) flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALCE20V8 automatically configured from user's design specification, which number formats. design
specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function. user given design options with PALCE20V8. First, programmed emulated device. This includes PAL20R8 series most 24-pin combinatorial devices. device programmer manufacturer will supply device codes standard architectures used with PALCE20V8. programmer will program PALCE20V8 corresponding device architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed directly PALCE20V8. Here user must PALCE20V8 device code. This option provides full utilization macrocells, allowing non-standard architectures built.
Adjacent Macrocell
SL0X SL1X *SG1 SL0X I/OX
From Adjacent
16491D-4
Macrocells MC7, replaced feedback multiplexer.
Figure PALCE20V8 Macrocell
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PALCE20V8 Family
Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, buffer always disabled. macrocell configured dedicated input derives input signal from adjacent I/O. macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALCE20V8 will emulate PAL20R8 family combinatorial device. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell SL1x sets output either active active high. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7, replaces feedback multiplexer. These configurations summarized table illustrated figure PALCE20V8 configured combinatorial device, pins available inputs array. device configured with registers, pins cannot used data inputs.
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception pins 18(21) 19(23). Pins 18(21) 19(23) feedback this mode.
Dedicated Input Non-Registered Device
control settings SL0x output buffer disabled. feedback signal adjacent pin.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input.
Combinatorial Registered Device
control settings SG0=0,SG1=1 SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal. Table Macrocell Configurations
SL0x Cell Configuration Devices Emulated Device registers Registered Output Combinatorial PAL20R8, 20R6, 20R4 PAL20R6, 20R4
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. SL1x input exclusive-OR gate which input flipflop. SL1x programmed inverted output non-inverted output. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled
Device registers Combinatorial Output Dedicated Input Combinatorial PAL20L2, 18L4,16L6,14L8 PAL20L2,18L4, 16L6 PAL20L8
Combinatorial Configurations
PALCE20V8 three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection made through programmable SL1x which controls exclusive-OR gate output AND/OR logic. output active high SL1x active SL1x PALCE20V8 Family 2-159
Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Note
Note
Combinatorial Output Active
Combinatorial Output Active High
Notes: Feedback available pins (21) (23) combinatorial output mode. This macrocell configuration available pins (21) (23).
Note
Adjacent
Dedicated Input Figure Macrocell Configurations 2-160 PALCE20V8 Family
16491D-5
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE20V8 depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Programming Erasing
PALCE20V8 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability
PALCE20V8 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming post-programming functional yields industry.
Register Preload
register PALCE20V8 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE20V8H fabricated with AMD's advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
Security
security provided PALCE20V8 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback verification programmed pattern device programmer, securing proprietary designs from competitors. only erased conjunction with array during erase cycle.
Compliance
PALCE20V8H-7/10 fully compliant with Local Specification published Special Interest Group. PALCE20V8H-7/10's predictable timing ensures compliance with specifications independent design. other hand, CPLD FPGA architectures without predictable timing, compliance dependent upon routing product term distribution.
Electronic Signature Word
electronic signature word provided PALCE20V8. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
PALCE20V8 Family
2-161
LOGIC DIAGRAM SKINNYDIP (PLCC LCC) Pinouts
CLK/I0
(28) (27)
I/O7 (26)
SL07
SL06
I/O6 (25)
SL06
SL05
I/O5 (24)
SL05
SL04
I/O4 (23)
SL04
16491D-6
2-162
PALCE20V8 Family
LOGIC DIAGRAM (continued) SKINNYDIP (PLCC LCC) Pinouts
SL03
I/O3 (21)
SL02
I/O2 (20)
(10)
SL02
SL01
(19)
(11)
SL01
SL00
I/O0 (18)
(12)
SL00
(13)
(17) OE/I11 (16)
16491D-6 (concluded)
PALCE20V8 Family
2-163
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE20V8H-15/25 Q-15/25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol fMAX tPZX tPXZ Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 45.5 62.5 41.6 Unit
Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE20V8H-15/25 Q-15/25 (Com'l)
2-173
SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
16491D-7
Clock
Registered Output
16491D-8
Combinatorial Output
Registered Output
Clock
16491D-9
Input Output 0.5V 0.5V
16491D-10
Clock Width
Input Output Disable/Enable
tPXZ Output 0.5V 0.5V tPZX
16491D-11
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times typical.
2-176
PALCE20V8 Family
SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output
Switching Test Circuit
Commercial Specification tPD, tPZX, tPXZ, Closed Open Closed Open Closed
16491D-12
Measured Output Value
H-5:
PALCE20V8 Family
2-177
TYPICAL CHARACTERISTICS 25°C
20V8H-5
20V8H-7 (mA) 20V8H-10 20V8H-15/25
20V8Q-10 20V8Q-15/25
16491D-13
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
2-178
PALCE20V8 Family
ENDURANCE CHARACTERISTICS
PALCE20V8 manufactured using AMD's advanced electrically erasable process. This technology
uses cell replace fuse link used bipolar parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions Unit Years Years Cycles
PALCE20V8 Family
2-179
POWER-UP RESET
PALCE20V8 been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below.
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width
synchronous operation power-up reset wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000 Switching Characteristics Unit
Power
Registered Output
Clock
16491D-16
Power-Up Reset Waveforms
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PALCE20V8 Family

PALCE20V8 Family CMOS 24-Pin Universal Programmable Array Logic

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