SLES160 NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICR

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SLES160 NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICR

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PCM3052A
SLES160 NOVEMBER 2005
24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER,
FEATURES
Microphone Amplifier Bias Monaural Microphone Amplifier: 34-dB Gain Differential Input Microphone Bias: 3.75 Multiplexer Multiplex Stereo Single-Ended Line Inputs Monaural Microphone Amplifier Vrms Vrms Full-Scale Input Range 22-k Input Resistance 0.1-Vrms Input dB/range, dB/step Reference Output: 24-Bit Delta-Sigma Stereo ADC: Full-Scale Input: Vp-p Antialiasing Filter Included 1/64 Decimation Filter: Pass-Band Ripple: ±0.05 Stop-Band Attenuation: On-Chip High-Pass Filter: 0.91 High Performance: THD+N: (Typical) SNR: (Typical) Dynamic Range: (Typical) Stereo DAC: Single-Ended Voltage Output: Vp-p Analog Low-Pass Filter Included Oversampling Digital Filter: Pass-Band Ripple: ±0.03 Stop-Band Attenuation: High Performance: THD+N: (Typical) SNR: (Typical) Dynamic Range: (Typical) S/PDIF Output Digital Input
Multiple Functions With Interface: Digital De-Emphasis: 32-, 44.1-, 48-kHz Zipper-Noise-Free Digital Attenuation Soft Mute Bypass Control S/PDIF Output Control Power Down: ADC/DAC Independently External Power-Down Pin: ADC/DAC Simultaneously Audio Data Format: 24-Bit Only Sampling Rate: 16-96 Both System Clock: Only Dual Power Supplies: Analog Digital Package: VQFN-32
DESCRIPTION
PCM3052A low-cost, single-chip, 24-bit stereo audio codec (ADC DAC) with single-ended analog voltage input output. also analog front consisting 34-dB microphone amplifier, microphone bias generator, stereo multiplexers, wide-range PGA. Analogto-digital converters (ADCs) employ delta-sigma modulation with 64-times oversampling. other hand, digital-to-analog converters (DACs) employ modulation with 128-times oversampling. ADCs include digital decimation filter with high-pass filter, DACs include 8-times oversampling digital interpolation filter. PCM3052A many functions which controlled using interface: digital de-emphasis, digital attenuation, soft mute etc. PCM3052A also S/PDIF output digital input. power-down mode, which works ADCs DACs simultaneously, provided external pin. PCM3052A suitable wide variety cost-sensitive audio (recorder player) applications where good performance required. PCM3052A fabricated using highly advanced CMOS process available small 32-pin VQFN package.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. System Two, Audio Precision trademarks Audio Precision, Inc. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
PCM3052A
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SLES160 NOVEMBER 2005
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
PCM3052A Supply voltage Supply voltage differences Ground voltage differences Digital input voltage Analog input voltage VCC1, VCC2, VCC3 VCC1, VCC2, VCC3 AGND1, AGND2, AGND3, DGND PDWN, DIN, SCKI, SDA, SCL, ADR, I2CEN DOUT, LRCK, BCK, DOUTS VINL, VINR, VREF1, VREF2, REFO, ATEST, L/M, VOUTR, VOUTL, VCOM, MINP, MINM, MBIAS -0.3 -0.3 ±0.1 ±0.1 -0.3 (VDD -0.3 (VCC -40°C 125°C -55°C 150°C 150°C 260°C, 260°C
Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (reflow, peak)
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Digital supply voltage Analog supply voltage Digital input logic family System clock Sampling clock Line input, full scale, Microphone input, full scale, 3.75 compatible Vp-p mVp-p UNIT
Digital input clock frequency Analog input voltage Digital output load capacitance Line output load resistance Line output load capacitance
Microphone bias output load resistance Reference output load resistance Operating free-air temperature
PCM3052A
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ELECTRICAL CHARACTERISTICS
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted
PARAMETER DIGITAL INPUT/OUTPUT DATA FORMAT Audio data interface format Audio data length Audio data format Sampling frequency, Sampling frequency, System clock frequency INPUT LOGIC
TEST CONDITIONS
UNIT
Bits
MSB-first, complement IOUT 0.75 VCC1 0.15 0.75 VCC1 0.15 Hz-20 kHz, with 10-µF decoupling VCC1 0.15
Input logic level Input logic level Input logic current Input logic current
VIL(2) IIH(2)
IIH(1)(3) IIL(1)
OUTPUT LOGIC IOUT IOUT -0.3 IOUT Input level Gain Input resistance Frequency response THD+N MICROPHONE BIAS GENERATOR Output voltage Output source current Output impedance Output noise voltage REFERENCE OUTPUT Output voltage Output source/sink current Output impedance Output noise voltage Hz-20 kHz, with 10-µF decoupling IOUT VCC1 VCC1 0.15 µVrms IOUT 0.75 VCC1 µVrms Single-ended Single-ended Single-ended 1-kHz, 100-mVrms output 1-kHz, 1-Vrms output
Output logic level
MICROPHONE AMPLIFIER mVrms
Pins LRCK, (Schmitt-trigger input with 50-k typical internal pulldown resistor) Pins DIN, SCKI, SDA, SCL, I2CEN (Schmitt-trigger input, tolerant) Pins PDWN, (Schmitt-trigger input with 50-k typical internal pulldown resistor, tolerant). Pins DOUT, DOUTS (Open-drain output)
PCM3052A
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ELECTRICAL CHARACTERISTICS (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted
PARAMETER MULTIPLEXER Input channel Input range full scale Input Impedance Antialiasing filter frequency response Input center voltage (VREF1) Gain range Gain step Monotonicity CHARACTERISTICS Resolution Full-scale input voltage Accuracy Gain mismatch, channe-to-channel Gain error Bipolar-zero error Dynamic Performance
TEST CONDITIONS
UNIT
VINL, VINR VINL, VINR gain
VCC1
Vrms
Ensured
Bits Vp-p
VINL, VINR gain Full scale input, VINL, VINR Full scale input, VINL, VINR bypass, VINL, VINR kHz, -0.5
VCC1 0.454 0.583 ±0.05
THD+N
Total harmonic distortion noise
kHz, -0.5 kHz, kHz, kHz, A-weighted kHz, A-weighted kHz, A-weighted kHz, A-weighted ±0.05
Dynamic range Signal-to-noise ratio Channel separation (between L-ch R-ch line-in) Channel separation (between microphone line-in) Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time frequency response CHARACTERISTICS Resolution Accuracy Gain mismatch, channel-to-channel Gain error Bipolar zero error
Bits
0.583
17.4/fS 0.019
kHz, using System Twoaudio measurement system Audio Precisionin mode with 20-kHz 400-Hz calculation, gain VINL VINR.
PCM3052A
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SLES160 NOVEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted
PARAMETER Dynamic Performance
TEST CONDITIONS kHz, VOUT
UNIT
THD+N
Total harmonic distortion noise
kHz, VOUT kHz, VOUT kHz, VOUT kHz, EIAJ, A-weighted kHz, EIAJ, A-weighted kHz, EIAJ, A-weighted kHz, EIAJ, A-weighted
Dynamic range Signal-to-noise ratio Channel separation Analog Output Output voltage Center voltage Load impedance frequency response Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time De-emphasis error POWER SUPPLY REQUIREMENTS VCC1 VCC2 VCC3
VCC2 VCC2
Vp-p
coupling ±0.03
-0.03 -0.20 0.454 0.546 ±0.03
0.546
20/fS ±0.1
Voltage range
4.25
Supply current
Full power down
(10)
Full power down (10) Operation, Operation, Power dissipation operation kHz/DAC power down power down/DAC operation Full power down (10)
fOUT kHz, using System audio measurement system Audio Precision mode with 20-kHz 400-Hz HPF. ICC1 ICC2 ICC3 (10) Halt SCKI, BCK, LRCK.
PCM3052A
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ELECTRICAL CHARACTERISTICS (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted
PARAMETER TEMPERATURE RANGE Operation temperature Thermal resistance °C/W TEST CONDITIONS UNIT
DEVICE INFORMATION
BLOCK DIAGRAM
VINL
Single-Ended
Delta-Sigma Modulator BCLK Decimation Filter with Audio Data Interface LRCK DOUT DOUTS
VREF1 VREF2 REFO
Reference Buffer
VINR
Single-Ended
Delta-Sigma Modulator PDWN
ATEST MBIAS MINM MINP Bias Clock Timing Generator, Power Control SCKI
VOUTL
Analog Buffer
Multilevel Delta-Sigma Modulator Oversampling Interpolation Filter Mode Control Interface
I2CEN
VCOM Analog Buffer Multilevel Delta-Sigma Modulator
VOUTR
Power Supply
AGND3
VCC3
AGND2
VCC2
AGND1
VCC1
DGND
B0085-01
PCM3052A
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SLES160 NOVEMBER 2005
DEVICE INFORMATION (continued) ASSIGNMENTS
PACKAGE (TOP VIEW)
VOUTR
AGND2
VCC2
I2CEN
VOUTL
VCOM MBIAS MINM MINP AGND3 VCC3 REFO
SCKI
DGND DOUTS DOUT LRCK
AGND1
ATEST
PDWN
VREF1
VREF2
VINR
VINL
VCC1
P0036-01
TERMINAL FUNCTIONS
TERMINAL NAME AGND1 AGND2 AGND3 ATEST DGND DOUT DOUTS I2CEN LRCK MBIAS MINM MINP PDWN REFO DESCRIPTION Mode control address select input analog ground analog ground Microphone amplifier bias analog ground Analog test, must open Digital ground Audio data clock input Audio data digital input
Audio data digital output S/PDIF data digital output Mode control enable/disable input, active HIGH line/microphone select indicator Audio data latch enable input
Microphone bias output/decoupling, 0.75 VCC1 Microphone amplifier input ADC, inverting Microphone amplifier input ADC, non-inverting power down control input, active Reference output decoupling, VCC1
Schimtt-trigger input with 50-k typical internal pulldown resistor, tolerant Schimtt-trigger input with 50-k typical internal pulldown resistor Schimtt-trigger input, tolerant
PCM3052A
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL NAME SCKI VCC1 VCC2 VCC3 VCOM VINL VINR VOUTL VOUTR VREF1 VREF2 DESCRIPTION System clock input, Mode control clock input
Mode control data input/output analog power supply, analog power supply,
Microphone amplifier bias analog power supply, common voltage decoupling, VCC2 Digital power supply, Line input ADC, L-channel Line input ADC, R-channel Analog output from DAC, L-channel Analog output from DAC, R-channel reference voltage output, VCC1 reference voltage decoupling, VCC1
Schimtt-trigger input/open-drain output, tolerant
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (ADC SECTION)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
DIGITAL FILTER
OVERALL CHARACTERISTICS
STOP-BAND ATTENUATION CHARACTERISTICS
Amplitude Amplitude
G001
-100
-150
-200 Normalized Frequency
-100
G002
Normalized Frequency
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (ADC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
PASS-BAND RIPPLE CHARACTERISTICS
Amplitude -1.0 0.45 -4.13
TRANSITION BAND CHARACTERISTICS
Amplitude
-0.2
-0.4
-0.6
-0.8
G003
0.47
0.49
0.51
0.53
0.55
G004
Normalized Frequency
Normalized Frequency
Figure HIGH-PASS FILTER STOP-BAND CHARACTERISTICS
Amplitude -100 -1.0
G005
Figure HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
Amplitude
-0.2
-0.4
-0.6
-0.8
G006
Normalized Frequency
Normalized Frequency
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (ADC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
ANALOG FILTER (Line Input, Gain
ANTIALIASING FILTER STOP-BAND CHARACTERISTICS
ANTIALIASING FILTER PASS-BAND CHARACTERISTICS
f-3dB Amplitude Amplitude Frequency
G007
-0.2
-0.4
-0.6
-0.8
-1.0
Frequency
G008
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (DAC SECTION)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
DIGITAL FILTER
FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff)
Amplitude -100 -120 -140 Frequency
G009
FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff)
Amplitude
-0.2
-0.4
-0.6
-0.8
-1.0
G010
Frequency
Figure DE-EMPHASIS kHz)
Level Error
G011
Figure DE-EMPHASIS ERROR kHz)
-0.1 -0.2 -0.3 -0.4 -0.5
G012
Frequency
Frequency
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (DAC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
DE-EMPHASIS 44.1 kHz)
Level Error
G013
DE-EMPHASIS ERROR 44.1 kHz)
-0.1 -0.2 -0.3 -0.4 -0.5
G014
Frequency
Frequency
Figure DE-EMPHASIS kHz)
Level Error
G015
Figure DE-EMPHASIS ERROR kHz)
-0.1 -0.2 -0.3 -0.4 -0.5
G016
Frequency
Frequency
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES INTERNAL FILTER (DAC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 256fS, 24-bit data, unless otherwise noted.
ANALOG FILTER
STOP-BAND CHARACTERISTICS kHz-10 MHz)
PASS-BAND CHARACTERISTICS (100 Hz-1 MHz)
f-3dB Amplitude Amplitude Frequency
G017
-0.2
-0.4
-0.6
-0.8
-1.0
Frequency
G018
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES (ADC SECTION)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
LINE INPUT Gain
THD+N TEMPERATURE
THD+N Total Harmonic Distortion Noise -0.5
DYNAMIC RANGE TEMPERATURE
Dynamic Range
Dynamic Range
-100
G019
G020
Free-Air Temperature
Free-Air Temperature
Figure THD+N SUPPLY VOLTAGE
THD+N Total Harmonic Distortion Noise -0.5
Figure DYNAMIC RANGE SUPPLY VOLTAGE
Dynamic Range
Dynamic Range
-100 4.25
4.50
4.75
5.00
5.25
5.50
G021
4.25
4.50
4.75
5.00
5.25
5.50
G022
Supply Voltage
Supply Voltage
Figure
Figure
PCM3052A
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TYPICAL PERFORMANCE CURVES (ADC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
THD+N SAMPLING FREQUENCY
THD+N Total Harmonic Distortion Noise -0.5
DYNAMIC RANGE SAMPLING FREQUENCY
Dynamic Range
Dynamic Range
-100
G023
G024
Sampling Frequency
Sampling Frequency
Figure
Figure
PCM3052A
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SLES160 NOVEMBER 2005
TYPICAL PERFORMANCE CURVES (DAC SECTION)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
THD+N TEMPERATURE
THD+N Total Harmonic Distortion Noise
DYNAMIC RANGE TEMPERATURE
Dynamic Range
Dynamic Range
-100
-105
G025
G026
Free-Air Temperature
Free-Air Temperature
Figure THD+N SUPPLY VOLTAGE
THD+N Total Harmonic Distortion Noise
Figure DYNAMIC RANGE TEMPERATURE
Dynamic Range
Dynamic Range
-100
-105 4.25
4.50
4.75
5.00
5.25
5.50
G027
4.25
4.50
4.75
5.00
5.25
5.50
G028
Supply Voltage
Supply Voltage
Figure
Figure
PCM3052A
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TYPICAL PERFORMANCE CURVES (DAC SECTION) (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
THD+N SAMPLING FREQUENCY
THD+N Total Harmonic Distortion Noise
DYNAMIC RANGE SAMPLING FREQUENCY
Dynamic Range
Dynamic Range
-100
-105
G029
G030
Sampling Frequency
Sampling Frequency
Figure
Figure
PCM3052A
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TYPICAL PERFORMANCE CURVES
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
OUTPUT SPECTRUM (Line Input, Gain
OUTPUT SPECTRUM (-0.5 8192)
Amplitude -100 -120 -140 Frequency
G031
OUTPUT SPECTRUM (-60 8192)
Amplitude -100 -120 -140
Frequency
G032
Figure
Figure
OUTPUT SPECTRUM
OUTPUT SPECTRUM 8192)
Amplitude -100 -120 -140 Frequency
G033
OUTPUT SPECTRUM (-60 8192)
Amplitude -100 -120 -140
Frequency
G034
Figure
Figure
PCM3052A
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TYPICAL PERFORMANCE CURVES (continued)
specifications 25°C, VCC1 VCC2 VCC3 kHz, SCKI 24-bit data, unless otherwise noted.
SUPPLY CURRENT
SUPPLY CURRENT TEMPERATURE
Supply Current ICC1 ICC2 ICC3 Supply Current
G035
SUPPLY CURRENT SAMPLING FREQUENCY, OPERATING
ICC1 ICC2 ICC3
G036
Free-Air Temperature
Sampling Frequency
Figure SUPPLY CURRENT SUPPLY VOLTAGE
Supply Current Supply Current 4.25
Figure SUPPLY CURRENT SUPPLY VOLTAGE
ICC1 ICC2 ICC3
Supply Voltage
G037
4.50
4.75
5.00
5.25
5.50
G038
Supply Voltage
Figure
Figure
PCM3052A
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THEORY OPERATION SECTION
block consists reference circuit, channels single-ended differential converter, fifth-order delta-sigma modulator with fully differential architecture, decimation filter with high-pass filter, serial interface circuit which also used serial interface input signal shown block diagram. Figure block diagram fifth-order delta-sigma modulator transfer function. on-chip reference circuit with external capacitors provides reference voltages that needed section, defines full-scale voltage range both channels. on-chip, single-ended differential signal converter saves design, space, extra parts cost external signal converter. Full differential architecture provides wide dynamic range excellent power supply rejection performance. input signal sampled oversampling rate on-chip antialiasing filter eliminates need external sample-hold amplifier. fifth-order delta-sigma noise shaper, which consists five integrators using switched-capacitor technique comparator, shapes quantization noise generated outside audio signal band comparator 1-bit DAC. high-order delta-sigma modulation randomizes modulator outputs reduces idle-tone level. 1-bit stream from delta-sigma modulator converted 1-fS, 24-bit digital signal removing high-frequency noise components with decimation filter. component signal removed HPF, output converted time-multiplexed serial signal through serial interface.
Analog X(z)
SW-CAP Integrator
SW-CAP Integrator
SW-CAP Integrator
SW-CAP Integrator
SW-CAP Integrator
Qn(z)
Digital Y(z)
H(z)
Comparator
1-Bit
Y(z) STF(z) X(z) NTF(z) Qn(z) Signal Transfer Function STF(z) H(z) H(z)] Noise Transfer Function NTF(z) H(z)]
B0005-02
Figure Block Diagram Fifth-Order Delta-Sigma Modulator
SECTION
section based delta-sigma modulator, which consists 8-level amplitude quantizer fourth-order noise shaper. This section converts oversampled input data 8-level delta-sigma format. block diagram 8-level delta-sigma modulator shown Figure This 8-level delta-sigma modulator advantage stability clock jitter over typical one-bit (2-level) delta-sigma modulator. combined oversampling rate delta-sigma modulator internal interpolation filter system clocks. theoretical quantization-noise performance 8-level delta-sigma modulator shown Figure
PCM3052A
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THEORY OPERATION (continued)
8-Level Quantizer
B0008-03
Figure 8-Level Delta-Sigma Modulator Block Diagram
Amplitude -100 -120 -140 -160 -180
G039
G040
Sampling Frequency
Dynamic Range
Jitter psP-P
Figure Quantization Noise Spectrum
Figure Clock Jitter
PCM3052A
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THEORY OPERATION (continued) SYSTEM CLOCK
system clock PCM3052A must where audio sampling rate, kHz. Table lists typical system clock frequencies, Figure illustrates system clock timing. Table Typical System Clock
SAMPLING RATE FREQUENCY (fS) LRCK 44.1
tw(SCKH) System Clock tw(SCKL) 1/256
T0005-10
SYSTEM CLOCK FREQUENCY 4.096 8.192 11.2896 12.288 24.576
PARAMETER tw(SCKH) tw(SCKL) System clock pulse duration, HIGH System clock pulse duration,
UNIT
Figure System Clock Timing
POWER SUPPLY EXTERNAL RESET, POWER DOWN
PCM3052A both internal power-on-reset circuit external reset circuit. sequences both resets shown follows. Figure timing chart internal power-on reset. power-on-reset circuits implemented, each VCC1 VDD. Initialization (reset) performed automatically time when VCC1 exceed (typical) (typical), respectively. Internal reset released after 1024 SCKI from power-on-reset release, PCM3052A begins normal operation. VOUTL VOUTR from forced VCOM VCC2) level VCC2 rises. When synchronization between SCKI, BCK, LRCK maintained, VOUTL VOUTR into fade-in sequence. Then VOUTL VOUTR provide outputs corresponding after t(DACDLY1) 2100/fS from power-on-reset release. other hand, DOUT from provides output corresponding VINL VINR after t(ADCDLY1) 4500/fS from power-on-reset release. synchronization maintained, internal reset released, operation kept power-down mode. After resynchronization, goes into fade-in sequence, goes into normal operation after internal initialization. DOUTS provide S/PDIF data after power-on-reset release SPDIF HIGH (see serial control port mode control section). Figure shows timing chart external reset. PDWN (pin initiates external forced reset when PDWN LOW, provides power-down mode, which lowest power-dissipation state PCM3052A. When PDWN transitions from HIGH while SCKI, BCK, LRCK synchronized, VOUTL VOUTR faded forced into VCOM VCC2) level after tDACDLY1 2100/fS. same time internal reset becomes LOW, DOUT becomes ZERO, PCM3052A enters power-down mode. return normal operation, PDWN HIGH. Then power-on reset sequence, Figure performed.
PCM3052A
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DOUTS driven immediately after PDWN asserted recovers about 40/fS following PDWN release. Notes: Large noises generated VOUTL VOUTR power supply turned during normal operation. switch PDWN during fade-in fade-out causes immediate change between fade-in fade-out. Changing mode controls during normal operation degrade analog performance. recommended that mode controls changed through serial control port, that changing stopping clock, switching power supply off, etc., done power-down mode.
VCC1, (VCC1 Typ) (VCC1 Typ)
LRCK, BCK, SCKI
Synchronous Clocks
PDWN 1024 SCKI
Internal Reset
Power Down
Normal Operation
t(DACDLY1), 2100 About 40/fS VOUTL, VOUTR VCOM (0.5 VCC2) t(ADCDLY1), 4500 DOUT ZERO
DOUTS
Disable
Enable S/PDIF HIGH
T0097-01
Figure Output Output Power-On Reset
PCM3052A
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VCC1, VCC2, VCC3,
(VCC1 VCC3 Typ)
LRCK, BCK, SCKI
Synchronous Clocks
Synchronous Clocks
PDWN
1024 SCKI
Internal Reset
Normal Operation
Power Down
Normal Operation
t(DACDLY1), 2100
t(DACDLY1), 2100
VOUTL, VOUTR
VCOM (0.5 VCC2)
VCC2
t(ADCDLY1), 4500
DOUT
ZERO
About 40/fS
DOUTS
T0098-01
Figure Output Output External Reset (PDWN Pin)
PCM3052A
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AUDIO INTERFACE
Digital audio data interfaced PCM3052A LRCK (pin 10), (pin 11), (pin 12), DOUT (pin 13), DOUTS (pin 14). PCM3052A accept 24-bit format only. case AC-3 type output data DOUTS, bits must held LOW. Digital Audio Interface Transmitter (DIT) section this data sheet. Table Audio Data Format
DATA FORMAT 24-bit, MSB-first,
PCM3052A accepts only clocks during clock LRCK. Figure Figure illustrate audio data input/output format timing.
LRCK Left-Channel Right-Channel
DOUT
Sub-Frame
T0016-15
DOUTS Sub-Frame
Sub-Frame
Figure Audio Data Input/Output Format
PCM3052A
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t(LRP) LRCK t(BCL) t(BCH) t(BL) t(BCY) t(DIS) t(DIH) t(LB)
t(BDO) t(LDO)
DOUT
T0021-03
PARAMETER tBCY tBCH tBCL tLRP tDIS tDIH tBDO tLDO pulse cycle time pulse duration, HIGH pulse duration, rising edge LRCK edge LRCK edge rising edge LRCK pulse duration setup time rising edge hold time rising edge DOUT delay time from falling edge DOUT delay time from LRCK edge Rising time signals Falling time signals
UNIT
NOTE: Load capacitance DOUT Rising falling time measured from IN/OUT signal swing.
Figure Audio Data Input/Output Timing
PCM3052A
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
PCM3052A operates with LRCK synchronized system clock slave mode. PCM3052A does need specific phase relationship among LRCK, BCK, system clock, does require synchronization LRCK, BCK, system clock. relationship between system clock LRCK changes more than BCKs during sample period LRCK jitter, etc., internal operation halts within 6/fS, analog output forced VCC2 until re-synchronization system clock LRCK completed then time t(DACDLY2) elapsed. DOUTS also held during same period. Internal operation also halts within 6/fS, digital output forced into ZERO code until re-synchronization system clock LRCK completed then time t(ADCDLY2) elapsed. case changes less than BCKs, re-synchronization does occur previously described analog/digital output control discontinuity does occur. Figure illustrates analog output, digital output, DOUTS output loss synchronization. During undefined data, PCM3052A generate some noise audio signal. Also, transition normal undefined data undefined zero data normal creates discontinuity data analog digital outputs, which could generate some noise audio signal.
Synchronization Lost Resynchronization
State Synchronization
Synchronous
Asynchronous t(DACDLY2) (32/fS)
Undefined Data
Synchronous
Within 6/fS
VCOM (0.5 VCC2) t(ADCDLY2) (32/fS) Normal Data
VOUT
Normal Data
DOUT
Normal Data
Undefined Data
Zero Data
Normal Data
DOUTS
Normal Data
Undefined Data
Normal Data
T0020-07
Figure Output Output Loss Synchronization
MICROPHONE AMPLIFIER MICROPHONE BIAS GENERATOR
PCM3052A built-in, high-performance differential-input microphone amplifier with 34-dB gain, (minimum) input resistance, 59-dB 100-mVrms output. Bandwidth -3-dB attenuation. PCM3052A also low-noise microphone bias generator with 0.75-VCC1 1-mA current-source capability electret microphones. Output impedance external noise reduction. output microphone amplifier line input connected inputs multiplexer. serial control port used control which input multiplexer selects (see Figure 50).
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REFERENCE OUTPUT
PCM3052A reference output (RFFO, supply reference voltage (0.5 VCC1) external components. 10-mA sink/source capability with output impedance.
(0.75 VCC1) MBIAS
MINM Electret Microphone MINP (0.5 VCC1)
S0124-01
REFO
Figure Microphone Amplifier, Microphone Bias Generator, Reference Output
LINE MICROPHONE INPUT SELECT INDICATOR
PCM3052A employs indicator (L/M, show which analog input selected, line microphone. Table Line Microphone Select Indicator
HIGH LINE/MIC SELECT INDICATOR Microphone Line
PCM3052A
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MULTIPLEXER
PCM3052A built-in analog front-end circuit which shown Figure Multiplexer input gain selected mode control serial port, shown Serial Control Port Mode Control section. full-scale input voltage range Vrms Vrms, adjusted adequate level following sections. VINL VINR input resistance maintained above gains. input resistance value each gain calculated Equation IN(kW, typical) (PGA Gain
VINL L-ch LIN+
LIN- VINR R-ch RIN+
RIN- 2-ch
S0125-01
Figure Multiplexer
ANALOG OUTPUTS FROM
PCM3052A independent output channels, VOUTL VOUTR. These unbalanced outputs, each capable driving Vp-p (typical) into ac-coupled load. internal output amplifiers VOUTL VOUTR biased common-mode bipolar zero) voltage, equal VCC2 output amplifiers include continuous-time filter, which helps reduce out-of-band noise energy present outputs noise-shaping characteristics PCM3052A delta-sigma modulators. frequency response this filter shown typical performance curves. itself, this filter adequate attenuate out-of-band noise acceptable level many applications. external low-pass filter required provide sufficient out-of-band noise rejection. Further discussion post-filter circuits provided PCM1742 data sheet (SBAS176).
VCOM OUTPUT
unbuffered common-mode voltage output pin, VCOM (pin 26), brought decoupling purposes. This nominally biased voltage level equal VCC2. This used bias external circuits. Output resistance this (typical).
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
PCM3052A employs S/PDIF output from DOUTS (pin 14). data (I2S format only) from digital data input (DIN, encoded S/PDIF format with preambles according IEC958. S/PDIF output controlled through serial control port. output data type (linear AC-3) also selected through serial control port. output data type AC-3, word length limited bits PCM3052A. Therefore, bits format data must LOW.
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Each after audio sample word assigned PCM3052A follows. Validity bit: User data: Channel status [0]: Channel status [1]: Channel status [2]: Channel status [3:5]: Channel status [6:7]: Channel status [8:15]: Channel status [16:19]: Channel status [20:23]: Channel status [24:27]: Channel status [28:29]: Channel status [30:31]: Channel status [32:35]: Channel status [36:191]: Parity bit: Writable through serial control port Fixed Fixed (consumer use) Writable through serial control port (audio sample word type) Writable through serial control port (copyright flag) Writable through serial control port (additional format information) Fixed (mode Writable through serial control port (category code) Fixed 0000 (source number) Fixed 0000 (channel number) Writable through serial control port (sampling frequency) Writable through serial control port (clock accuracy) Fixed Writable through serial control port (word length) Fixed Even parity preceding data from preamble channel status
S/PDIF output timing shown Figure S/PDIF block starts with preamble after 32/fS from frame where S/PDIF output control becomes HIGH. behavior DOUTS power-on reset, external reset, loss synchronization shown Figure Figure Figure respectively.
Frame Frame Frame Frame
(I2S Format)
L-ch
R-ch
L-ch
R-ch
L-ch
R-ch
S/PDIF Output Control
Disable
Enable
32/fS
DOUTS
Frame
Preamble
Audio Sample Word Validity
User Bits Channel Status
Parity
T0099-01
Figure S/PDIF Output Timing
PCM3052A
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SERIAL CONTROL PORT MODE CONTROL
several built-in functions PCM3052A controlled through format serial-control port, (pin (pin 19). PCM3052A supports serial data transmission protocol standard mode slave device. This protocol explained specification 2.0. Serial control available even during power-down state without system clock, except when MRST I2CEN (pin LOW. Slave Address
PCM3052A seven bits slave address. first bits (MSBs) slave address factory preset 100011. next address byte device select which user-defined (pin 20). maximum PCM3052As connected same time. Each PCM3052A responds when receives slave address. Packet Protocol master device must control packet protocol, which consists start condition, slave address with read/write bit, data write acknowledgement read, stop condition. PCM3052A supports slave receiver function.
Slave Address
DATA
DATA
Start Condition
Write Operation
Transmitter Data Type
R/W: Read Operation Otherwise, Write Operation ACK: Acknowledgement Byte DATA: Bits (Byte) NACK: Acknowledgement bite Slave Address DATA DATA
Stop Condition
Master Device Slave Device Start Condition Write Stop Condition
T0049-04
Figure Basic Framework
PCM3052A
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Write Operation
PCM3052A supports receiver function. master write PCM3052A registers using single multiple accesses. master sends PCM3052A slave address with write bit, register address, data. multiple access required, address that starting register, followed data transferred. When data received properly, index register incremented automatically. When index register reaches 50h, next value 41h. When undefined registers accessed, PCM3052A does send acknowledgement. Figure diagram write operation. register address write data bits MSB-first format.
Transmitter Data Type
Slave Address
Address
Write Data
Write Data
Master Device Slave Device Start Condition ACK: Acknowledge Write Stop Condition
R0002-03
Figure Framework Write Operation
Serial Control Enable/Disable
PCM3052A supports serial control enable/disable function I2CEN (pin avoid unstable start condition. When I2CEN transitions from HIGH, both (pin (pin must HIGH stable (pin must also stable. While I2CEN LOW, write operation disabled. timing chart I2CEN shown Figure
I2CEN Disable Enable
(min)
(min)
SDA/SCL
Don't Care
HIGH Fixed
Don't Care
HIGH
T0100-01
Figure I2CEN Timing Chart
PCM3052A
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TIMING DIAGRAM
Start t(D-HD) t(BUF) t(D-SU) t(SDA-R) Repeated Start t(SDA-F) t(P-SU) Stop
t(SCL-R) t(LOW)
t(RS-HD)
t(S-HD) t(SCL-F)
t(HI)
t(RS-SU)
T0050-01
PARAMETER f(SCL) t(BUF) t(LOW) t(HI) tRS-SU t(S-HD) t(RS-HD) t(D-SU) t(D-HD) t(SCL-R) t(SCL-R1) t(SCL-F) t(SDA-R) t(SDA-F) t(P-SU) clock frequency free time between STOP START condition period clock High period clock Setup time START/repeated START condition Hold time START/repeated START condition Data setup time Data hold time Rise time signal Rise time signal after repeated START condition after acknowledge Fall time signal Rise time signal Fall time signal Setup time STOP condition Capacitive load line Noise margin high level each connected device (including hysteresis)
CONDITIONS Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode
UNIT
1000 1000 1000 1000 1000
Figure Control Interface Timing
MODE CONTROL REGISTERS
User-Programmable Mode Controls PCM3052A several user programmable functions which accessed control registers. registers programmed using serial control port, which previously discussed this data sheet. Table lists available mode control functions, along with their reset default conditions associated register addresses. register shown Table
PCM3052A
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Table User-Programmable Mode Controls
FUNCTION Digital attenuation control, 0.5-dB steps (DAC) Mode control register reset (ADC DAC) System reset (ADC DAC) power-save control (ADC) Power Save Control (DAC) Soft-mute control (DAC) Oversampling rate control (DAC) De-emphasis function control (DAC) De-emphasis sampling rate selection (DAC) Digital filter rolloff control (DAC) Output phase select (DAC) Multiplexer input channel control (ADC) gain control (ADC) bypass control (ADC) output control (DAC) Additional format information (DIT) Copyright flag (DIT) Audio sample word type (DIT) output control (DIT) Category code (DIT) Clock accuracy (DIT) Sampling frequency (DIT) Validity L-channel (DIT) Validity R-channel (DIT) S/PDIF output control (DIT) Word Length (DIT) RESET DEFAULT attenuation Normal operation Normal operation Normal operation Normal operation Mute disabled 64-fS oversampling De-emphasis disabled Sharp rolloff Normal LINE enabled Disabled audio channels without pre-emphasis Asserted Disable General Level 44.1kHz Valid Valid Disabled bits REGISTER BIT(S) AT1[7:0], AT2[7:0] MRST SRST ADPSV DAPSV MUT[2:1] OVR1 DM12 DMF[1:0] FLT0 DREV PG[4:0] DACMSK AFI[5:3] COPY AUDIO DITMSK CAT[15:8] CLK[29:28] SF[27:24] VALIDL VALIDR SPDIF WL[35:32]
Table Register
REGISTER ADDRESS (B8-B14) REGISTER AT17 AT27 MRST DACMSK CAT15 VALIDL AT16 AT26 SRST OVR1 DMF1 CAT14 VALIDR AT15 AT25 ADPSV DMF0 FLT0 AFI5 CAT13 CLK29 SPDIF AT14 AT24 DAPSV DM12 AFI4 CAT12 CLK28 DATA AT13 AT23 AFI3 CAT11 SF27 WL35 AT12 AT22 COPY CAT10 SF26 WL34 AT11 AT21 MUT2 AUDIO CAT9 SF25 WL33 AT10 AT20 MUT1 DREV DITMSK CAT8 SF24 WL32
means reserved test operation future extension, these bits should during regular operation. write values other addresses than those listed table.
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REGISTER DEFINITIONS
REGISTER REGISTER AT17 AT27 AT16 AT26 AT15 AT25 AT14 AT24 AT13 AT23 AT12 AT22 AT11 AT21 AT10 AT20
ATx[7:0]: Digital Attenuation Level Setting (DAC) Where corresponding output VOUTL VOUTR Default value: 1111 1111b
ATX[7:0] 1111 1111b 1111 1110b 1111 1101b 1000 0011b 1000 0010b 1000 0001b 1000 0000b 0000 0000b DECIMAL VALUE ATTENUATION LEVEL SETTING Attenuation. (default) -0.5 -1.0 -62.0 -62.5 -63.0 Mute Mute
Each channel (VOUTL VOUTR) includes digital attenuation function. attenuation level from 0.5-dB steps, also infinite attenuation (mute). attenuation level change from current value target value performed incrementing decrementing small step size every 1/fS time interval during 2048/fS. small step size determined automatically that provide transition attenuation level with characteristic S-shaped curve from current value target value. While attenuation level change sequence progress 2048/fS, processing attenuation level change command ignored, command overwritten into command buffer. last command attenuation level change performed after present attenuation level change sequence finished. attenuation data each channel individually. attenuation level calculated using following formula: Attenuation level (dB) (ATx[7:0]DEC 255) where ATx[7:0]DEC through 255. ATx[7:0]DEC through 128, attenuation infinite attenuation. preceding table shows attenuation levels various settings.
REGISTER MRST SRST ADPSV DAPSV
MRST: Mode Control Register Reset (ADC DAC) Default value:
MRST MRST default value Normal operation (default)
MRST controls mode control register reset. Pop-noise generated. SRST: System Reset (ADC DAC) Default value:
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SRST SRST
Re-synchronization Normal operation (default)
SRST controls system reset. PCM3052A does into power-down state. mode control register reset this control. Also pop-noise generated. ADPSV: Power-Save Control (ADC) Default value:
ADPSV ADPSV Normal operation (default) Power-save mode
ADPSV controls power-save mode. power-save mode, goes into power-down state, data reset, DOUT forced into ZERO immediately. control enabled. DAPSV: Power-Save Control (DAC) Default value:
DAPSV DAPSV Normal operation (default) Power-save mode
DAPSV controls power-save mode. power-save mode, output faded goes into power-down state. control enabled. waiting time more than 2100/fS from power-save-mode assertion required release power-save mode. function available SPDIF even though DAPSV
REGISTER OVR1 MUT2 MUT1
OVR1: Oversampling Rate Control (DAC) Default value:
OVR1 OVR1 oversampling (default) oversampling
OVR1 used control oversampling rate delta-sigma converters. write over this register during normal operation generate noise. MUTx: Soft-Mute Control (DAC) where, corresponding output VOUTL VOUTR Default value:
MUTx MUTx Mute disabled (default) Mute enabled
mute bits, MUT1 MUT2, used enable disable soft-mute function corresponding outputs, VOUTL VOUTR. soft-mute function incorporated into digital attenuators. When mute disabled (MUTx attenuator operate normally. When mute enabled setting MUTx digital attenuator corresponding output decreased from current setting infinite attenuation, attenuator step (0.5 every 8/fS seconds. This provides pop-free muting output. setting MUTx attenuator increased step every 8/fS seconds previously programmed attenuation level.
PCM3052A
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REGISTER
DMF1
DMF0
DM12
DMF[1:0]: Sampling Frequency Selection De-Emphasis Function (DAC) Default value:
DMF[1:0] DE-EMPHASIS SAMPLING RATE SELECTION 44.1 (default) Reserved
DMF[1:0] bits used select sampling frequency used digital de-emphasis function when enabled. DM12: Digital De-Emphasis Function Control (DAC) Default value:
DM12 DM12 De-emphasis disabled (default) De-emphasis enabled
DM12 used enable disable digital de-emphasis function. plots shown Typical Performance Curves section this data sheet.
REGISTER FLT0
FLT0: Digital Filter Rolloff Control (DAC) Default value:
FLT0 FLT0 Sharp rolloff (default) Slow rolloff
FLT0 allows user select digital filter rolloff that best suited their application. filter rolloff selections available: Sharp Slow. filter responses these selections shown Typical Performance Curves section this data sheet.
REGISTER DREV
DREV: Output Phase Select (DAC) Default value:
DREV DREV Normal output (default) Inverted output
DREV used control output analog signal phase control.
PCM3052A
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REGISTER
AML: Multiplexer Input Channel Selection (ADC) Default value:
MULTIPLEXER INPUT CHANNEL SELECTION Line (default) Microphone
selects input channel multiplexer. PG[4:0]: Gain Selection (ADC) Default value: 0100
PG[4:0] 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 Gain Selection Digital mute Digital mute Digital mute PG[4:0] 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Gain Selection (default) Digital mute Digital mute Digital mute Digital mute
PG[4:0] bits control gain adjusting signal level ADC.
REGISTER
BYP: Bypass Control (ADC) Default value:
Normal output, enable (default) Bypass output, disable
controls function; components input offset converted bypass mode.
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REGISTER
DACMSK
AFI5
AFI4
AFI3
DITMSK
COPY AUDIO
DACMSK: Output Control (DAC) Default value:
DACMSK DACMSK Mask disable (default) Mask level
DACMSK used mask level. analog outputs from forced level immediately. Larger noise generated this control. AFI[5:3]: Additional Format Information (DIT) Default value: audio channels without pre-emphasis) AFI[5:3] bits control bits[5:3] channel status bits compliance with IEC958. COPY: Copyright Flag (DIT) Default value: (Asserted) COPY controls bit[2] channel status bits compliance with IEC958. AUDIO: Audio Sample Word Type (DIT) Default value: (PCM) AUDIO controls bit[1] channel status bits compliance with IEC958. DITMSK: Output Control (DIT) Default value:
DITMSK DITMSK Mask disable (default) Force DOUTS encoded ZERO status
DITMSK forces only audio sample words DOUTS encoded ZERO status. validity channel status bits, values register output.
PCM3052A
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REGISTER
CAT15
CAT14
CAT13
CAT12
CAT11
CAT10
CAT9
CAT8
CAT[15:8]: Category Code (DIT) Default value: 0000 0000 (general) CAT[15:8] bits control bits[15:8] channel status bits compliance with IEC958.
REGISTER CLK29 CLK28 SF27 SF26 SF25 SF24
CLK[29:28]: Clock Accuracy (DIT) Default value: (level CLK[29:28] bits control bits[29:28] channel status bits compliance with IEC958. SF[27:24]: Sampling Frequency (DIT) Default value: 0000 (44.1 kHz) SF[27:24] bits control bits[27:24] channel status bits compliance with IEC958.
REGISTER WL35 WL34 WL33 WL32 VALIDL VALIDR SPDIF
VALIDL: Validity L-channel (DIT) Default value: (valid) VALIDL controls validity L-channel compliance with IEC958. VALIDR: Validity R-channel (DIT) Default value: (valid) VALIDR controls validity R-channel compliance with IEC958. SPDIF: S/PDIF Output Control (DIT) Default value:
SPDIF SPDIF DOUTS disabled (default) DOUTS enabled
SPDIF controls output from DOUTS pin. case default, DOUTS always becomes status. WL[35:32]: Word Length (DIT) Default value: 0001 bits) WL[35:32] bits control bits[35:32] channel status bits actual data word length audio sample word including auxiliary 4-bits from DOUTS compliance with IEC958. WL[35:32] bits indicate bits, actual data word length audio sample word limited bits even though data input 24-bits, example.
PCM3052A
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TYPICAL CIRCUIT CONNECTION
Figure illustrates typical circuit connection.
Line Control
Post
VOUTL VOUTR
AGND2 I2CEN SCKI
VCC2
VCOM MBIAS MINM MINP AGND3
PCM3052A
DGND DOUTS DOUT LRCK
System Clock Audio Interface
VCC3 REFO
ATEST
Line
S0126-01
NOTE: 0.1-µF ceramic 10-µF electrolytic capacitors typical, depending power supply quality pattern layout. 0.1-µF ceramic 10-µF electrolytic capacitors recommended. C10: 1-µF non-polar electrolytic capacitors recommended, which give 27-Hz cutoff frequency. C11, C12: 0.22-µF electrolytic capacitors recommended, which give 5-Hz cutoff frequency gain C13, C14: 2.2-µF electrolytic capacitors typical. C15: 10-µF electrolytic capacitor recommended. typical recommended.
Figure Typical Application Diagram
AGND1
PDWN
VINL
VREF1
VREF2
VCC1
VINR
PCM3052A
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DESIGN LAYOUT CONSIDERATIONS APPLICATION
Power Supply Pins (VCC1, VCC2, VCC3, VDD) digital analog power supply lines PCM3052A should bypassed corresponding ground pins with 0.1-µF ceramic 10-µF electrolytic capacitors close pins possible maximize dynamic performance DAC. Although PCM3052A four power lines maximize potential dynamic performance, using common power supply VCC1, VCC2, VCC3. 3.3-V power supply VDD, which generated from power supply VCC1, VCC2, VCC3, recommended avoid unexpected power supply trouble like latch-up power supply sequencing problems. Grounding (AGND1, AGND2, AGND3, DGND) maximize dynamic performance PCM3052A, analog digital grounds connected internally. These points should have impedance avoid digital noise signal components feeding back into analog ground. They should connected directly each other under parts reduce potential noise problems. VINL, VINR Pins 0.22-µF electrolytic capacitor recommended ac-coupling capacitor, which gives 5-Hz cutoff frequency gain higher full-scale input voltage required, adjusted adding only series resistor VINX pins. VREF1, VREF2, VCOM Pins Both 0.1-µF ceramic 10-µF electrolytic capacitors recommended from VREF1 VREF2 AGND1, from VCOM AGND2, ensure source impedance references. These capacitors should located close possible VREF1, VREF2, VCOM pins reduce dynamic errors references. MBIAS 10-µF electrolytic capacitor recommended between MBIAS AGND3 ensure noise MBIAS. REFO Both 0.1-µF ceramic 10-µF electrolytic capacitors recommended between REFO AGND1 ensure noise REFO. MINM, MINP Pins 1-µF non-polar electrolytic capacitor which gives 27-Hz cutoff frequency, recommended coupling capacitor. System Clock quality SCKI influence dynamic performance, PCM3052A (both ADC) operates based SCKI. Therefore, might necessary consider jitter, duty, rise fall time, etc. system clock. External Mute Control power-down ON/OFF control without click noise which generated output level changes, external mute control generally required. control sequence, which described External Mute CODEC Power Down SCKI stop resume necessary, CODEC Power Down OFF, External Mute OFF, recommended.
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device PCM3052ARTF PCM3052ARTFR
Status PREVIEW PREVIEW
Package Type
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

SLES160 NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICR

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