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High Performance 10-Bit Display Interface AD9984A
10-bit, analog-to-digital converters MSPS maximum conversion rate clock jitter MSPS Automatic gain matching Automated offset adjustment input Power-down dedicated serial register 4:4:4, 4:2:2, output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output Programmable output high impedance control Hsyncs Vsync counter Sync-on-green (SOG) pulse filter Pb-free package
AD9984A
AUTO OFFSET AUTO GAIN Pr/REDIN1 Pr/REDIN0 CLAMP 10-BIT AUTO OFFSET AUTO GAIN Y/GREENIN1 Y/GREENIN0 CLAMP 10-BIT AUTO OFFSET AUTO GAIN Pb/BLUEIN1 Pb/BLUEIN0 CLAMP 10-BIT
OUTPUT DATA FORMATTER
Cb/Cr/REDOUT
Y/GREENOUT
Cb/BLUEOUT
HSYNC1 HSYNC0
DATACK SYNC PROCESSING SOGOUT ODD/EVEN FIELD HSOUT VSOUT/A0
VSYNC0 VSYNC1
APPLICATIONS
Advanced Plasma display panels LCDTV HDTV graphics processing monitors projectors Scan converters
SOGIN1 SOGIN0 EXTCK/COAST CLAMP FILT
POWER MANAGEMENT
VOLTAGE REFS SERIAL REGISTER
REFHI REFLO
06476-001
Figure
GENERAL DESCRIPTION
AD9984A complete 10-bit, MSPS, monolithic analog interface optimized capturing YPbPr video graphics signals. MSPS encode rate capability full power analog bandwidth support HDTV video modes 1080p, well graphics resolutions UXGA (1600 1200 Hz). AD9984A includes triple with internal reference, PLL, programmable gain, offset, clamp control. user provides only power supply analog input. Three-state CMOS outputs powered from AD9984A on-chip generates sample clock from tri-level sync (for YPbPr video) horizontal sync (for graphics). Sample clock output frequencies range from MHz. With internal coast generation, maintains output frequency absence sync input. 32-step sampling clock phase adjustment provided. Output data, sync, clock phase relationships maintained. auto-offset feature enabled automatically restore signal reference levels calibrate offset differences between three channels. auto channel-to-channel gainmatching feature enabled minimize gain mismatches between three channels. AD9984A also offers full sync processing composite sync sync-on-green applications. clamp signal generated internally provided user through CLAMP input pin. Fabricated advanced CMOS process, AD9984A provided space-saving, Pb-free, 80-lead profile quad flat package (LQFP) 64-lead lead frame chip scale package (LFCSP) specified over 70°C temperature range.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. rights reserved.
AD9984A TABLE CONTENTS
Features Applications. Functional Block Diagram General Description Revision History Specifications. Analog Interface Characteristics Absolute Maximum Ratings. Explanation Test Levels Thermal Resistance Caution. Configurations Function Descriptions Theory Operation Digital Inputs Analog Input Signal Handling. Hsync Vsync Inputs. Serial Control Port Output Signal Handling. Clamping Gain Offset Control. Sync-on-Green. Reference Bypassing. Clock Generation Sync Processing. Power Management. Timing Diagrams. Hsync Timing Coast Timing. Output Formatter 2-Wire Serial Control Port Data Transfer Serial Interface. 2-Wire Serial Register 2-Wire Serial Control Registers. Chip Identification Divider Control Clock Generator Control Phase Adjust. Input Gain Input Offset Hsync Control. Vsync Control. Coast Clamp Controls. Control Input Power Control. Output Control Sync Processing Detection Status. Polarity Status Hsync Count Test Registers. Layout Recommendations. Analog Interface Inputs Outputs (Both Data Clocks). Digital Inputs Outline Dimensions Ordering Guide
REVISION HISTORY
7/07-Revision Initial Version
Rev. Page
AD9984A SPECIFICATIONS
ANALOG INTERFACE CHARACTERISTICS
DAVDD clock maximum conversion rate, full temperature range 70°C. Table Electrical Characteristics
Test Level AD9984AKSTZ-140 AD9984AKCPZ-140 0.098 25°C Full 25°C Full Full ±0.6 ±2.35 +1.8/-1.0 +1.9/-1.0 ±7.0 ±9.0 AD9984AKSTZ-170 AD9984AKCPZ-170 0.098 ±0.7 ±2.35 GNT2 +1.9/-1.0 +2.0/-1.0 ±8.5 ±9.0
Parameter RESOLUTION Number Bits Size ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Full-Scale Matching Offset Adjustment Range SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Clock Data Skew (tSKEW) tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOSU Maximum Clock Rate Minimum Clock Rate Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, (VIL) Input Current, High (IIH) Input Current, (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, (VOL) Duty Cycle (DATACK) Output Coding
Temp
Unit Bits full scale (FS)
Full Full 25°C 25°C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full Full Full
-0.5 -1.0 Binary Binary +2.0 -0.5
ppm/°C MSPS MSPS ps/°C
+2.0
-1.0
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AD9984A
Parameter POWER SUPPLY Supply Voltage Supply Voltage Supply Voltage DAVDD Supply Voltage Supply Current (ID) Supply Current (IDD) Supply Current (IPVD) DAVDD Supply Current (IDAVDD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Crosstalk
Temp Full Full Full Full 25°C 25°C 25°C 25°C Full Full Full 25°C Full
Test Level
AD9984AKSTZ-140 AD9984AKCPZ-140 3.47
AD9984AKSTZ-170 AD9984AKCPZ-170 1.755 3.47
Unit
Explanation Test Levels section. Guaranteed design, production tested.
Rev. Page
AD9984A ABSOLUTE MAXIMUM RATINGS
Table
Parameter DAVDD Analog Inputs REFHI REFLO Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 1.98 1.98 1.98 -25°C +85°C -65°C +150°C 150°C 150°C
EXPLANATION TEST LEVELS
III. 100% production tested. 100% production tested 25°C sample tested specified temperatures. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested 25°C; guaranteed design characterization testing.
THERMAL RESISTANCE
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. specified worst-case conditions, that device soldered circuit board surface-mount packages. Table Thermal Resistance
Package Type 80-Lead LQFP 64-Lead LFCSP Unit
°C/W °C/W
CAUTION
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AD9984A CONFIGURATIONS FUNCTION DESCRIPTIONS
EXTCK/COAST (1.8V) (1.8V) (1.8V) (3.3V) HSYNC0 HSYNC1 VSYNC0 VSYNC1 BLUE BLUE BLUE CLAMP FILT
(1.8V) BAIN0 BAIN1 (1.8V) GAIN0 SOGIN0 (1.8V)
INDICATOR
BLUE BLUE BLUE BLUE BLUE BLUE BLUE (3.3V) GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN DAVDD (1.8V)
GAIN1 SOGIN1 (1.8V) RAIN0 RAIN1 PWRDN REFLO REFHI
VIEW (Not Scale)
AD9984A
FIELD
VSOUT/A0
SOGOUT
(3.3V)
(3.3V)
HSOUT
DATACK
CONNECT
Figure 80-Lead LQFP Configuration
Rev. Page
06476-002
AD9984A
VSOUT/A0
SOGOUT
DATACK
HSOUT
DAVDD
GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN
INDICATOR
FIELD REFHI REFLO PWRDN RAIN1 RAIN0 SOGIN1 GAIN1 SOGIN0 GAIN0 BAIN1 BAIN0
AD9984A
VIEW (Not Scale)
GREEN BLUE BLUE BLUE BLUE BLUE BLUE
CLAMP
BLUE
BLUE
BLUE
BLUE
EXTCK/COAST
VSYNC1
HSYNC1
HSYNC0
VSYNC0
FILT
Figure 64-Lead LFCSP Configuration
Table Complete Configuration List
Type Inputs Number 80-Lead LQFP 64-Lead LFCSP Mnemonic RAIN0 RAIN1 GAIN0 GAIN1 BAIN0 BAIN1 HSYNC0 HSYNC1 VSYNC0 VSYNC1 SOGIN0 SOGIN1 EXTCK CLAMP COAST1 PWRDN
Function Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Channel Analog Input Converter Horizontal Sync Input Channel Horizontal Sync Input Channel Vertical Sync Input Channel Vertical Sync Input Channel Input Sync-on-Green Channel Input Sync-on-Green Channel External Clock Input External Clamp Input Signal External Coast Signal Input Power-Down Control
06476-020
Value CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Rev. Page
AD9984A
Type Outputs Number 80-Lead LQFP 64-Lead LFCSP Mnemonic RED[9:0] GREEN[9:0] BLUE[9:0] DATACK HSOUT VSOUT SOGOUT FIELD FILT REFLO REFHI DAVDD Function Outputs Converter Outputs Converter Outputs Converter Data Output Clock Hsync Output Clock (Phase-aligned with DATACK) Vsync Output Clock Sync-on-Green Slicer Output Odd/Even Field Output Connection External Filter Components Internal Connection External Capacitor Input Amplifier Connection External Capacitor Input Amplifier Analog Power Supply Output Power Supply Power Supply Digital Logic Power Supply Ground Value CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
References
Power Supply
Control
Serial Port Data Serial Port Data Clock (100 maximum) Serial Port Address Input
CMOS CMOS CMOS
EXTCK COAST share same pin. VSOUT share same pin.
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AD9984A
Table Function Descriptions
Mnemonic RAIN0 GAIN0 BAIN0
RAIN1 GAIN1 BAIN1
HSYNC0 HSYNC1
Function Analog Input Channel Analog Input Green Channel Analog Input Blue Channel Analog Input Channel Analog Input Green Channel Analog Input Blue Channel Horizontal Sync Input Channel Horizontal Sync Input Channel
Description These high impedance inputs accept red, green, blue channel graphics signals, respectively. three channels identical used colors, colors assigned convenient reference. They accommodate input signals ranging from full scale. Signals should ac-coupled these pins support clamp operation. Refer Figure Figure
VSYNC0 VSYNC1
Vertical Sync Input Channel Vertical Sync Input Channel
SOGIN0 SOGIN1
Sync-on-Green Input Channel Sync-on-Green Input Channel
CLAMP
External Clamp Input (Optional)
EXTCK/COAST
External Clock (EXTCK)
Optional Coast Input Clock Generator (COAST)
PWRDN
Power-Down Control (PWRDN) Input Amplifier Reference
REFLO, REFHI
These inputs receive logic signal that establishes horizontal timing reference provides frequency reference pixel clock generation. logic sense these pins automatically determined chip manually controlled Serial Register 0x12, Bits[5:4] (Hsync polarity). Only leading edge Hsync used PLL; trailing edge used clamp timing. When Hsync polarity falling edge Hsync used. When Hsync polarity rising edge active. These inputs include Schmitt trigger noise immunity. These inputs vertical sync provide timing information generation field (odd/even) internal coast generation. logic sense this automatically determined chip manually controlled Serial Register 0x14, Bits[5:4] (Vsync polarity). These inputs help process signals with embedded sync, typically green channel. These pins connect high speed comparator with internally generated threshold. threshold level programmed steps voltage between above negative peak input signal. default voltage threshold When connected ac-coupled graphics signal with embedded sync, noninverting digital output produced SOGOUT. This output usually composite sync signal, containing both vertical horizontal sync information that must separated before passing horizontal sync signal Hsync processing. When used, these inputs should left unconnected. more details about this function should configured, refer Sync-on-Green section. This logic input used define time during which input signal clamped ground midscale. should exercised when reference level known present analog input channels, typically during back porch graphics signal. CLAMP enabled setting control clamp function (Register 0x18, default When disabled, this ignored clamp timing determined internally counting delay duration from trailing edge Hsync input. logic sense this automatically determined chip controlled clamp polarity (Register 0x1B, Bits[7:6]). When used, this left unconnected (there internal pull-down resistor) clamp function programmed This dual functionality. EXTCK allows insertion external clock source rather than internally generated, locked clock. EXTCK enabled programming Register 0x03, This EXTCK function does affect COAST function. COAST used cause pixel clock generator stop synchronizing with Hsync continue produce clock current frequency phase. This useful when processing signals from sources that fail produce Hsync pulses during vertical interval. coast signal generally required PC-generated signals. logic sense this determined automatically controlled coast polarity (Register 0x18, Bits[7:6]). When this function EXTCK function used, this grounded coast polarity programmed Input coast polarity defaults power-up. This COAST function does affect EXTCK function. PWRDN allows manual power-down control. manual power-down control selected (Register 0x1E, 4),and this used, recommended polarity (Register 0x1E, active high hardwire this ground with resistor. REFLO REFHI connected together through capacitor. These used stability input circuitry. Figure
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AD9984A
Mnemonic FILT Function External Filter Connection Description proper operation, pixel clock generator requires external filter. Connect filter shown Figure this pin. optimal performance, minimize noise parasitics this node. more information, Layout Recommendations section. This reconstructed phase-aligned version Hsync input. Both polarity duration this output programmed serial registers. maintaining alignment with DATACK main data outputs (RED[9:0], GREEN[9:0], BLUE[9:0]), data timing with respect Hsync always determined. This dual functionality. VSOUT either separated Vsync from composite signal direct pass through Vsync signal. polarity this output controlled serial bit. placement duration modes graphics transmitter duration Register 0x14, Register 0x15, Bits[7:0]. This VSOUT function does affect function. selects serial port device address, allowing parts from Analog Devices, Inc., same serial bus. high impedance external pull-up resistor enables this read power-up This function does interfere with VSOUT function. more details description 2-Wire Serial Control Port section. This outputs four possible signals (controlled Register 0x1D, Bits[1:0]): SOGINx, HSYNCx, regenerated Hsync from filter, filtered Hsync. Figure view this connected. Other than slicing SOG, output from this receives additional processing AD9984A. Vsync separation performed sync separator. This output identifies whether current field interlaced signal) even. Data I2C® serial port. Clock serial port. main data outputs. MSB. delay from pixel sampling time output fixed. When sampling time changed adjusting phase register, output timing shifted well. DATACK HSOUT outputs also moved maintain timing relationship among signals. This main clock output signal used strobe output data HSOUT into external logic. Four possible output clocks selected with Register 0x20, Bits[7:6]. Three these related pixel clock (pixel clock, phase-shifted pixel clock, frequency pixel clock). They produced internal clock generator EXTCK, synchronous with pixel sampling clock. fourth option data clock output internally generated pixel clock. sampling time internal pixel clock changed adjusting phase register (Register 0x04). When this changed, pixel-related DATACK timing also shifted. data (RED[9:0], GREEN[9:0], BLUE[9:0]), DATACK, HSOUT outputs moved maintain timing relationship among signals. These pins supply power main elements circuit. They should quiet filtered possible. large number output pins switching high speed MHz) generates large amounts power supply transients (noise). These supply pins identified separately from pins. result, special care must taken minimize output noise transferred into sensitive analog circuitry. AD9984A interfacing with lower voltage logic, connected lower supply voltage compatibility. most sensitive portion AD9984A clock generation circuitry. These pins provide power clock help user design optimal performance. designer should provide quiet, noise-free power these pins. This supplies power digital logic. recommended connect this supply. ground return on-chip circuitry. recommended that AD9984A assembled single solid ground plane with careful attention ground current paths.
HSOUT
Horizontal Sync Output
VSOUT/A0
Vertical Sync Output (VSOUT)
Serial Port Address Input (A0)
SOGOUT
Sync-On-Green Slicer Output
FIELD RED[9:0] GREEN[9:0] BLUE[9:0] DATACK
Odd/Even Field Interlaced Video Serial Port Data Serial Port Data Clock Data Output, Channel Data Output, Green Channel Data Output, Blue Channel Data Clock Output
(1.8 (1.8
Main Power Supply Digital Output Power Supply
(1.8
Clock Generator Power Supply Digital Input Power Supply Ground
DAVDD (1.8
Rev. Page
AD9984A THEORY OPERATION
AD9984A fully integrated solution capturing digitizing analog YPbPr signals display advanced TVs, flat panel monitors, projectors, other types digital displays. Implemented high performance CMOS process, interface capture signals with pixel rates MHz. AD9984A includes necessary input buffering, signal restoration (clamping), offset gain (brightness contrast) adjustment, pixel clock generation, sampling phase control, output data formatting. controls programmable 2-wire serial interface (I2C). Full integration these sensitive analog functions makes system design straightforward less sensitive physical electrical environment. With typical power dissipation less than operating temperature range 70°C, device requires special environmental considerations.
INPUT 47nF
06476-003
RAIN GAIN BAIN
Figure Analog Input Interface Circuit
HSYNC VSYNC INPUTS
interface also accepts Hsync Vsync signals, which used generate pixel clock, clamp timing, coast field information. These either sync signal directly from graphics source, preprocessed TTL- CMOSlevel signal. Hsync input includes Schmitt trigger buffer immunity noise signals with long rise times. typical PC-based graphic systems, sync signals simply TTL-level drivers feeding unshielded wires into monitor cable. such, termination required.
DIGITAL INPUTS
digital inputs AD9984A operate CMOS levels. following digital inputs tolerant (that applying them does cause damage): HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, CLAMP.
SERIAL CONTROL PORT
serial control port designed logic; however, tolerant logic signals. Refer 2-Wire Serial Control Port section more information.
ANALOG INPUT SIGNAL HANDLING
AD9984A six, high impedance, analog input pins red, green, blue channels. They accommodate signals ranging from p-p. Signals typically brought onto interface board with DVI-I connector, 15-pin connector, connectors. AD9984A should located close possible input connector. Signals should routed using matchedimpedance traces (normally input pins. input pins, signal should resistively terminated signal ground return) capacitively coupled AD9984A inputs through capacitors. These capacitors form part restoration circuit. ideal world perfectly matched impedances, best performance obtained with widest possible signal bandwidth. wide bandwidth inputs AD9984A (300 MHz) track input signal continuously moves from pixel level next digitize pixel during long, flat pixel time. many systems, however, there mismatches, reflections, noise, which result excessive ringing distortion input waveform. This makes more difficult establish sampling phase that provides good image quality. small inductor series with input shown effective rolling input bandwidth slightly providing high quality signal over wider range conditions. Using high speed, signal chip, bead inductor (such Fair-Rite 2508051217Z0) circuit shown Figure provides good results most applications.
OUTPUT SIGNAL HANDLING
digital outputs operate from (VDD).
CLAMPING
Clamping
properly digitize incoming signal, offset input must adjusted range on-board ADCs. Most graphics systems produce signals with black ground white approximately 0.75 However, sync signals embedded graphics, sync often ground, black white approximately Some common line amplifier boxes emitter-follower buffers split signals increase drive capability. This introduces offset signal, which must removed proper capture AD9984A. clamping identify portion (time) signal when graphic system known producing black. offset then introduced that results producing black output (Code 0x00) when known black input present. offset then remains place when other signal levels processed, entire signal shifted eliminate offset errors. most graphics systems, black transmitted between active video lines. With displays, when electron beam completed writing horizontal line screen right side), beam deflected quickly left side screen (called horizontal retrace) black signal provided prevent beam from disturbing image.
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AD9984A
systems with embedded sync, blacker-than-black signal (Hsync) briefly produced signal that time begin retrace. Because input black level this time, important avoid clamping during Hsync. Fortunately, there usually period following Hsync (called back porch) where good black reference provided. This time when clamping should done. clamp timing established simply exercising CLAMP appropriate time with clamp source (Register 0x18, polarity this signal clamp polarity bits (Register 0x1B, Bits[7:6]). simpler method clamp timing employs AD9984A internal clamp timing generator. clamp placement register (Register 0x19) programmed with number pixel periods that should pass after trailing edge Hsync before clamping starts. second register, clamp duration (Register 0x1A), sets duration clamp. These both 8-bit values, providing considerable flexibility clamp generation. Although Hsync duration widely vary, clamp timing referenced trailing edge Hsync because back porch (black reference) always follows Hsync. effective starting point establishing clamping clamp placement 0x04 (providing pixel periods graphics signal stabilize after sync) clamp duration 0x28 (giving clamp pixel periods reestablish black reference). Clamping accomplished placing appropriate charge external input coupling capacitor. value this capacitor affects performance clamp. small, there significant amplitude change during horizontal line time (between clamping intervals). capacitor large, takes long time clamp recover from large change incoming signal offset. recommended value (100 results recovering from step error within lines with clamp duration pixel periods signal.
GAIN OFFSET CONTROL
AD9984A contains three programmable gain amplifiers (PGAs), each three analog inputs. range sufficient accommodate input signals with inputs ranging from full scale. gain three 9-bit registers, gain (Register 0x05, Register 0x06), green gain (Register 0x07, Register 0x08), blue gain (Register 0x09, Register 0x0A). each register, gain setting corresponds highest gain, while gain setting 511d corresponds lowest gain. Note that increasing gain setting results image with less contrast. offset control shifts analog input, resulting change brightness. Three 11-bit registers, offset (Register 0x0B, Register 0x0C), green offset (Register 0x0D, Register 0x0E), blue offset (Register 0x0F, Register 0x10) provide independent settings each channel. Note that function offset register depends whether auto-offset enabled (Register 0x1B, manual offset used, nine bits offset registers (for channel, Register 0x0B, Bits[6:0] plus Register 0x0C, Bits[7:6]) control absolute offset added channel. offset control provides ±255 LSBs adjustment range, with offset corresponding output code.
Automatic Offset
addition manual offset adjustment mode, AD9984A also includes circuitry automatically calibrate offset each channel. monitoring output each during back porch input signals, AD9984A self-adjust eliminate offset errors channels offset errors present incoming graphics video signals. activate auto-offset mode, Register 0x1B, Next, target code registers (Register 0x0B through Register 0x10) must programmed. values programmed into target code registers should output code desired from AD9984A during back porch reference time. example, signals, three registers normally programmed Code while YPbPr signals, green channel normally programmed Code blue channels normally 512. target code registers have bits channel twos complement format. This allows value between -1024 +1023 programmed. Although value this range programmed, AD9984A offset range able reach every value. Intended target code values range from (but limited -160 +160 when ground clamping, when midscale clamping. Note that target code valid.
YPbPr Clamping
YPbPr graphic signals slightly different from signals that reference level (black level signals) color difference signals midpoint video signal rather than bottom. three inputs composed luminance color difference signals. color difference signals, necessary clamp midscale range range (512) rather than bottom range (0), while channel clamped ground. Clamping midscale rather than ground accomplished setting clamp select bits serial register. Each three converters selection enable them independently clamped midscale ground. These bits located Register 0x18, Bits[3:1]. midscale reference voltage internally generated each converter.
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AD9984A
Negative target codes included duplicate feature that present with manual offset adjustment. benefit that mimicked ability easily adjust brightness display. setting target code value that does correspond ideal range, result image that brighter darker. target code higher than ideal results brighter image, whereas target code lower than ideal results darker image. ability program target code offers large degree freedom flexibility. Although channels either most cases, flexibility select other values makes possible insert intentional skews between channels. also allows range skewed that voltages outside normal range digitized. example, setting target code allows sync tip, which normally below black level, digitized evaluated. internal logic auto-offset circuit requires data clock cycles perform function. This operation executed immediately after clamping pulse. Therefore, important clamping pulse signal least data clock cycles before active video. This true whether using AD9984A internal clamp circuit external CLAMP signal. autooffset function programmed continuously one-time basis (see 0x2C-Bit[4] Auto-Offset Hold section). continuous mode, update frequency programmed (Register 0x1B, Bits[4:3]). Continuous operation with updates every Hsyncs recommended. Guidelines basic auto-offset operation shown Table Table Table Auto-Offset Register Settings
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x18, Bits[3:1] 0x1B, Bits[5:3] Value 0x00 0x80 0x00 0x80 0x00 0x80 Comments Sets target Must written. Sets green target Must written. Sets blue target Must written. Sets red, green, blue channels ground clamp. Selects update rate every clamps enables auto-offset.
Automatic Gain Matching
AD9984A includes circuitry match gains between three channels within each other. Matching gains each channel necessary achieve good color balance display. products without this feature, gain matching achieved writing software that evaluates output each channel, calculates gain mismatches, then writes values gain registers each channel compensate. With auto gain matching function, this software routine longer needed. activate auto gain matching, Register 0x3C, Bits[2:0] 110. Auto gain matching similar timing requirements auto offset. requires data clock cycles perform function, starting immediately after clamp pulse. Unlike auto offset, auto gain matching does require that these clock cycles occur during back porch reference time, although recommended. During auto gain matching operation, data outputs AD9984A frozen (held value they just prior operation). auto gain matching function programmed continuously one-time basis (see 0x3C-Bit[3] Auto Gain Matching Hold section). continuous mode, update frequency programmed (Register 0x1B, Bits[4:3]). Continuous operation with updates every Hsyncs recommended.
SYNC-ON-GREEN
sync-on-green inputs (SOGIN0, SOGIN1) operate steps. First, they baseline clamp level incoming video signal with negative peak detector. Second, they voltage level slicer's comparator (Register 0x1D, Bits[7:3]) with variable trigger level programmable level (typically above negative peak. Each sync-ongreen input must ac-coupled green analog input through capacitor. value capacitor must 20%. sync-on-green used, this connection required. sync-on-green signal always negative polarity.
47nF RAIN 47nF BAIN 47nF GAIN SOGIN
06476-004
06476-005
Table YPbPr Auto-Offset Register Settings
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x18, Bits[3:1] 0x1B, Bits[5:3] Value 0x40 0x00 0x00 0x80 0x40 0x00 Comments Sets (red) target 512. Must written. Sets (green) target Must written. Sets (blue) target 512. Must written. Sets midscale clamp ground clamp. Selects update rate every clamps enables auto-offset.
Figure Typical Input Configuration
REFERENCE BYPASSING
REFLO REFHI connected each other capacitor (see Figure These references used input circuitry.
REFHI 10µF REFLO
Figure Input Amplifier Reference Capacitors
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AD9984A
CLOCK GENERATION
used generate pixel clock. Hsync input provides reference frequency PLL. voltage controlled oscillator (VCO) generates much higher pixel clock frequency. pixel clock divided divide value (Register 0x01 Register 0x02) phase-compared with Hsync input. error used shift frequency maintain lock between signals. stability this clock very important element providing clearest most stable image. During each pixel time, signal slews from pixel amplitude settles value; this called slewing time. Then, input voltage stabilizes before signal must slew value; this called stable time. ratio slewing time stable time function graphics bandwidth bandwidth transmission system (cable termination). This ratio also function overall pixel rate. dynamic characteristics system remain fixed, slewing settling time likewise fixed. This time must subtracted from total pixel period, leaving stable period. higher pixel frequencies, total cycle time shorter stable pixel time becomes shorter well.
PIXEL CLOCK INVALID SAMPLE TIMES
Four programmable registers provided optimize performance PLL. These registers 12-bit divisor register, 2-bit range register, 3-bit charge pump current register, 5-bit phase adjust register.
12-Bit Divisor Register
input Hsync frequencies accommodate Hsync long product Hsync divisor falls within operating range VCO. multiplies frequency Hsync signal, producing pixel clock frequencies range MHz. divisor register controls exact multiplication factor. This register value between 4095 long output frequency within range.
2-Bit Range Register
improve noise performance AD9984A, operating frequency range divided into four overlapping regions. range register sets this operating range. frequency ranges four regions shown Table Table Frequency Ranges
Pixel Clock Range (MHz)
KVCO Gain (MHz/V)
frequencies lower, enable range (Reg. 0x36[0]).
3-Bit Charge Pump Current Register
This register varies current that drives low-pass loop filter. possible current values listed Table
06476-006
Table Charge Pump Current/Control Bits
Current 1500
Figure Pixel Sampling Times
jitter clock reduces precision sampling time must also subtracted from stable pixel time. Considerable care been taken design AD9984A clock generation circuit minimize jitter. clock jitter AD9984A operating modes, making reduction valid sampling time jitter negligible. characteristics determined loop filter design, charge pump current, range setting. loop filter design illustrated Figure Recommended settings range charge pump current VESA standard display modes listed Table
8.2nF 1.5k 82nF
5-Bit Phase Adjust Register
phase generated sampling clock shifted locate optimum sampling point within clock cycle. phase adjust register provides phase-shift steps 11.25° each. Hsync signal with identical phase shift available through HSOUT pin. Phase adjust still available external pixel clock used. COAST internal coast used allow continue same frequency absence incoming Hsync signal during disturbances Hsync (such from equalization pulses). This used during vertical sync period other time that Hsync signal unavailable.
FILT
Figure Loop Filter Design
06476-007
Rev. Page
AD9984A
polarity coast signal through coast polarity register (Register 0x18, Bits[6:5]). addition, polarity Hsync signal through Hsync polarity register (Register 0x12, Bits[5:4]). both Hsync coast, value active high. internal coast function driven Vsync signal, which typically time when Hsync signals disrupted with extra equalization pulses.
Table Recommended Range Charge Pump Current Settings Standard Display Formats
Standard Resolution Refresh Rate (Hz) Horizontal Frequency (kHz) 31.500 37.700 37.500 43.300 35.100 37.900 48.100 46.900 53.700 48.400 56.500 60.000 64.000 68.300 64.000 80.000 91.100 75.000 15.750 31.470 15.625 31.250 45.000 33.750 33.750 67.500 Pixel Rate (MHz) 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 65.000 75.000 78.750 85.500 94.500 108.000 135.000 157.500 162.000 13.510 27.000 13.500 27.000 74.250 74.250 74.250 148.500 Divider 1024 1056 1040 1056 1048 1344 1328 1312 1336 1376 1688 1688 1728 2160 1650 2200 2200 2200 Range Current Gear (Reg.0x36[0])
SVGA
1024
SXGA
1280 1024
UXGA
1600 1200 480i 480p 576i 576p 720p 1035i 1080i 1080p
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AD9984A
SYNC PROCESSING
inputs sync processing section AD9984A combinations digital Hsyncs Vsyncs, analog sync-ongreen sync-on-Y signals, optional external coast signal. From these signals, part generates precise, jitterfree clock from PLL, odd/even-field signal, HSOUT VSOUT signals, count Hsyncs Vsync, programmable SOGOUT. main sync processing blocks sync slicer, sync separator, Hsync filter, Hsync regenerator, Vsync filter, coast generator. sync slicer extracts sync signal from green graphics luminance video signal that connected SOGINx inputs, outputs digital composite sync. sync separator extracts Vsync from composite sync signal, which come from either sync slicer HSYNCx inputs. Hsync filter used eliminate extraneous pulses from HSYNCx SOGINx inputs, outputting clean, low-jitter signal that appropriate mode detection clock generation. Hsync regenerator used recreate clean, although jitter, Hsync signal that used mode detection counting Hsyncs Vsync. Vsync filter used eliminate spurious Vsyncs, maintain stable timing relationship between Vsync Hsync output signals, generate odd/even field output. coast generator creates robust coast signal allow maintain frequency absence Hsync pulses.
AD9984A
HSYNC0 ACTIVITY DETECT HSYNC1 ACTIVITY DETECT SOGIN0 POLARITY DETECT POLARITY DETECT
CHANNEL SELECT 0x1E:6
HSYNC SELECT 0x12:6
HSYNC FILTER REGENERATOR FILTERED HSYNC REGENERATED HSYNC
SYNC SLICER ACTIVITY DETECT ACTIVITY DETECT SYNC FILTER 0x20:1
SYNC PROCESSOR VSYNC FILTER
SOGIN1
SYNC SLICER
POLARITY
SOGOUT
VSYNC0 ACTIVITY DETECT VSYNC1 ACTIVITY DETECT POLARITY DETECT POLARITY DETECT VSYNC
SOGOUT SELECT 0x1D:1,0 VSYNC VSOUT/A0 FILTERED VSYNC VSYNC FILTER 0x14:2 POLARITY POLARITY POLARITY FIELD HSOUT
VSYNC FILTER 0x14:2
SYNC FILTER 0x20:2 COAST
HSYNC
HSYNC/VSYNC COUNTER 0x26, 0x27
EXTCK/COAST
CLOCK GENERATOR
COAST SELECT 0x18:7
Figure Sync Processing Block Diagram
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DATACK
AD9984A
Sync Slicer
purpose sync slicer extract sync signal from green graphics luminance video signal that connected input. sync signal extracted step process. First, input clamped negative peak, (typically below black level). Next, signal goes comparator with variable trigger level (set Register 0x1D, Bits[7:3]), nominally 0.128 above clamped level. sync slicer output digital composite sync signal containing both Hsync Vsync information (see Figure 10).
Hsync Filter Regenerator
Hsync filter used eliminate extraneous pulses from Hsync inputs, outputting clean, jitter signal that appropriate mode detection clock generation. Hsync regenerator used recreate clean, jitter, Hsync signal that used mode detection counting Hsyncs Vsync. Hsync regenerator high degree tolerance extraneous missing pulses Hsync input, appropriate creating pixel clock jitter. Hsync regenerator runs automatically requires setup operate. Hsync filter requires setting filter window. filter window sets periodic window time around regenerated Hsync leading edge where valid Hsyncs allowed occur. general idea that extraneous pulses sync input occur outside this filter window thus, filtered out. filter window timing, program value into Register 0x23. resulting filter window time times around regenerated Hsync leading edge. Just sync separator threshold multiplier, allow ±20% variance multiplier account operating conditions range). second output from Hsync filter status (Register 0x25, that indicates extraneous pulses present incoming sync signal. Extraneous pulses often included copy protection purposes, this status used detect such pulses. filtered Hsync (rather than HSYNCx/SOGINx signal) pixel clock generation controlled Register 0x20, regenerated Hsync (rather than HSYNCx/SOGINx signal) sync processing controlled Register 0x20, Using filtered Hsync regenerated Hsync recommended. Figure illustration filtered Hsync.
Sync Separator
part sync processing, sync separator's task extract Vsync from composite sync signal. works idea that Vsync signal stays active much longer time than Hsync signal. using digital low-pass filter digital comparator, sync separator rejects pulses with small durations (such Hsyncs equalization pulses) only passes pulses with large durations, such Vsync (see Figure 10). threshold digital comparator programmable maximum flexibility. program threshold duration, write value Register 0x11. resulting pulse width example, digital comparator threshold pulse less than rejected, while pulse greater than passes through. There factors keep mind when using sync separator. First, resulting clean Vsync output delayed from original Vsync duration equal digital comparator threshold ns). Second, there some variability multiplier value. maximum variability over operating conditions ±20% (160 ns). Because normal Vsync Hsync pulse widths differ factor approximately more, variability issue.
NEGATIVE PULSE WIDTH SAMPLE CLOCKS 700mV MAXIMUM INPUT +300mV -300mV
SOGOUT OUTPUT CONNECTED HSYNCIN
COMPOSITE SYNC HSYNCIN
06476-009
VSYNCOUT FROM SYNC SEPARATOR
Figure Sync Slicer Sync Separator Output
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AD9984A
HSYNCIN
FILTER WINDOW
HSYNCOUT
VSYNC
EQUALIZATION PULSES
EXPECTED EDGE
FILTER WINDOW
Figure Sync Processing Filter
Vsync Filter Odd/Even Fields
Vsync filter used eliminate spurious Vsyncs, maintain stable timing relationship between Vsync Hsync output signals, generate odd/even field output. filter works examining placement Vsync with respect Hsync necessary, shifting time slightly. goal keep Vsync Hsync leading edges from switching same time, thus eliminating confusion when first line frame occurs. Register 0x14, enables Vsync filter. Vsync filter recommended cases, including interlaced video, required when using Hsyncs Vsync counter. Figure Figure illustrate even/odd field determination situations.
SYNC SEPERATOR THRESHOLD
FIELD QUADRANT HSYNCIN VSYNCIN VSYNCOUT
FIELD
FIELD
06476-010
FIELD
EVEN FIELD
Figure Even Field
SYNC SEPERATOR THRESHOLD
FIELD QUADRANT HSYNCIN VSYNCIN VSYNCOUT FIELD
FIELD
FIELD
FIELD
FIELD
Figure Field
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06476-012
FIELD
AD9984A
POWER MANAGEMENT
meet display requirements standby power, AD9984A includes power-down mode. power-down state controlled manually (via Register 0x1E, automatically chip. automatic control selected (Register 0x1E, =1), AD9984A's decision based status following sync detect bits Register 0x24: either Hsync sync-on-green input detected input, chip powers otherwise, powers down. manual control, AD9984A allows flexibility control through both dedicated register bit. dedicated pin, hardware watchdog circuit controls power-down, while software controls power-down register bit. With manual power-down control, polarity power-down must (Register 0x1E, whether used not. unused, recommended polarity active high hardwire ground with resistor. power-down mode, several circuits continue operate normally. serial register sync detect circuits maintain power that AD9984A woken from powerdown state. band circuit maintains power because needed sync detection. sync-on-green SOGOUT functions continue operate because SOGOUT needed when sync detection performed secondary chip. these circuits require minimal power operate. Typical standby power AD9984A about There options that selected when powerdown. These controlled Register 0x1E. controls whether SOGOUT high impedance not. most cases, user does place SOGOUT high impedance during normal operation. option SOGOUT high impedance included mainly allow factory testing modes. keeps AD9984A powered while placing only outputs high impedance. This option useful when data outputs from chips connected user wants switch instantaneously between two.
Table 11.Power-Down Control Mode Descriptions
Mode Power-Up Power-Down Power-Up Power-Down
Auto Power-Down Control
Inputs Power-Down
Sync Detect
Powered on/Comments Everything. Only serial bus, sync activity detect, SOG, band reference. Everything. Only serial bus, sync activity detect, SOG, band reference.
Auto power-down control Register 0x1E, Power-down controlled OR'ing with Register 0x1E, polarity Register 0x1E, Sync detect determined OR'ing Register 0x24,
TIMING DIAGRAMS
timing diagrams Figure Figure show operation AD9984A. output data clock signal created that rising edge always occurs between data transitions used latch output data externally. There pipeline AD9984A that must flushed before valid data becomes available. This means data sets present before valid data available.
tPER tDCYCLE
DATACK
tSKEW
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DATA HSOUT
Figure Output Timing
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AD9984A
DATAIN HSYNCx
DATACK CLOCK CYCLE DELAY DATAOUT CLOCK CYCLE DELAY HSOUT
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Figure 4:4:4 Timing Mode
DATAIN
HSYNCx
DATACK CLOCK CYCLE DELAY YOUT Cb/CrOUT CLOCK CYCLE DELAY HSOUT
06476-015
NOTES PIXEL AFTER HSOUT CORRESPONDS BLUE INPUT. EVEN NUMBER PIXEL DELAY BETWEEN HSOUT DATAOUT.
Figure 4:2:2 Timing Mode
DATAIN
HSYNCx
DATACK CLOCK CYCLE DELAY CLOCK CYCLE DELAY HSOUT
NOTES OUTPUT DATACK DELAYED CLOCK PERIOD REGISTERS. PROJECT DOCUMENT VALUES (FALLING EDGE) (RISING EDGE). 4:2:2 MODE: TIMING IDENTICAL, VALUES CHANGE.
06476-016
GENERAL NOTES DATA DELAY VARY CLOCK CYCLE, DEPENDING PHASE SETTING. ADCs SAMPLE INPUT FALLING EDGE DATACK. HSYNC SHOWN ACTIVE HIGH (EDGE SHOWN LEADING EDGE).
Figure Double Data Rate (DDR) Timing Mode
HSYNC TIMING
Hsync processed AD9984A eliminate ambiguity timing leading edge with respect phasedelayed pixel clock data. Hsync input used reference generate pixel sampling clock. sampling phase adjusted with respect Hsync through full 360° steps phase adjust register optimize pixel sampling time). Display systems Hsync align memory display write cycles.
Therefore, important have stable timing relationship between Hsync output (HSOUT) data clock (DATACK). Three things happen Hsync AD9984A. First, polarity Hsync input determined and, result, known output polarity. known output polarity programmed either active high active (Register 0x12, Second, HSOUT aligned with DATACK data outputs. Third, duration HSOUT pixel clocks) Register 0x13. HSOUT sync signal that should used drive rest display system.
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AD9984A
COAST TIMING
most computer systems, Hsync signal provided continuously dedicated wire. these systems, COAST input function unnecessary should used. some systems, however, Hsync disturbed during vertical sync period (Vsync). some cases, Hsync pulses disappear. other systems, such those that employ composite sync (Csync) signals embedded sync-on-green, Hsync include equalization pulses other distortions during Vsync. avoid upsetting clock generator during Vsync, important ignore these distortions. pixel clock sees extraneous pulses, attempts lock this frequency, changes frequency Vsync period. then takes lines correct Hsync timing recover beginning frame, resulting tearing image display. COAST input provided eliminate this problem. asynchronous input that disables input holds clock current frequency. free several lines without significant frequency drift. Coast generated internally AD9984A (see Register 0x18) provided externally graphics controller. When internal coast selected (Register 0x18, Register 0x14, Bits[7:6] select source), Vsync used basis determining position coast. internal coast signal enabled programmed number Hsync periods before periodic Vsync signal (Precoast Register 0x16), dropped programmed number Hsync periods after Vsync (Postcoast Register 0x17). recommended that Vsync filter enabled when using internal coast function allow AD9984A precisely determine number Hsyncs/Vsync their location. many applications where disruptions occur coast used, values precoast postcoast sufficient avoid most extraneous pulses.
OUTPUT FORMATTER
output formatter capable generating several output formats presented data output pins. output formats assignments each format listed Table addition, there several clock options output clock. user select pixel clock, phaseshifted pixel clock, pixel clock, pixel clock test purposes. output clock also inverted. Data output available 30-pin YCbCr, either 4:2:2 4:4:4 selected, secondary channel available. This secondary channel always 4:2:2 DDR. contains same video data primary channel utilized either another display storage device. Depending choice output modes, primary output pins, pins, pins.
Mode Descriptions 4:4:4
channels come with their data bits same time. Data aligned negative edge clock easy capture. This normal 30-bit output mode 4:4:4 YCbCr.
4:2:2
green channels contain 4:2:2 formatted data pins) with data green channel data channel. Data aligned negative edge clock. blue channel contains secondary channel with formatted 4:2:2 data. data edges aligned both edges pixel clock, therefore, using clock necessary capture data.
4:4:4
This mode puts full 4:4:4 data bits green channels, thus saving pins. first half (RGB[14:0]) 30-bit data sent rising edge second half (RGB[29:15]) sent falling edge. 4:2:2 data sent blue channel, 4:2:2 mode. RGB[29:0] R[9:0] G[9:0] B[9:0], RGB[29:15] R[9:0] G[9:5] RGB[14:0] G[4:0] B[9:0]
Table Output Formats
Port 4:4:4 4:2:2 4:4:4
Red/Cr
Green Green/Y
Blue Blue/Cb
4:2:2 Cb,Cr 4:2:2 Cb,Cr 4:2:2
G[4:0] R[9:0]
B[9:0] G[9:5]
Arrows table indicate clock edge. Rising edge clock falling edge 4:2:2 modes, sent before
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AD9984A 2-WIRE SERIAL CONTROL PORT
2-wire serial control interface provided with AD9984A. AD9984A devices connected 2-wire serial interface with each device having unique address. 2-wire serial interface comprises clock (SCL) bidirectional data (SDA) pin. analog flat panel interface acts slave receiving transmitting data over serial interface. When serial interface active, logic levels pulled high external pull-up resistors. Data received transmitted line must stable duration positive-going pulse. Data must change only when low. changes state while high, serial interface interprets that action start stop sequence. following five components serial operation: Start signal Slave address byte Base register address byte Data byte read write Stop signal Table Serial Port Addresses
(MSB)
DATA TRANSFER SERIAL INTERFACE
each byte data read written, first sequence. AD9984A does acknowledge master device during write sequence, remains high master generate stop signal. master device does acknowledge AD9984A during read sequence, AD9984A interprets this data. remains high master generate stop signal. Writing data specific control registers AD9984A requires writing 8-bit address control register interest after slave address been established. This control register address base address subsequent write operations. After initial data byte written, base address autoincrements each additional data byte. more bytes transferred than available addresses, address does increment remains maximum value 0x44. base address higher than 0x44 does produce acknowledge signal. Data read from control registers AD9984A similar manner. Reading requires data transfer operations. base address must written with slave address byte sequential read operation. Reading (the slave address byte high) begins previously established base address. address read register auto-increments after each byte transferred. terminate read/write sequence AD9984A, stop signal must sent. stop signal comprises low-to-high transition while high.
When serial interface inactive (SCL high), communication initiated sending start signal. start signal high-to-low transition while high. This signal alerts slaved devices that data transfer sequence coming. first bits data transferred after start signal comprise 7-bit slave address (the first seven bits) single (the eighth bit). indicates direction data transfer, read from write slave device. transmitted slave address matches address device, AD9984A acknowledges match bringing ninth pulse. addresses match, AD9984A does acknowledge
repeated start signal occurs when master device driving serial interface generates start signal without first generating stop signal terminate current communication. This used change mode communication (read, write) between slave master without releasing serial interface lines.
tBUFF
tSTAH
tDHO tDAL
tDSU
tSTASU
tSTOSU
tDAH
Figure Serial Port Read/Write Timing
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AD9984A
Serial Interface Read/Write Examples Write Control Register
Start signal Slave address byte (R/W low) Base address byte Data byte base address Stop signal Start signal Slave address byte (R/W low) Base address byte Data byte base address Data byte (base address Data byte (base address Data byte (base address Stop signal
Read from Control Register
Start signal Slave address byte (R/W low) Base address byte Start signal Slave address byte (R/W high) Data byte from base address Stop signal Start signal Slave address byte (R/W low) Base address byte Start signal Slave address byte (R/W high) Data byte from base address Data byte from (base address Data byte from (base address Data byte from (base address
Write Four Consecutive Control Registers
Read from Four Consecutive Control Registers
Stop signal
06476-018
Figure Serial Interface-Typical Byte Transfer
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AD9984A 2-WIRE SERIAL REGISTER
AD9984A initialized controlled registers that determine operating modes. external controller employed write read control registers through 2-wire serial interface port. Table Control Register
Address 0x00 0x01 Read/Write, Read Only Bits Default Value 0010 0000 0110 1001 Register Name Chip Revision MSBs Description 8-bit register that represents silicon revision level. MSBs (Bits[11:4] Divider. Larger values mean operates faster rate. This register should loaded first when change needed. (This gives more time lock). LSBs (Bits[3:0]) Divider. Links make 12-bit register.1 Range Select. Chooses frequency range (see Clock Generation section). Charge Pump Current. Varies current that drives low-pass filter (see Clock Generation section). External Clock Enable. Clock Phase Adjust. Larger values mean more delay. T/32). MSBs Channel Gain Control. Controls input range (contrast) each respective channel. Larger values give less contrast. LSBs Channel Gain Control. Links with Register 0x05 form 9-bit gain that controls input range (contrast) channel. lower value corresponds higher gain.1 MSBs Green Channel Gain Control. Controls input range (contrast) each respective channel. Larger values give less contrast. LSBs Green Channel Gain Control. Links Register 0x07 form 9-bit green gain that controls input range (contrast) green channel. lower value corresponds higher gain.1 MSBs Blue Channel Gain Control. Controls input range (contrast) each respective channel. Larger values give less contrast. LSBs Blue Channel Gain Control. Links Register 0x09 form 9-bit blue gain that controls input range (contrast) blue channel. lower value corresponds higher gain.1 MSBs Channel Offset Control. Controls offset (brightness) each respective channel. Larger values decrease brightness.1 LSBs Channel Offset Control. Links Register 0x0B form 11-bit offset that controls offset (brightness) channel auto-offset mode. MSBs Green Channel Offset Control. Controls offset (brightness) each respective channel. Larger values decrease brightness.1 LSBs Green Channel Offset Control. Links Register 0x0D form 11-bit green offset that controls offset (brightness) green channel auto-offset mode. MSBs Blue Channel Offset Control. Controls offset (brightness) each respective channel. Larger values decrease brightness.1 LSBs Blue Channel Offset Control. Links Register 0x0F form 11-bit blue offset that controls offset (brightness) blue channel auto-offset mode. Sets threshold sync separator's digital comparator. Hsync Source Override. chip determines active Hsync source. active Hsync source Reg. 0x12,
0x02 0x03
1101 **** 01** **** **00 1*** **** *0** 1000 0*** *100 0000 00** ****
LSBs VCO/CPMP
0x04 0x05 0x06
Phase Adjust Gain MSBs Gain LSBs
0x07
*100 0000
Green Gain MSBs
0x08
00** ****
Green Gain LSBs
0x09 0x0A
*100 0000 00** ****
Blue Gain MSBs Blue Gain LSBs
0x0B
0100 0000
Offset MSBs
0x0C
000* ****
Offset LSBs
0x0D
0100 0000
Green Offset MSBs
0x0E
000* ****
Green Offset LSBs
0x0F
0100 0000
Blue Offset MSBs
0x10
000* ****
Blue Offset LSBs
0x11 0x12
0010 0000 0*** ****
Sync Separator Threshold Hsync Control
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AD9984A
Address Read/Write, Read Only Bits Default Value *0** **** Register Name Description Hsync Source Select. Determines source Hsync sync processing. This used only Reg. 0x12, both syncs active. Hsync from HSYNCx input pin. Hsync from SOG. Hsync Input Polarity Override. chip selects Hsync input polarity. input polarity Hsync controlled Reg. 0x12, Hsync Input Polarity. This used only Reg. 0x12, Hsync input polarity negative. Hsync input polarity positive. Hsync Output Polarity. Sets polarity Hsync output signal (HSOUT). HSOUT polarity negative. HSOUT polarity positive. Sets number pixel clocks that HSOUT active. Vsync Source Override. chip determines active Vsync source. active Vsync source Reg. 0x14, Vsync Source Select. Determines source Vsync sync processing. This used only Reg. 0x14, Vsync from VSYNCx input pin. Vsync from sync separator. Vsync Input Polarity Override. chip selects Vsync input polarity. input polarity Vsync Reg. 0x14, Vsync Input Polarity. This used only Reg. 0x14, Vsync input polarity negative. Vsync input polarity positive. Vsync Output Polarity. Sets polarity output Vsync signal (VSOUT). VSOUT polarity negative. VSOUT polarity positive. Vsync Filter Enable. This needs enabled when using Hsync Vsync counter. Vsync filter disabled. Vsync filter enabled. Vsync Duration Block Enable. This designed used with Vsync filter. Vsync output duration unchanged. Vsync output duration Register 0x15. Sets number Hsyncs that Vsync active. This only used Reg. 0x14, number Hsync periods coast prior Vsync. number Hsync periods coast after Vsync. Coast Source. Determines source coast signal. Using internal coast generated from Vsync. Using external coast signal from COAST pin. Coast Polarity Override. chip selects coast polarity. polarity coast signal Reg. 0x18, Coast Polarity. This used only Reg. 0x18, Coast polarity negative. Coast polarity positive. Clamp Source Select. Determines source clamp timing. Uses internal clamp generated from Hsync. Uses external CLAMP signal.
**0* ****
***1 ****
**** 1***
0x13 0x14
0010 0000 0*** ****
Hsync Duration Vsync Control
*0** ****
**0* ****
***1 ****
**** 1***
**** *0**
**** **0*
0x15 0x16 0x17 0x18
0000 1010 0000 0000 0000 0000 0*** ****
Vsync Duration Precoast Postcoast Coast Clamp Control
*0** ****
**1* ****
***0 ****
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AD9984A
Address Read/Write, Read Only Bits Default Value **** 0*** Register Name Description Clamp Select. Clamp channel ground. Clamp channel midscale. Green Clamp Select. Clamp green channel ground. Clamp green channel midscale. Blue Clamp Select. Clamp blue channel ground. Clamp blue channel midscale. Must proper operation. Places clamp signal integer number clock periods after trailing edge Hsync signal. Number clock periods that clamp signal actively clamping. Clamp Polarity Override. chip selects clamp polarity. polarity clamp signal Reg. 0x1B, Clamp Polarity. This used only Reg. 0x1B, Clamp polarity negative. Clamp polarity positive. Auto-Offset Enable. Auto-offset disabled. Auto-offset enabled (offsets become desired clamp code). Auto-Offset Update Frequency. This selects often autooffset circuit operates. Every clamps. Every clamps. Every clamps. Every Vsync periods. Must written default (011) proper operation. Must 0xFF proper operation. Slicer Comparator Threshold. Sets voltage level slicer's comparator. SOGOUT Polarity. Sets polarity signal SOGOUT pin. SOGOUT polarity negative. SOGOUT polarity positive. SOGOUT Select. SOGINx. HSYNCx. Regenerated Hsync from sync filter. Filtered Hsync from sync filter. Channel Select Override. chip determines which input channels use. input channel selection determined Reg. 0x1E, Channel Select. This used only Reg. 0x1E, syncs present both channels. Channel syncs data selected. Channel syncs data selected. Programmable Bandwidth. analog input bandwidth MHz). High analog input bandwidth (~300 MHz). Power-Down Control Select. Manual power-down control. Auto power-down control. Power-Down. Normal operation. Power-down.
**** *0**
**** **0*
0x19 0x1A 0x1B
**** ***0 0000 1000 0010 0000 0*** ****
Clamp Placement Clamp Duration Clamp Offset
*1** ****
**0* ****
***1 1***
0x1C 0x1D
**** *011 1111 1111 0111 1*** **** *0**
Test Register Control
**** **00
0x1E
****
Input Power Control
*0** ****
**1* ****
***1 ****
**** 0***
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AD9984A
Address Read/Write, Read Only Bits Default Value **** *0** Register Name Description Power-Down Polarity. Sets polarity signal PWRDN pin. PWRDN polarity negative. PWRDN polarity positive. Power-Down Fast Switching Control. Normal power-down operation. chip stays powered outputs high impedance mode. SOGOUT High Impedance Control. SOGOUT operates normal during power-down. SOGOUT high impedance during power-down. Output Mode. 4:4:4 mode. 4:2:2 YCbCr mode. 4:4:4 mode. Primary Output Enable. Primary output high impedance state. Primary output enabled. Secondary Output Enable. Secondary output high impedance state. Secondary output enabled. Output Drive Strength. Applies outputs except VSOUT. output drive strength. Medium output drive strength. High output drive strength. Output Clock Invert. Applies clocks output DATACK. Noninverted Pixel Clock. Inverted Pixel Clock. Output Clock Select. Pixel clock. phase-shifted pixel clock. pixel clock. pixel clock. Output High Impedance. Normal outputs. outputs except SOGOUT high impedance mode. SOGOUT High Impedance. Normal drive. SOGOUT high impedance mode. Field Output Polarity. Sets polarity field output signal. Active even field, active high field. Active field, active high even field. Sync Filter Enable. uses HSYNCx/SOGINx. uses filtered Hsync/SOG. Sync Processing Input Select. Selects sync source sync processor. Sync processing uses HSYNCx/SOGINx. Sync processing uses regenerated Hsync from sync filter. Must proper operation. Must default proper operation. Must default proper operation. Sync Filter Window Width Sync Detect Sets window time around regenerated Hsync leading edge steps) that sync pulses allowed pass through. HSYNC0 Detection. HSYNC0 active. HSYNC0 active.
**** **0*
**** ***0
0x1F
100* ****
Output Select
***1 ****
**** 0***
**** *10*
**** ***0
0x20
0*** ****
Output Select
*0** ****
**0* ****
***0 ****
**** 1***
**** *0**
0x21 0x22 0x23 0x24
**** ***0 0010 0000 0011 0010 0000 1010 _*** ****
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AD9984A
Address Read/Write, Read Only Bits Default Value *_** **** Register Name Description HSYNC1 Detection. HSYNC1 active. HSYNC1 active. VSYNC0 Detection. VSYNC0 active. VSYNC0 active. VSYNC1 Detection. VSYNC1 active. VSYNC1 active. SOGIN0 Detection. SOGIN0 active. SOGIN0 active. SOGIN1 Detection. SOGIN1 active. SOGIN1 active. COAST Detection. External COAST active. External COAST active. CLAMP Detection. External CLAMP active. External CLAMP active. HSYNC0 Polarity. HSYNC0 polarity negative. HSYNC0 polarity positive. HSYNC1 Polarity. HSYNC1 polarity negative. HSYNC1 polarity active high. VSYNC0 Polarity. VSYNC0 polarity negative. VSYNC0 polarity positive. VSYNC1 Polarity. VSYNC1 polarity negative. VSYNC1 polarity positive. COAST Polarity. External COAST negative. External COAST positive. CLAMP Polarity. External CLAMP negative. External CLAMP polarity positive. Extraneous Pulse Detection. extraneous pulses detected Hsync. Extraneous pulses detected Hsync. Sync Filter Lock. Sync filter unlocked Sync filter locked. MSBs Hsyncs Vsync count. LSBs Hsyncs Vsync count. Must written 0xBF proper operation. Must written 0x02 proper operation. Read only bits future use. Read only bits future use. Must written default proper operation.
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
**** ***_
0x25
_*** ****
Sync Polarity Detect
*_** ****
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
**** ***_
0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C
1011 1111 0000 0010
Hsyncs Vsync MSBs Hsyncs Vsync LSBs Test Register Test Register Test Register Test Register Offset Hold
000* ****
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AD9984A
Address Read/Write, Read Only Bits Default Value ***0 **** Register Name Description Auto-Offset Hold. Disables auto-offset holds feedback result. Continuous update. time update. Must written default proper operation. Must written 0xE8 proper operation. Must written 0xE0 proper operation. Filter Enable. When enabled, filters inputs less than filter disabled. filter enabled. Gear Select. Adds another range VCO. Used lower frequencies only. Disable gear. Enable gear. Test Bits. Must default proper operation. Auto Gain Matching Hold. Disables auto gain updates holds current auto offset values. Allows auto gain continuously update. Auto Gain Matching Enable. Auto gain matching disabled. 110= Auto gain matching enabled.
0x2D 0x2E 0x34
**** 0000 1111 0000 1111 0000 **** *0**
Test Register Test Register Filter
0x36
**** ***0
Gear
0x3C
0000 **** **** 0***
Auto Gain
**** *000
Functions with more than eight control bits, such divide ratio, gain, offset, only updated when LSBs written (for example, Register 0x02 divide ratio).
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AD9984A 2-WIRE SERIAL CONTROL REGISTERS
CHIP IDENTIFICATION
0x00-Bits[7:0] Chip Revision
This 8-bit register that represents silicon revision. Table Range Select Bits
Value Result (Pixel Rates)
DIVIDER CONTROL
0x01-Bits[7:0] Divide Ratio MSBs
These MSBs 12-bit divide ratio (PLLDIV). derives pixel clock from incoming Hsync signal. pixel clock frequency then divided integer value, such that output phase-locked Hsync. This PLLDIV value determines number pixel times (pixels plus horizontal blanking overhead) line. This typically more than number active pixels display. 12-bit value divider supports divide ratios from 4095 long output frequency within range. higher value loaded this register, higher resulting clock frequency with respect fixed Hsync frequency. VESA established some standard timing specifications that assist determining value PLLDIV function horizontal vertical display resolution frame rate (see Table 10). However, many computer systems precisely conform recommendations. result, these numbers should used only guide. display system manufacturer should provide automatic manual means optimizing PLLDIV. incorrectly PLLDIV usually produces more vertical noise bars display. greater error, greater number bars produced. power-up default value PLLDIV 1693. PLLDIVM 0x69, PLLDIVL 0xDX. AD9984A updates full divide ratio only when LSBs written. Writing this register itself does trigger update.
0x03-Bits[5:3] Charge Pump Current
These three bits establish current driving loop filter clock generator. current must correspond with desired operating frequency. power-up default value current 001. Table Charge Pump Current Bits
Result (Current) 1500
0x03-Bit[2] External Clock Enable
This determines source pixel clock. Table External Clock Enable
Value Result Internally generated clock. Externally provided clock signal.
Logic enables internal that generates pixel clock from externally provided Hsync. Logic enables external EXTCK input pin. this mode, divide ratio (PLLDIV) ignored. clock phase adjust (Phase) still functional. power-up default value EXTCK
0x02-Bits[7:4] Divide Ratio LSBs
These four LSBs 12-bit divide ratio (PLLDIV). power-up default value PLLDIV 1693. PLLDIVM 0x69, PLLDIVL 0xDX.
CLOCK GENERATOR CONTROL
0x03-Bits[7:6] Range Select
These bits establish operating range clock generator. range must correspond desired operating frequency (incoming pixel rate). gives best jitter performance high frequencies. this reason, output pixel rates still achieve good jitter performance, operates higher frequency, then divides down clock rate afterwards. Table pixel rates each range setting. output divisor automatically selected with range setting. power-up default value
PHASE ADJUST
0x04-Bits[7:3] Clock Phase Adjust
These bits adjust phase generate clock. 5-bit value adjusts sampling phase steps across pixel time. Each step represents 11.25° shift sampling phase. power-up default
INPUT GAIN
AD9984A accommodate input signals with full-scale range between p-p. Setting red, green, blue channel gain corresponds input range red, green, blue channel gain establishes input range Note that increasing gain results picture having less contrast (the input signal uses fewer available converter codes).
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AD9984A
0x05-Bits[6:0] Channel Gain Control MSBs
This register contains 7-bit MSBs channel gain control. Values written this register updated until register (Register 0x06) also been written power-up default 1000000.
0x0C-Bits[7:5] Channel Offset Control LSBs
This register contains 3-bit LSBs channel offset control. Combining these bits with bits MSBs Register 0x0B creates bits offset control.
0x0D-Bits[7:0] Green Channel Offset Control MSBs
This register contains 8-bit MSBs green channel offset control. Update this register occurs only when Register 0x0E also written
0x06 -Bits[7:6] Channel Gain Control LSBs
This register contains 2-bit LSBs channel gain control. Along with MSBs gain control Register 0x05, there bits gain control. Default power-up value
0x0E-Bits[7:5] Green Channel Offset Control LSBs
This register contains 3-bit LSBs green channel offset control. Combining these bits with bits MSBs Register 0x0D makes bits offset control.
0x07-Bits[6:0] Green Channel Gain Control MSBs
This register contains 7-bit MSBs green channel gain control. Register update requires writing 0x00 Register 0x08.
0x08-Bits[7:6] Green Channel Gain Control LSBs
This register contains 2-bit LSBs green channel gain control. Along with MSBs gain control Register 0x07, there bits gain control. Default power-up value
0x0F-Bits[7:0] Blue Channel Offset Control MSBs
8-bit blue channel offset control. Update this register occurs only when Register 0x10 also written
0x10-Bits[7:5] Blue Channel Offset Control LSBs
LSBs blue channel offset control combine with bits MSBs Register 0x0F make bits offset control.
0x09-Bits[6:0] Blue Channel Gain Control MSBs
This register contains 7-bit MSBs blue channel gain control. Register update requires writing 0x00 Register 0x0A.
HSYNC CONTROL
0x11-Bits[7:0] Sync Separator Threshold
This register sets threshold sync separator's digital comparator. value written this register multiplied threshold value. Therefore, value written, digital comparator threshold pulses less than rejected sync separator. There some variability multiplier value. maximum variability over operating conditions ±20% (160 ns). Because normal Vsync Hsync pulse widths differ factor about more, variability issue. power-up default value 32d.
0x0A-Bits[7:6] Blue Channel Gain Control LSBs
This register contains 2-bit LSBs blue channel gain control. Along with MSBs gain control Register 0x09, there bits gain control. Default power-up value
INPUT OFFSET
offset control shifts analog input, resulting change brightness. Note that function red, blue, green channel offset registers depends whether auto-offset enabled (Register 0x1B, auto-offset disabled, nine bits offset registers (Bits[6:0] offset register plus Bits[7:6] following register) control absolute offset added channel (for channel, Register 0x0B, Bits[6:0] plus Register 0x0C, Bits[7:6]) control absolute offset added channel. offset control provides ±255 LSBs adjustment range, with offset corresponding output code. auto-offset enabled, 11-bit offset (comprised bits register Bits[7:5] following register) determines clamp target code. 11-bit offset consists sign plus bits. register programmed 530d, output code equal 530d clamp period. Note that incrementing offset register setting adds offset, regardless auto-offset setting.
0x12-Bit[7] Hsync Source Override
This Hsync source override. Setting this allows chip determine active Hsync source. Setting uses Register 0x12 determine active Hsync source. Power-up default value Table Hsync Source Override
Value Result Hsync source determined chip. Hsync source determined user (Register 0x12,
0x12-Bit[6] Hsync Source Select
This selects source Hsync sync processing (only Register 0x12 both syncs active). Setting this specifies Hsync from input pin. Setting selects Hsync from SOG. Power-up default Table Hsync Source Select
Value Result HSYNCx input. Hsync from SOG.
0x0B-Bits[7:0] Channel Offset Control MSBs
This register 8-bit MSBs channel offset control. Along with LSBs channel offset Register 0x0C, there bits offset control channel. Values written this register updated until register (Register 0x0C) also been written
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AD9984A
0x12-Bit[5] Hsync Input Polarity Override
This determines whether chip selects Hsync input polarity specified. Setting this allows chip automatically select polarity input Hsync. Setting indicates that Register 0x12 specifies polarity. Power-up default Table Hsync Input Polarity Override
Value Result Hsync polarity determined chip. Hsync polarity determined user (Register 0x12,
0x14-Bit[6] Vsync Source Select
This selects source Vsync sync processing only Register 0x14 Setting specifies Vsync from input pin. Setting selects Vsync from sync separator. Power-up default Table Vsync Source Select
Value Result Vsync from VSYNCx input pin. Vsync from sync separator.
0x14-Bit[5] Vsync Input Polarity Override
This sets whether chip selects Vsync input polarity specified. Setting this allows chip automatically select polarity input Vsync. Setting this indicates that Register 0x14 specifies polarity. Power-up default Table Vsync Input Polarity Override
Value Result Vsync polarity determined chip. Vsync polarity determined user (Register 0x14,
0x12-Bit[4] Hsync Input Polarity
Register 0x12 value this specifies polarity input Hsync. Setting this indicates negative Hsync input polarity. Setting this indicates positive Hsync input polarity. Power-up default Table Hsync Input Polarity
Value Result Hsync input polarity negative. Hsync input polarity positive.
0x12-Bit[3] Hsync Output Polarity
This sets polarity Hsync output (HSOUT). Setting this indicates negative HSOUT polarity. Setting this indicates positive HSOUT polarity. Table Hsync Output Polarity
Value Result HSOUT polarity negative. HSOUT polarity positive.
0x14-Bit[4] Vsync Input Polarity
Register 0x14 value this specifies polarity input Vsync. Setting this indicates negative Vsync input polarity. Setting this indicates positive Vsync input polarity. Power-up default Table Vsync Input Polarity
Value Result Vsync input polarity negative. Vsync input polarity positive.
0x13-Bits[7:0] Hsync Duration
This 8-bit register sets duration HSOUT pulse. leading edge Hsync output triggered internally generated, phase-adjusted, feedback clock. AD9984A then counts number pixel clocks equal value this register. This triggers trailing edge HSOUT, which also phase-adjusted.
0x14-Bit[3] Vsync Output Polarity
This sets polarity Vsync output (VSOUT). Setting this indicates negative VSOUT polarity. Setting this indicates positive VSOUT polarity. Power-up default Table Vsync Output Polarity
Value Result VSOUT polarity negative. VSOUT polarity positive.
VSYNC CONTROL
0x14-Bit[7] Vsync Source Override
This active Vsync override. Setting this allows chip determine active Vsync source, setting uses Register 0x14 determine active Vsync source. Power-up default value Table Vsync Source Override
Value Result Vsync source determined chip. Vsync source determined user (Register 0x14,
0x14-Bit[2] Vsync Filter Enable
This enables Vsync filter allowing precise placement Vsync with respect Hsync facilitating correct operation Hsyncs/Vsync count. Table Vsync Filter Enable
Value Result Vsync filter disabled. Vsync filter enabled.
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AD9984A
0x14-Bit[1] Vsync Duration Block Enable
This enables Vsync duration block, which designed used with Vsync filter. Setting leaves Vsync output duration unchanged. Setting sets Vsync output duration based Register 0x15. Power-up duration Table Vsync Duration Block Enable
Value Result Vsync output duration unchanged. Vsync output duration Register 0x15.
0x18-Bit[5] Input Coast Polarity
This register sets input coast polarity when Register 0x18 power-up default setting Table Input Coast Polarity
Value Result Coast polarity negative. Coast polarity positive.
0x18-Bit[4] Clamp Source Select
This determines source clamp timing. enables clamp timing circuitry controlled clamp placement clamp duration. clamp position duration counted from leading edge Hsync. enables external CLAMP input pin. three channels clamped when clamp signal active. polarity clamp determined CLAMP polarity bit. power-up default setting Table Clamp Source Select
Value Result Internally generated clamp. Externally provided clamp signal (CLAMP).
0x15-Bits[7:0] Vsync Duration
This register used output duration Vsync, designed used with Vsync filter. This valid only Register 0x14, Power-up default 10d.
COAST CLAMP CONTROLS
0x16-Bits[7:0] Precoast
This register allows internally generated coast signal applied prior Vsync signal. This necessary cases where pre-equalization pulses present. step size this control Hsync period. precoast work correctly, necessary both Vsync filter (Register 0x14, sync processing filter (Register 0x20, either enabled disabled. power-up default
0x18-Bit[3] Clamp Select
This determines whether channel clamped ground midscale. power-up default setting Table Clamp Select
Value Result Clamp ground. Clamp midscale.
0x17-Bits[7:0] Postcoast
This register allows internally generated coast signal applied following Vsync signal. This necessary cases where post equalization pulses present. step size this control Hsync period. postcoast work correctly, necessary both Vsync filter (Register 0x14, sync processing filter (Register 0x20, enabled disabled. power-up default
0x18-Bit[2] Green Clamp Select
This determines whether green channel clamped ground midscale. power-up default setting Table Green Clamp Select
Value Result Clamp ground. Clamp midscale.
0x18-Bit[7] Coast Source
This used select active coast source. choices COAST input Vsync. Vsync selected, additional decision using VSYNCx input output from sync separator needs made (Register 0x14, Bits[7:6]). Table Coast Source
Value Result Vsync (internal coast). COAST pin.
0x18-Bit[1] Blue Clamp Select
This determines whether blue channel clamped ground midscale. power-up default setting Table Blue Clamp Select
Value Result Clamp ground. Clamp midscale.
0x18-Bit[6] Coast Polarity Override
This register used override internal circuitry that determines polarity coast signal going into PLL. power-up default setting Table Coast Polarity Override
Value Result Coast polarity determined chip. Coast polarity determined user (Register 0x18,
0x18-Bit[0]
Must proper operation.
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AD9984A
0x19-Bits[7:0] Clamp Placement
8-bit register that sets position internally generated clamp. When clamp source select (Register 0x18, clamp signal generated internally position established this register duration clamp duration register (Register 0x1A). Clamping started clamp placement count pixel periods after trailing edge Hsync. clamp placement programmed value between 255. value supported. clamp should placed during time that input signal presents stable black-level reference, usually back porch period between Hsync image. When clamp source this register ignored. Power-up default setting Table Auto-Offset Enable
Value Result Auto-offset disabled. Auto-offset enabled (manual offset mode).
0x1B-Bits[4:3] Auto-Offset Update Frequency
These bits control often auto-offset circuit updated enabled). Updating every Hsyncs recommended. power-up default setting Table Auto-Offset Update Frequency Bits
Value Result Update offset every 3-clamp periods. Update offset every 48-clamp periods. Update offset every 192-clamp periods. Update offset every Vsync periods.
0x1A-Bits[7:0] Clamp Duration
8-bit register that sets duration internally generated clamp. When clamp source select (Register 0x18, clamp signal generated internally position established clamp placement register (Register 0x19) duration this clamp duration register. Clamping begins clamp placement count (Register 0x19) pixel periods after trailing edge Hsync. clamp duration programmed value between 255. value supported. best results, clamp duration should include majority black reference signal time that follows Hsync signal trailing edge. Insufficient clamping time produce brightness changes screen, slow recovery from large changes average picture level (APL) brightness. When EXTCLMP this register ignored. Power-up default setting 20d.
0x1B-Bits[2:0]
Must written proper operation.
0x1C-Bits[7:0] Test Register
Must 0xFF proper operation.
CONTROL
0x1D-Bits[7:3] Slicer Comparator Threshold
These register bits adjust comparator threshold slicer steps with minimum setting equaling maximum setting equaling powerup default setting corresponds threshold value
0x1D-Bit[2] SOGOUT Polarity
This sets polarity SOGOUT signal. power-up default setting Table SOGOUT Polarity
Value Result SOGOUT polarity negative. SOGOUT polarity positive.
0x1B-Bit[7] Clamp Polarity Override
This used override internal circuitry that determines polarity clamp signal. power-up default setting Table Clamp Polarity Override
Value Result Clamp polarity determined chip. Clamp polarity determined user (Register 0x1B,
0x1D-Bits[1:0] SOGOUT Select
These register bits control what output SOGOUT pin. Options SOGINx from slicer (that unprocessed signal produced from sync slicer), HSYNCx, regenerated Hsync from sync filter that generate missing syncs coasting drop-out, finally, filtered Hsync that excludes extraneous syncs that occur within sync filter window. power-up default setting Table SOGOUT Select Bits
Value Result SOGINx. HSYNCx. Regenerated Hsync from sync filter. Filtered Hsync from sync filter.
0x1B-Bit[6] Clamp Polarity
This indicates polarity clamp signal only Register 0x1B power-up default setting Table Clamp Polarity
Value Result Clamp polarity negative. Clamp polarity positive.
0x1B-Bit[5] Auto-Offset Enable
This selects between auto-offset mode manual offset mode (auto-offset disabled). Automatic Offset section more information. power-up default setting
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AD9984A
INPUT POWER CONTROL
0x1E-Bit[7] Channel Select Override
This provides override automatic input channel selection. Power-up default setting Table Channel Select Override
Value Result Channel input source determined chip. Channel input source determined user, (Register 0x1E,
0x1E-Bit[3] Power-Down
This used manually place chip power-down mode. only used manual power-down control selected (Register 0x1E, Both state this register power-down (Pin used control manual power-down. (See Power Management section more details power-down.) Table Power-Down
Value Result Normal operation. Power-down.
0x1E-Bit[6] Channel Select
This selects active input channel Register 0x1E This selects between Channel data syncs Channel data syncs. Power-up default setting Table Channel Select
Value Result Channel data syncs selected. Channel data syncs selected.
0x1E-Bit[2] Power-Down Polarity
This defines polarity power-down (Pin 17). only used manual power-down control selected (Register 0x1E, Table Power-Down Polarity
Value Result PWRDN polarity negative. PWRDN polarity positive.
0x1E-Bit[5] Programmable Bandwidth
This selects between high input bandwidth; having input bandwidth useful limiting noise lower frequency inputs. power-up default setting analog input bandwidth MHz; high analog input bandwidth ~300 MHz. Table Programmable Bandwidth
Value Result analog input bandwidth. High analog input bandwidth.
0x1E-Bit[1] Power-Down Fast Switching Control
This controls special fast switching mode. With this bit, AD9984A stay active during power-down only puts outputs high impedance. This option useful when data outputs from chips connected user wants instantaneously switch between two. Table Power-Down Fast Switching Control
Value Result Normal power-down operation. chip stays powered outputs high impedance mode.
0x1E-Bit[4] Power-Down Control Select
This determines whether power-down controlled manually automatically chip. automatic control selected setting this AD9984A's decision based status some sync detect bits (Register 0x24, either Hsync sync-on-green input detected input, chip powers powers down. manual control, AD9984A allows flexibility control through both dedicated register bit. dedicated allows hardware watchdog circuit control power-down, whereas register allows power-down controlled software. With manual power-down control, polarity power-down must (Register 0x1E, whether used not. unused, recommended polarity active high hardwire ground with resistor. Table Power-Down Control Select
Value Result Manual power-down control (user determines power-down). Auto power-down control (chip determines power-down).
0x1E-Bit[0] SOGOUT High Impedance Control
This controls whether SOGOUT output high impedance when power-down mode. most cases, SOGOUT high impedance during normal operation because usually needed sync detection graphics controller. option SOGOUT high impedance included mainly allow factory testing modes. Table SOGOUT High Impedance Control
Value Result SOGOUT operates normal during power-down. SOGOUT high impedance during power-down.
OUTPUT CONTROL
0x1F-Bits[7:5] Output Mode
These bits choose between three options output mode. 4:4:4 mode, standard. 4:2:2 mode, YCbCr standard, which reduces number output pins from 4:4:4 output mode, data mode, changes every clock edge. power-up default setting 100.
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AD9984A
Table Output Mode Bits
Value Result 4:4:4 mode. 4:2:2 YCbCr mode. 4:4:4 mode.
Table Output Clock Select Bits
Value Result Pixel clock. phase-shifted pixel clock. pixel clock. pixel clock.
0x1F-Bit[4] Primary Output Enable
This places primary output active high impedance mode. power-up default setting Table Primary Output Enable
Value Result Primary output high impedance mode. Primary output enabled.
0x20-Bit[5] Output High Impedance
This puts outputs (except SOGOUT) high impedance state. power-up default setting Table Output High Impedance
Value Result Normal outputs. outputs (except SOGOUT) high impedance mode.
0x1F-Bit[3] Secondary Output Enable
This places secondary output active high impedance mode. secondary output designated when using either 4:2:2 4:4:4 DDR. these modes, data blue output channel secondary output while output data green channels primary output. Secondary output always YCbCr data mode. Output Formatter section Table power-up default setting Table Secondary Output Enable
Value Result Secondary output high impedance mode. Secondary output enabled.
0x20-Bit[4] SOGOUT High Impedance
This allows SOGOUT placed high impedance mode. power-up default setting Table SOGOUT High Impedance
Value Result Normal drive. SOGOUT high impedance mode.
0x20-Bit[3] Field Output Polarity
This sets polarity field output bit. power-up default setting Table Field Output Polarity
Value Result Active even field, active high field. Active field, active high even field.
0x1F-Bits[2:1] Output Drive Strength
These bits select drive strength high speed digital outputs (except VSOUT, FIELD). Higher drive strength results faster rise/fall times and, general, makes easier capture data. Lower drive strength results slower rise/fall times helps reduce digitally generated power supply noise. power-up default setting Table Output Drive Strength Bits
Value Result output drive strength. Medium output drive strength. High output drive strength.
SYNC PROCESSING
0x20-Bit[2] Sync Filter Enable
This selects which signal uses. select between versions HSYNCx/SOGINx filtered versions Hsync/SOG. filtering Hsync eliminate nearly extraneous transitions that have traditionally caused disruption. power-up default setting Table Sync Filter Enable
Value Result uses HSYNCx SOGINx. uses filtered Hsync SOG.
0x1F-Bit[0] Output Clock Invert
This allows inversion output clock. power-up default setting Table Output Clock Invert
Value Result Noninverted pixel clock. Inverted pixel clock.
0x20-Bit[1] Sync Processing Input Select
This selects whether sync processor uses sync regenerated Hsync following functions: coast, Hsyncs Vsync count, field detection, Vsync duration counts. Using regenerated Hsync recommended. Table Sync Processing Input Select
Value Result Sync processing uses HSYNCx SOGINx. Sync processing uses internally regenerated Hsync.
0x20-Bits[7:6] Output Clock Select
These bits selects optional output clocks such fixed internal clock, clock, phase-shifted clock, normal pixel clock. power-up default setting
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AD9984A
0x20-Bit[0]
Must proper operation. Table VSYNC1 Detection
Value Result activity detected. Activity detected.
0x21-Bits[7:0]
Must default.
0x24-Bit[3] SOGIN0 Detection
This used indicate when activity detected SOGIN0 pin. SOGIN0 held high low, activity detected. Figure shows where this function implemented. Table SOGIN0 Detection
Value Result activity detected. Activity detected.
0x22-Bits[7:0]
Must default.
0x23-Bits[7:0] Sync Filter Window Width
This 8-bit register sets window time regenerated Hsync leading edge steps) time that sync pulses allowed pass through. Therefore, with default value window width ±250 goal window width reject extraneous pulses (see Sync Processing section). with sync separator threshold, multiplier value somewhat variable. maximum variability over operating conditions ±20% ns).
0x24-Bit[2] SOGIN1 Detection
This used indicate when activity detected SOGIN1 input pin. SOGIN1 held high low, activity detected. Figure shows where this function implemented. Table SOGIN1 Detection
Value Result activity detected. Activity detected.
DETECTION STATUS
0x24-Bit[7] HSYNC0 Detection
This used indicate when activity detected HSYNC0 input pin. HSYNC0 held high low, activity detected. sync processing block diagram (Figure shows where this function implemented. Table HSYNC0 Detection
Value Result activity detected. Activity detected.
0x24-Bit[1] COAST Detection
This detects activity EXTCK/COAST pin. indicates that signals active, does indicate which one. signal detected. Table COAST Detection
Value Result activity detected. Activity detected.
0x24-Bit[6] HSYNC1 Detection
This used indicate when activity detected HSYNC1 input pin. HSYNC1 held high low, activity detected. Figure shows where this function implemented. Table HSYNC1 Detection Results
Value Result activity detected. Activity detected.
0x24-Bit[0] CLAMP Detection
This used indicate when activity detected external CLAMP pin. external CLAMP held high low, activity detected. Table CLAMP Detection
Value Result activity detected. Activity detected.
0x24-Bit[5] VSYNC0 Detection
This used indicate when activity detected VSYNC0 input pin. VSYNC0 held high low, activity detected. Figure shows where this function implemented. Table VSYNC0 Detection Results
Value Result activity detected. Activity detected.
POLARITY STATUS
0x25-Bit[7] HSYNC0 Polarity
This indicates polarity HSYNC0 input. Table HSYNC0 Polarity
Value Result HSYNC0 polarity negative. HSYNC0 polarity positive.
0x24-Bit[4] VSYNC1 Detection
This used indicate when activity detected VSYNC1 input pin. VSYNC1 held high low, activity detected. Figure shows where this function implemented.
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AD9984A
0x25-Bit[6] HSYNC1 Polarity
This indicates polarity HSYNC1 input. Table HSYNC1 Polarity
Value Result HSYNC1 polarity negative. HSYNC1 polarity positive.
HSYNC COUNT
0x26-Bits[7:0] Hsyncs Vsync MSBs
This register contains MSBs 12-bit counter that reports number Hsyncs Vsync active input. useful determining mode setting divide ratio.
0x25-Bit[5] VSYNC0 Polarity
This indicates polarity VSYNC0 input. Table VSYNC0 Polarity
Value Result VSYNC0 polarity negative. VSYNC0 polarity positive.
0x27-Bits[7:4] Hsyncs Vsync LSBs
This register contains four LSBs 12-bit counter that reports number Hsyncs Vsync active input.
TEST REGISTERS
0x28-Bits[7:0] Test Register
Must written 0xBF proper operation.
0x25-Bit[4] VSYNC1 Polarity
This indicates polarity VSYNC1 input. Table VSYNC1 Polarity
Value Result VSYNC1 polarity negative. VSYNC1 polarity positive.
0x29-Bits[7:0] Test Register
Must written 0x02 proper operation.
0x2A-Bits[7:0] Test Register
Read only bits future use.
0x2B-Bits[7:0] Test Register
Read only bits future use.
0x25-Bit[3] COAST Polarity
This indicates polarity external COAST signal. Table COAST Polarity
Value Result COAST polarity negative. COAST polarity positive.
0x2C-Bits[7:5] Offset Hold
Must written default 0x00 proper operation.
0x2C-Bit[4] Auto-Offset Hold
This controls whether auto-offset function runs continuously only once holds result. Continuous updates recommended because they allow AD9984A compensate drift over time, temperature, onetime updates preferred, they should performed every time part powered when there mode change. perform one-time update, auto-offset must first enabled (Register 0x1B, Next, this (auto-offset hold) must first auto-offset function operate settle final value. Auto-offset hold should then hold offset values that auto circuitry calculates. AD9984A auto-offset circuit's maximum settle time updates. example, update frequency once every Hsyncs, maximum settling time 1920 Hsyncs Hsyncs). Table Auto-Offset Hold
Value Result Allows auto-offset continuously update. Disables auto-offset updates holds current auto-offset values.
0x25-Bit[2] CLAMP Polarity
This indicates polarity CLAMP signal. Table CLAMP Polarity
Value Result CLAMP polarity negative. CLAMP polarity positive.
0x25-Bit[1] Extraneous Pulse Detection
second output from Hsync filter, this status tells whether extraneous pulses present incoming sync signal. Often, extraneous pulses used copy protection, this status used this purpose. Table Extraneous Pulse Detection
Value Result extraneous pulses detected during active Hsync. Extraneous pulses detected during active Hsync.
0x2C-Bits[3:0]
Must written proper operation.
0x25-Bit[0] Sync Filter Lock
When this sync filter locked. When sync filer unlocked.
0x2D-Bits[7:0] Test Register
Read/write bits future use. Must written 0xE8 proper operation.
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AD9984A
0x2E-Bits[7:0] Test Register
Read/write bits future use. Must written 0xE0 proper operation. one-time updates preferred, they should performed every time part powered when there mode change. perform one-time update, auto gain matching must first enabled (Register 0x3C, Bits[2:0]). Next, this (auto gain matching hold) must first auto gain matching function operate settle final value. auto gain matching hold should then hold gain values that auto circuitry calculates. AD9984A auto gain matching circuit's maximum settle time updates. example, update frequency once every Hsyncs, maximum settling time would Hsyncs Hsyncs). Table Auto Gain Matching Hold
Value
0x34-Bit[2] Filter Enabler
When this does pass pulses less than width. This reduces spurious signals that improperly drive circuit. Default this off.
0x36-Bit[0] Gear Select
This allows select lower gear lower pixel clocks while remaining more linear range. Table Gear Select
Value Result Normal setting. Enables lower clock output.
0x3C-Bits[7:4] Test Bits
Must proper operation.
Result Disables auto gain updates holds current auto gain values. Allows auto gain update continuously.
power-up default setting
0x3C-Bits[2:0] Auto Gain Matching Enable
These bits enable disable auto gain matching function. Table Auto Gain Matching Enable Bits
Value Result Auto gain matching disabled. Auto gain matching enabled.
0x3C-Bit[3] Auto Gain Matching Hold
This controls whether auto gain matching function runs continuously runs once holds result. Continuous updates recommended because they allow AD9984A compensate drift over time, temperature,
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AD9984A LAYOUT RECOMMENDATIONS
AD9984A high precision, high speed, analog device. achieve maximum performance from part, important have well laid-out board. section provides guide designing board using AD9984A. particularly important maintain noise good stability (the clock generator supply). Abrupt changes result similar changes sampling clock phase frequency. This avoided paying careful attention regulation, filtering, bypassing. desirable provide separate regulated supplies each analog circuitry groups PVD). Some graphic controllers substantially different levels power when active (during active picture time), when idle (during horizontal vertical sync periods). This result measurable change voltage supplied analog supply regulator, which turn produce changes regulated analog supply voltage. This mitigated regulating analog supply, least PVD, from different, cleaner, power source (for example, from supply). also recommended single ground plane entire board. Experience repeatedly shown that noise performance same better with single ground plane. Using multiple ground planes detrimental because each separate ground plane smaller, long ground loops result. some cases, using separate ground planes unavoidable. these cases, place least single ground plane under part. location split should receiver digital outputs. this case, even more important place components wisely because current loops become much longer (current takes path least resistance). example current loop power plane AD9984A digital output trace, digital data receiver, digital ground plane, analog ground plane.
ANALOG INTERFACE INPUTS
following layout techniques graphics inputs: Minimize trace length running into graphics inputs. This accomplished placing AD9984A close possible graphics connector. Long input trace lengths undesirable because they pick noise from board other external sources. Place termination resistors (see Figure close possible AD9984A chip. additional trace length between termination resistors input AD9984A increases magnitude reflections, which corrupts graphics signal. matched impedance traces. Trace impedances other than also increase chance reflections. AD9984A very high input bandwidth (300 MHz). While desirable acquiring high resolution graphics signal with fast edges, also means that captures high frequency noise. Therefore, important reduce amount noise that coupled inputs. Avoid running digital traces near analog inputs. high bandwidth AD9984A, using lowpass filter with analog inputs help reduce noise. (for many applications, filtering unnecessary.) Experiments have shown that placing ferrite bead (specifically, Fair-Rite 2508051217Z0) series prior termination resistor helpful filtering excess noise. However, application could work best with different bead value. Alternatively, placing resistor between termination resistor input coupling capacitor beneficial.
Place loop filter components close FILT possible. place digital other high frequency traces near these components. values suggested data sheet with tolerances less.
OUTPUTS (BOTH DATA CLOCKS)
minimize trace length that digital outputs have drive. Longer traces have higher capacitance require more instantaneous current drive, which creates more internal digital noise. Shorter traces reduce possibility reflections. Adding series resistor suppress reflections, reduce EMI, reduce current spikes inside AD9984A. series resistors used, place them close AD9984A pins possible (although vias extra length output trace resistors closer). possible, limit capacitance driven each digital output less than This easily accomplished keeping traces short connecting outputs only device. Loading outputs with excessive capacitance increases current transients inside AD9984A creates more digital noise power supplies.
Power Supply Bypassing
recommended bypass each power supply with capacitor. exception when more supply pins adjacent each other. these groupings powers/grounds, only necessary have bypass capacitor. fundamental idea have bypass capacitor within ~0.5 each power pin. Also, avoid placing capacitor opposite side board from AD9984A, because doing interposes resistive vias path. bypass capacitors should physically located between power plane power pin. Current should flow from power plane capacitor power pin. make power connection between capacitor power pin. Placing underneath capacitor pads, down power plane, generally best approach.
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AD9984A
DIGITAL INPUTS
Digital inputs AD9984A (HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, CLAMP) designed work with signals, tolerant signals. Therefore, extra components need added using logic. noise that gets onto Hsync input trace adds jitter system. Therefore, minimize trace length digital other high frequency traces near
Reference Bypass
AD9984A reference voltages that must bypassed proper operation ADC. REFLO REFHI connected each other through capacitor. These references used circuitry assure greatest stability. Place them close AD9984A possible.
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AD9984A OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60
16.20 16.00 15.80
VIEW (PINS DOWN)
14.20 14.00 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 3.5° 0.10 COPLANARITY
VIEW
VIEW
ROTATED
0.65 LEAD PITCH
0.38 0.32 0.22
051706-A
COMPLIANT JEDEC STANDARDS MS-026-BEC
Figure 80-Lead Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown millimeters
9.00
0.60 0.60
0.30 0.25 0.18
INDICATOR
INDICATOR
VIEW
8.75
EXPOSED
(BOTTOM VIEW)
*4.85 4.70 4.55
0.50 0.40 0.30
1.00 0.85 0.80
0.80 0.65 0.05 0.02 0.50 0.20
7.50
SEATING PLANE
*COMPLIANT JEDEC STANDARDS MO-220-VMMD-4 EXCEPT EXPOSED DIMENSION
Figure 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-64-1) Dimensions shown millimeters
ORDERING GUIDE
Model AD9984AKSTZ-140 AD9984AKSTZ-1701 AD9984AKCPZ-1401 AD9984AKCPZ-1701 AD9984A/PCBZ1
Temperature Range 70°C 70°C 70°C 70°C
Package Description 80-Lead Profile Quad Flat Package [LQFP] 80-Lead Profile Quad Flat Package [LQFP] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board [LQFP]
RoHS Compliant Part.
Rev. Page
063006-B
Package Option ST-80-2 ST-80-2 CP-64-1 CP-64-1
AD9984A NOTES
Rev. Page
AD9984A NOTES
Purchase licensed components Analog Devices sublicensed Associated Companies conveys license purchaser under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
©2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D06476-0-7/07(0)
Rev. Page
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