FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity High
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LC2MOS Signal Conditioning AD7712*
FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity High Level Level Analog Input Channels Programmable Gain Both Inputs Gains from Differential Input Level Channel Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single- Dual-Supply Operation Power typ) with Power-Down Mode (100 typ) APPLICATIONS Process Control Smart Transmitters Portable Industrial Instruments GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VBIAS
AVDD
2.5V REFERENCE CHARGE-BALANCING CONVERTER AUTO-ZEROED MODULATOR DIGITAL FILTER SYNC STANDBY MCLK MCLK
AIN1(+) AIN1(-)
AIN2
VOLTAGE ATTENUATION
CLOCK GENERATION SERIAL INTERFACE
AD7712
CONTROL REGISTER
OUTPUT REGISTER
AGND DGND MODE SDATA SCLK DRDY
AD7712 complete analog front frequency measurement applications. device analog input channels accepts either level signals directly from transducer high level VREF) signals, outputs serial digital word. employs sigma-delta conversion technique realize bits missing codes performance. level input signal applied proprietary programmable gain front based around analog modulator. high level analog input attenuated before being applied same modulator. modulator output processed on-chip digital filter. first notch this digital filter programmed on-chip control register, allowing adjustment filter cutoff settling time. Normally, channels will used main channel with second channel used auxiliary input periodically measure second voltage. part operated from single supply tying AGND), provided that input signals level analog input more positive than taking negative, part convert signals down -VREF this level input. This level input, well reference input, features differential input capability. AD7712 ideal smart, microcontroller based systems. Input channel selection, gain settings, signal polarity configured software using bidirectional serial
*Protected U.S. Patent 5,134,401.
port. AD7712 also contains self-calibration, system calibration, background calibration options, allows user read write on-chip calibration registers. CMOS construction ensures power dissipation, hardware programmable power-down mode reduces standby power consumption only typical. part available 24-lead, inch wide, plastic hermetic dual-in-line package (DIP), well 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
level analog input channel allows AD7712 accept input signals directly from strain gage transducer, removing considerable amount signal conditioning. maximize flexibility part, high level analog input accepts signals VREF/GAIN. AD7712 ideal microcontroller processor applications with on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity, calibration modes. AD7712 allows user read write on-chip calibration registers. This means that microcontroller much greater control over calibration procedure. missing codes ensures true, usable, 23-bit dynamic range coupled with excellent 0.0015% accuracy. effects temperature drift eliminated on-chip self-calibration, which removes zero-scale full-scale errors.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2004 Analog Devices, Inc. rights reserved.
AD7712-SPECIFICATIONS stated.=All+5specifications IN(-) AGND; MCLK unless otherwise
MAX,
IN(+) +2.5 unless otherwise noted.)
Parameter STATIC PERFORMANCE Missing Codes
Versions1 Tables 0.0015 0.003 0.25 0.25 0.003 0.006 AVDD Table VREF10 VREF VREF10 VREF 0.05 fCLK IN/256
Unit Bits Bits Bits Bits Bits µV/°C µV/°C µV/°C µV/°C µV/°C µV/°C ppm/°C µV/°C µV/°C
Conditions/Comments Guaranteed Design. Filter Notches Filter Notch Filter Notch Filter Notch Filter Notch Depends Filter Cutoffs Selected Gain Filter Notches Typically 0.0003% Excluding Reference Excluding Reference. Gains Excluding Reference. Gains Gains Gains Gains Gains Excluding Reference Typically 0.0006% Excluding Reference. Gains Excluding Reference. Gains Filter Notches 0.02 Filter Notches 0.02 fNOTCH fNOTCH
Output Noise Integral Nonlinearity 25°C TMIN TMAX Positive Full-Scale Error2, Full-Scale Drift5 Unipolar Offset Error2, Unipolar Offset Drift5 Bipolar Zero Error2, Bipolar Zero Drift5 Gain Drift Bipolar Negative Full-Scale Error2 25°C TMIN TMAX Bipolar Negative Full-Scale Drift5 ANALOG INPUTS/REFERENCE INPUTS Normal-Mode Rejection6 Normal-Mode Rejection6 AIN1/REF Input Leakage Current 25°C6 TMIN TMAX Sampling Capacitance6 Common-Mode Rejection (CMR) Common-Mode Rejection6 Common-Mode Rejection6 Common-Mode Voltage Range7 Analog Inputs8 Input Sampling Rate, AIN1 Input Voltage Range9
AVDD AVDD Filter Notches 0.02 Filter Notches 0.02
fNOTCH fNOTCH
ppm/°C µV/°C
AIN2 Input Voltage Range9
Normal Operation. Depends Gain Selected Unipolar Input Range (B/U Control Register Bipolar Input Range (B/U Control Register Normal Operation. Depends Gain Selected Unipolar Input Range (B/U Control Register Bipolar Input Range (B/U Control Register Additional Error Contributed Resistor Attenuator Additional Drift Contributed Resistor Attenuator Additional Error Contributed Resistor Attenuator
AIN2 Input Impedance AIN2 Gain Error11 AIN2 Gain Drift AIN2 Offset Error11 AIN2 Offset Drift Reference Inputs IN(+) IN(-) Voltage12 Input Sampling Rate,
Specified Performance. Part Functional with Lower VREF Voltages
NOTES Temperature range follows: Version, -40°C +85°C; Version -55°C +125°C. also Note Applies after calibration temperature interest. Positive full-scale error applies both unipolar bipolar input ranges. These errors will order output noise part shown Table after system calibration. These errors will typical after self-calibration background calibration. Recalibration temperature background calibration mode will remove these drift errors. These numbers guaranteed design and/or characterization. This common-mode voltage range allowed, provided that input voltage AIN1(+) AIN1(-) does exceed AIN1 analog input presents very high impedance dynamic load that varies with clock frequency input sample rate. maximum recommended source resistance depends selected gain (see Tables analog input voltage range AIN1(+) input given here with respect voltage AIN1(-) input. input voltage range AIN2 input with respect AGND. absolute voltage AIN1 input should more positive than more negative than VREF IN(+) IN(-). This error removed using system calibration capabilities AD7712. This error removed AD7712's self-calibration features. offset drift AIN2 input times value given Static Performance section. reference input voltage range restricted input voltage range requirement BIAS input.
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AD7712
SPECIFICATIONS (continued)
Parameter REFERENCE OUTPUT Output Voltage Initial Tolerance Drift Output Noise Line Regulation (AVDD) Load Regulation External Current VBIAS INPUT13 Input Voltage Range Versions1 AVDD 0.85 VREF AVDD AVDD 0.85 VREF VBIAS Rejection LOGIC INPUTS Input Current Inputs except MCLK VINL, Input Voltage VINH, Input High Voltage MCLK Only VINL, Input Voltage VINH, Input High Voltage LOGIC OUTPUTS VOL, Output Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance14 TRANSDUCER BURNOUT Current Initial Tolerance Drift SYSTEM CALIBRATION AIN1 Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16, Input Span15 AIN2 Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit17 Input Span15 Unit ppm/°C mV/V mV/mA Conditions/Comments pk-pk Noise; Bandwidth Maximum Load Current
%/°C
VBIAS Input Section Whichever Smaller: V/-5 Nominal AVDD/VSS Whichever Smaller: Nominal AVDD/VSS VBIAS Input Section Whichever Greater: V/-5 Nominal AVDD/VSS Whichever Greater: Nominal AVDD/VSS Increasing with Gain
ISINK ISOURCE
(1.05 VREF)/GAIN -(1.05 VREF)/GAIN -(1.05 VREF)/GAIN VREF/GAIN (2.1 VREF)/GAIN (4.2 VREF)/GAIN -(4.2 VREF)/GAIN -(4.2 VREF)/GAIN VREF/GAIN (8.4 VREF)/GAIN
GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128)
NOTES AD7712 tested with following BIAS voltages. With VBIAS with AVDD VBIAS with AVDD VBIAS Guaranteed design, production tested. After calibration, analog input exceeds positive full scale, converter will output analog input less than negative full scale, then device will output These calibration span limits apply provided absolute voltage AIN1 analog inputs does exceed does more negative than offset calibration limit applies both unipolar zero point bipolar zero point.
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AD7712-SPECIFICATIONS
Parameter POWER REQUIREMENTS Power Supply Voltages AVDD Voltage18 DVDD Voltage19 AVDD Voltage Power Supply Currents AVDD Current DVDD Current Current Power Supply Rejection Positive Supply (AVDD DVDD)21 Negative Supply (VSS) Power Dissipation Normal Mode Normal Mode Standby (Power-Down) Mode Versions1 Unit Conditions/Comments +10.5 52.5 AVDD DVDD Typically AVDD DVDD Typically AVDD DVDD Typically Specified Performance Specified Performance Specified Performance
Rejection w.r.t. AGND; Assumes BIAS Fixed
NOTES AD7712 specified with clock voltages specified with clock voltages greater than 5.25 less than 10.5 Operating with voltages range 5.25 10.5 guaranteed only over temperature range. tolerance input allowed provided that does exceed more than Measured applies selected passband. PSRR will exceed with filter notches PSRR will exceed with filter notches PSRR depends gain: gain typ; gain typ; gain typ; gains typ. These numbers improved typ) deriving BIAS voltage (via Zener diode reference) from supply. Using hardware STANDBY pin. Standby power dissipation using software standby (PD) Control Register typ. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
25°C, unless otherwise noted.)
AVDD DVDD -0.3 AVDD -0.3 AVDD AGND -0.3 AVDD DGND -0.3 DVDD AGND -0.3 DVDD DGND -0.3 AGND +0.3 DGND +0.3 AIN1 Input Voltage AGND AVDD Reference Input Voltage AGND AVDD AGND -0.3 AVDD
Digital Input Voltage DGND -0.3 AVDD Digital Output Voltage DGND -0.3 DVDD Operating Temperature Range Commercial Version) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) 300°C Power Dissipation (Any Package) 75°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD7712AN AD7712AR AD7712AR-REEL AD7712AR-REEL7 AD7712AQ AD7712SQ EVAL-AD7712EB
Temperature Range Package Options* -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C Evaluation Board N-24 RW-24 RW-24 RW-24 Q-24 Q-24
PDIP, CERDIP; SOIC.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7712 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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AD7712 TIMING
Parameter fCLK
AVDD AGND (DVDD MHz; Input Logic 0+10Logic 15%;DVSS ,=unless otherwise noted.) DGND CHARACTERISTICS fCLKIN
Limit TMIN, TMAX Versions) Unit Conditions/Comments Master Clock Frequency: Crystal Oscillator Externally Supplied AVDD Specified Performance AVDD 5.25 10.5 Master Clock Input Time; tCLK 1/fCLK Master Clock Input High Time Digital Output Rise Time; Typically Digital Output Fall Time; Typically SYNC Pulse Width DRDY Setup Time; tCLK 1/fCLK DRDY Hold Time Setup Time Hold Time SCLK Falling Edge Data Access Time (RFS Data Valid) SCLK Falling Edge Data Valid Delay SCLK High Pulse Width SCLK Pulse Width Setup Time Hold Time SCLK Falling Edge Delay Time SCLK Falling Edge Hold Time Data Valid SCLK Setup Time Data Valid SCLK Hold Time
tCLK tCLK Self-Clocking Mode
tCLK tCLK 1000 tCLK tCLK tCLK tCLK IN/2 tCLK IN/2 tCLK IN/2 tCLK IN/2 tCLK tCLK
NOTES Guaranteed design, production tested. Sample tested during initial release after redesign process change that affect this parameter. input signals specified with (10% timed from voltage level Figures AD7712 specified with clock voltages specified with clock voltages greater than 5.25 less than 10.5 duty cycle range 55%. must supplied whenever AD7712 STANDBY mode. clock present this case, device draw higher current than specified possibly become uncalibrated. AD7712 production tested with 5.25 guaranteed characterization operate kHz. Specified using points waveform interest. These numbers measured with load circuit Figure defined time required output cross
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AD7712 TIMING CHARACTERISTICS (continued)
Parameter External Clocking Mode fSCLK t247 t257 t298 t318 Limit TMIN, TMAX Versions) fCLK IN/5 tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK IN/2 tCLK tCLK SCLK High Unit Conditions/Comments Serial Clock Input Frequency DRDY Setup Time DRDY Hold Time Setup Time Hold Time Data Access Time (RFS Data Valid) SCLK Falling Edge Data Valid Delay SCLK High Pulse Width SCLK Pulse Width SCLK Falling Edge DRDY High SCLK Data Valid Hold Time RFS/TFS SCLK Falling Edge Hold Time Data Valid Hold Time Setup Time Hold Time SCLK Falling Edge Hold Time Data Valid SCLK Setup Time Data Valid SCLK Hold Time
NOTES These numbers derived from measured time taken data output change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that times quoted timing characteristics true relinquish times part and, such, independent external loading capacitances. Specifications subject change without notice.
CONFIGURATION SOIC
SCLK MCLK MCLK
OUTPUT 100pF 2.1V
DGND DVDD SDATA DRDY
1.6mA
SYNC MODE AIN1(+) AIN1(-)
VIEW (Not Scale) AGND
AIN2 IN(+) IN(-) VBIAS
AD7712
STANDBY
Figure Load Circuit Access Time Relinquish Time
AVDD
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AD7712
FUNCTION DESCRIPTION
Mnemonic SCLK
Function Serial Clock. Logic input/output, depending status MODE pin. When MODE high, device self-clocking mode, SCLK provides serial clock output. This SCLK becomes active when goes low, goes high impedance when either returns high when device completed transmission output word. When MODE low, device external clocking mode, SCLK acts input. This input serial clock continuous clock with data transmitted continuous train pulses. Alternatively, noncontinuous clock with information being transmitted AD7712 smaller batches data. Master Clock Signal Device. This provided form crystal external clock. crystal tied across MCLK MCLK pins. Alternatively, MCLK driven with CMOS-compatible clock MCLK left unconnected. clock input frequency nominally MHz. When master clock device crystal, crystal connected between MCLK MCLK OUT. Address Input. With this input low, reading writing device control register. With this input high, access either data register calibration registers. Logic Input. Allows synchronization digital filters when using number AD7712s. resets nodes digital filter. Logic Input. When this high, device self-clocking mode. With this low, device external clocking mode. Analog Input Channel Positive input programmable gain differential analog input. AIN1(+) input connected output current source that used check that external transducer burned gone open circuit. This output current source turned on/off control register. Analog Input Channel Negative input programmable gain differential analog input. Logic Input. Taking this shuts down internal analog digital circuitry, reducing power consumption less than Test Pin. Used when testing device. connect anything this pin. Analog Negative Supply, Tied AGND single-supply operation. input voltage AIN1 should negative w.r.t. correct operation device. Analog Positive Supply Voltage, Input Bias Voltage. This input voltage should such that VBIAS 0.85 VREF AVDD VBIAS 0.85 VREF where VREF IN(+) IN(-). Ideally, this should tied halfway between AVDD VSS. Thus, with AVDD tied OUT; with AVDD tied AGND, while with AVDD tied Reference Input. IN(-) anywhere between AVDD provided IN(+) greater than IN(-). Reference Input. reference input differential providing that IN(+) greater than IN(-). IN(+) anywhere between AVDD VSS. Reference Output. internal reference provided this pin. This single-ended output that referred AGND. Analog Input Channel High level analog input that accepts analog input voltage range VREF/GAIN. nominal VREF +2.5 gain AIN2 input voltage range Ground Reference Point Analog Circuitry. Transmit Frame Synchronization. Active logic input used write serial data device with serial data expected after falling edge this pulse. self-clocking mode, serial clock becomes active after goes low. external clocking mode, must before first data-word written part. Receive Frame Synchronization. Active logic input used access serial data from device. self-clocking mode, both SCLK SDATA lines become active after goes low. external clocking mode, SDATA line becomes active after goes low.
MCLK
MCLK SYNC MODE AIN1(+)
AIN1(-) STANDBY AVDD VBIAS
IN(-) IN(+) AIN2 AGND
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AD7712
Mnemonic DRDY Function Logic Output. falling edge indicates that output word available transmission. DRDY will return high upon completion transmission full output word. DRDY also used indicate when AD7712 completed on-chip calibration sequence. Serial Data. Input/output with serial data being written either control register calibration registers serial data being accessed from control register, calibration registers, data register. During output data read operation, serial data becomes active after goes (provided DRDY low). During write operation, valid serial data expected rising edges SCLK when low. output data coding natural binary unipolar inputs offset binary bipolar inputs. Digital Supply Voltage, DVDD should exceed AVDD more than normal operation. Ground Reference Point Digital Circuitry.
SDATA
DVDD DGND
TERMINOLOGY Integral Nonlinearity
Positive Full-Scale Overrange
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero-scale (not confused with bipolar zero), point below first code transition (000 001) full scale, point above last code transition (111 111). error expressed percentage full scale.
Positive Full-Scale Error
Positive full-scale overrange amount overhead available handle input voltages AIN1(+) input greater than (AIN1(-) VREF/GAIN) AIN2 greater than VREF/GAIN (for example, noise peaks excess voltages system gain errors system calibration routines) without introducing errors overloading analog modulator overflowing digital filter.
Negative Full-Scale Overrange
Positive full-scale error deviation last code transition (111 111) from ideal input full-scale voltage. AIN1(+), ideal full-scale input voltage (AIN1(-) VREF/GAIN LSBs); AIN2, ideal fullscale voltage VREF/GAIN LSBs. Positive full-scale error applies both unipolar bipolar analog input ranges.
Unipolar Offset Error
This amount overhead available handle voltages AIN1(+) below (AIN1(-) VREF/GAIN) AIN2 below VREF/GAIN without overloading analog modulator overflowing digital filter. Note that analog input will accept negative voltage peaks AIN1(+) even unipolar mode provided that AIN1(+) greater than AIN1(-) greater than
Offset Calibration Range
Unipolar offset error deviation first code transition from ideal voltage. AIN1(+), ideal input voltage (AIN1(-) LSB); AIN2, ideal input when operating unipolar mode.
Bipolar Zero Error
system calibration modes, AD7712 calibrates offset with respect analog input. offset calibration range specification defines range voltages that AD7712 accept still accurately calibrate offset.
Full-Scale Calibration Range
This deviation midscale transition (0111 1000 000) from ideal input voltage. AIN1(+), ideal input voltage (AIN1(-) LSB); AIN2, ideal input -0.5 when operating bipolar mode.
Bipolar Negative Full-Scale Error
This range voltages that AD7712 accept system calibration mode still correctly calibrate full scale.
Input Span
This deviation first code transition from ideal input voltage. AIN1(+), ideal input voltage (AIN1(-) VREF/GAIN LSB); AIN2, ideal input voltage VREF/GAIN LSB) when operating bipolar mode.
system calibration schemes, voltages applied sequence AD7712's analog input define analog input range. input span specification defines minimum maximum input voltages from zero full scale that AD7712 accept still accurately calibrate gain.
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AD7712
Control Register Bits)
write device with input writes data control register. read device with input accesses contents control register. control register bits wide when writing register bits data must written otherwise data will loaded control register. other words, possible write just first bits data into control register. more than clock pulses provided before returns high, then clock pulses after 24th clock pulse ignored. Similarly, read operation from control register should access bits data. FS11 FS10
Don't Care.
Operating Mode Operating Mode Normal Mode. This normal mode operation device whereby read device accesses data from data register. This default condition these bits after internal power-on reset. Activate Self-Calibration. This activates self-calibration channel selected This one-step calibration sequence, when complete, part returns normal mode (with MD2, MD1, control registers returning DRDY output indicates when this self-calibration complete. this calibration type, zero-scale calibration done internally shorted (zeroed) inputs, full-scale calibration done VREF. Activate System Calibration. This activates system calibration channel selected This two-step calibration sequence, with zero-scale calibration done first selected input channel DRDY indicating when this zero-scale calibration complete. part returns normal mode this first step two-step sequence. Activate System Calibration. This second step system calibration sequence with full-scale calibration being performed selected input channel. Once again, DRDY indicates when fullscale calibration complete. When this calibration complete, part returns normal mode. Activate System Offset Calibration. This activates system offset calibration channel selected This one-step calibration sequence and, when complete, part returns normal mode with DRDY indicating when this system offset calibration complete. this calibration type, zero-scale calibration done selected input channel, full-scale calibration done internally VREF. Activate Background Calibration. This activates background calibration channel selected background calibration mode then AD7712 provides continuous self-calibration reference shorted (zeroed) inputs. This calibration takes place part conversion sequence, extending conversion time reducing word rate factor major advantage that user does have worry about recalibrating device when there change ambient temperature. this mode, shorted (zeroed) inputs VREF, well analog input voltage, continuously monitored, calibration registers device automatically updated. Read/Write Zero-Scale Calibration Coefficients. read device with high accesses contents zero-scale calibration coefficients channel selected write device with high writes data zero-scale calibration coefficients channel selected word length reading writing these coefficients bits, regardless status control register. Therefore, when writing calibration register, bits data must written; otherwise data will transferred calibration register. Read/Write Full-Scale Calibration Coefficients. read device with high accesses contents full-scale calibration coefficients channel selected write device with high writes data full-scale calibration coefficients channel selected word length reading writing these coefficients bits, regardless status control register. Therefore, when writing calibration register, bits data must written; otherwise data will transferred calibration register.
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AD7712
Gain Gain
(Default Condition after Internal Power-On Reset)
Channel Selection
Channel AIN1 AIN2 Level Input High Level Input (Default Condition after Internal Power-On Reset)
Power-Down
Normal Operation Power-Down
(Default Condition after Internal Power-On Reset)
Word Length Output Word Length
16-Bit 24-Bit
(Default Condition after Internal Power-On Reset)
Burnout Current
(Default Condition after Internal Power-On Reset)
Bipolar/Unipolar Selection (Both Inputs)
Bipolar Unipolar
(Default Condition after Internal Power-On Reset)
Filter Selection (FS11-FS0)
on-chip digital filter provides sinc3 (sinx/x)3) filter response. bits data programmed into these bits determine filter cutoff frequency, position first notch filter, data rate part. association with gain selection, also determines output noise (and therefore effective resolution) device. first notch filter occurs frequency determined relationship filter first notch frequency (fCLK IN/512)/code where code decimal equivalent code bits FS11 range 2,000. With nominal fCLK MHz, this results first notch frequency range from 9.76 1.028 kHz. ensure correct operation AD7712, value code loaded these bits must within this range. Failure this will result unspecified operation device. Changing filter notch frequency, well selected gain, impacts resolution. Tables Figure show effect filter notch frequency gain effective resolution AD7712. output data rate effective conversion time) device equal frequency selected
first notch filter. example, first notch filter selected then word available rate every first notch kHz, word available every settling time filter full-scale step input change worst case 1/(output data rate). This settling time 100% final value. example, with first filter notch settling time filter full-scale step input change max. first notch kHz, settling time filter full-scale input step max. This settling time reduced l/(output data rate) synchronizing step input change reset digital filter. other words, step input takes place with SYNC low, settling time will l/(output data rate). change channels takes place, settling time l/(output data rate) regardless SYNC input. frequency determined programmed first notch frequency according relationship filter frequency 0.262 first notch frequency.
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AD7712
Tables show output noise some typical notch frequencies. numbers given bipolar input ranges with VREF These numbers typical generated with analog input voltage output noise from part comes from sources. First, there electrical noise semiconductor devices used implementation modulator (device noise). Second, when analog input signal converted into digital domain, quantization noise added. device noise level largely independent frequency. quantization noise starts even lower level rises rapidly with increasing frequency become dominant noise source. Consequently, lower filter notch settings (below approximately) tend device noise dominated while higher notch settings dominated quantization noise. Changing filter notch cutoff frequency quantization noise dominated region results more dramatic improvement noise performance than does device noise dominated region shown Table Furthermore, quantization noise added after PGA, effective resolution independent gain higher filter notch frequencies. Meanwhile, device noise added and, therefore, effective resolution suffers little high gains lower notch frequencies. lower filter notch settings (below Hz), missing codes performance device 24-bit level. higher settings, more codes will missed until notch setting; missing codes performance guaranteed only 12-bit level. However, since effective resolution part 10.5 bits this filter notch setting, this missing codes performance should more than adequate applications. effective resolution device defined ratio output noise input full scale. This does remain constant with increasing gain with increasing bandwidth. Table same Table except that output expressed terms effective resolution (the magnitude noise with respect VREF/GAIN, i.e., input full scale). possible post filtering device improve output data rate given frequency further reduce output noise (see Digital Filtering section).
Table Output Noise Gain First Notch Frequency
First Notch Filter Gain Data Rate1 Frequency
kHz3 2.62 6.55 7.86 13.1 15.72 26.2 65.5 4.33 5.28
Typical Output Noise
Gain
0.78 1.31 2.06 2.36 0.26
Gain
0.48 0.63 0.84 1.33
Gain
0.33 0.57 0.64 0.87 0.29
Gain
0.25 0.44 0.46 0.54 0.63
Gain
0.25 0.41 0.43 0.46 0.62
Gain
0.25 0.38 0.46 0.65
Gain
0.25 0.38 0.46 0.56 0.65
NOTES default condition (after internal power-on reset) first notch filter these filter notch frequencies, output noise primarily dominated device noise, and, result, independent value reference voltage. Therefore, increasing reference voltage will give increase effective resolution device (i.e., ratio noise input full scale increased since output noise remains constant input full scale increases). these filter notch frequencies, output noise dominated quantization noise, and, result, proportional value reference voltage.
Table Effective Resolution Gain First Notch Frequency First Notch Filter Data Rate Frequency 2.62 6.55 7.86 13.1 15.72 26.2 65.5 Effective Resolution* (Bits) Gain 22.5 21.5 18.5 10.5 Gain 21.5 18.5 15.5 10.5 Gain 21.5 20.5 18.5 15.5 Gain 19.5 18.5 15.5 Gain 20.5 19.5 19.5 15.5 Gain 19.5 18.5 18.5 18.5 17.5 15.5 12.5 10.5 Gain 18.5 17.5 17.5 17.5 12.5 Gain 17.5 16.5 16.5 16.5 14.5 12.5
*Effective resolution defined magnitude output noise with respect input full scale (i.e., VREF resolution numbers rounded nearest LSB.
VREF/GAIN). above table applies
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AD7712
Figures give information similar that outlined Table these plots, output noise shown full range available cutoffs frequencies rather than some typical cutoff frequencies Tables numbers given these plots typical values 25°C.
10000 GAIN 1000 GAIN GAIN
1000
GAIN
OUTPUT NOISE
GAIN GAIN GAIN
OUTPUT NOISE
GAIN
1000 NOTCH FREQUENCY 10000
1000
10000
NOTCH FREQUENCY
Figure Plot Output Noise Gain Notch Frequency (Gains
CIRCUIT DESCRIPTION
Figure Plot Output Noise Gain Notch Frequency (Gains 128)
AD7712 sigma-delta converter with on-chip digital filtering, intended measurement wide dynamic range, frequency signals such those industrial control process control applications. contains sigma-delta chargebalancing) ADC, calibration microcontroller with on-chip static RAM, clock oscillator, digital filter, bidirectional serial communications port. part contains analog input channels, programmable gain differential input, programmable gain high level single-ended input. gain range both inputs from 128. AIN1 input, this means that input accept unipolar signals between +2.5 bipolar signals range from when reference input voltage equals input voltage range AIN2 input VREF/GAIN with nominal reference gain input signal selected analog input channel continuously sampled rate determined frequency master clock, MCLK selected gain (see Table III). chargebalancing converter (sigma-delta modulator) converts sampled signal into digital pulse train whose duty cycle contains digital information. programmable gain function analog input also incorporated this sigmadelta modulator with input sampling frequency being modified give higher gains. sinc3 digital low-pass filter processes output sigma-delta modulator updates output register rate determined first notch frequency this filter. output data read from serial port randomly periodically rate output register update rate. first notch this digital filter (and therefore frequency) programmed on-chip control register. programmable range this first notch frequency from 9.76 1.028 kHz, giving programmable range frequency 2.58
basic connection diagram part shown Figure This shows AD7712 external clocking mode with both AVDD DVDD pins AD7712 being driven from analog supply. Some applications will have separate supplies both AVDD DVDD, some these cases, analog supply will exceed digital supply (see Power Supplies Grounding section).
ANALOG SUPPLY
AVDD
DVDD DRDY DATA READY TRANSMIT (WRITE) RECEIVE (READ) SERIAL DATA SERIAL CLOCK ADDRESS INPUT
DIFFERENTIAL ANALOG INPUT SINGLE-ENDED ANALOG INPUT
AIN1(+) AIN1(-) AIN2
AD7712
SDATA SCLK MODE
DVDD ANALOG GROUND DIGITAL GROUND
STANDBY AGND DGND IN(+) BIAS IN(-)
SYNC MCLK
MCLK
Figure Basic Connection Diagram
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AD7712
AD7712 provides number calibration options that programmed on-chip control register. calibration cycle initiated time writing this control register. part perform self-calibration using on-chip calibration microcontroller SRAM store calibration parameters. Other system components also included calibration loop remove offset gain errors input channel using system calibration mode. Another option background calibration mode where part continuously performs self-calibration updates calibration coefficients. Once part this mode, user does have worry about issuing periodic calibration commands device asking device recalibrate when there change ambient temperature power supply voltage. AD7712 gives user access on-chip calibration registers, allowing microprocessor read device's calibration coefficients also write calibration coefficients part from prestored values E2PROM. This gives microprocessor much greater control over AD7712's calibration procedure. also means that user verify that device performed calibration correctly comparing coefficients after calibration with prestored values E2PROM. AD7712 operated single-supply systems, provided that analog input voltage AIN1 input does more negative than larger bipolar signals AIN1 input, required part. battery operation power systems, AD7712 offers standby mode (controlled STANDBY pin) that reduces idle power consumption typically
THEORY OPERATION
Oversampling fundamental operation sigma-delta ADCs. Using quantization noise formula ADC: (6.02 number bits 1.76) 1-bit comparator yields 7.78 AD7712 samples input signal frequency greater (see Table III). result, quantization noise spread over much wider frequency than that band interest. noise band interest reduced still further analog filtering modulator loop, which shapes quantization noise spectrum move most noise energy frequencies outside bandwidth interest. noise performance thus improved from this 1-bit level performance outlined Tables Figure output comparator provides digital input 1-bit DAC, that system functions negative feedback loop that tries minimize difference signal. digital data that represents analog input voltage contained duty cycle pulse train appearing output comparator. retrieved parallel binary data-word using digital filter. Sigma-delta ADCs generally described order analog low-pass filter. simple example first-order sigmadelta shown Figure This contains only first order low-pass filter integrator. also illustrates derivation alternative name these devices: charge-balancing ADCs.
DIFFERENTIAL AMPLIFIER COMPARATOR
general block diagram sigma-delta shown Figure contains following elements:
sample-hold amplifier differential amplifier subtracter analog low-pass filter 1-bit converter (comparator) 1-bit digital low-pass filter
COMPARATOR ANALOG LOW-PASS FILTER DIGITAL FILTER
Figure Basic Charge-Balancing
DIGITAL DATA
consists differential amplifier (whose output difference between analog input output 1-bit DAC), integrator, comparator. term charge balancing, comes from fact that this system negative feedback loop that tries keep charge integrator capacitor zero balancing charge injected input voltage with charge injected 1-bit DAC. When analog input zero, only contribution integrator output comes from 1-bit DAC. charge integrator capacitor zero, output must spend half time half time -FS. Assuming ideal components, duty cycle comparator will 50%. When positive analog input applied, output 1-bit must spend larger proportion time +FS, duty cycle comparator increases. When negative input voltage applied, duty cycle decreases. AD7712 uses second-order sigma-delta modulator digital filter that provides rolling average sampled output. After power-up, there step change input voltage, there settling time that must elapse before valid data obtained.
Figure General Sigma-Delta
operation, analog signal sample subtracter, along with output 1-bit DAC. filtered difference signal comparator, whose output samples difference signal frequency many times that analog signal sampling frequency (oversampling).
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AD7712
Input Sample Rate
modulator sample frequency device remains fCLK IN/512 (19.5 fCLK MHz) regardless selected gain. However, gains greater than achieved combination multiple input samples modulator cycle scaling ratio reference capacitor input capacitor. result multiple sampling, input sample rate device varies with selected gain (see Table III). effective input impedance where input sampling capacitance input sample rate.
Table III. Input Sampling Frequency Gain
GAIN
-100 -120 -140 -160 -180 -200 -220
Gain
Input Sampling Frequency (fS) fCLK IN/256 fCLK MHz) fCLK IN/256 fCLK MHz) fCLK IN/256 (156 fCLK MHz) fCLK IN/256 (312 fCLK MHz) fCLK IN/256 (312 fCLK MHz) fCLK IN/256 (312 fCLK MHz) fCLK IN/256 (312 fCLK MHz) fCLK IN/256 (312 fCLK MHz)
-240 FREQUENCY
Figure Frequency Response AD7712 Filter
DIGITAL FILTERING
AD7712's digital filter behaves like similar analog filter, with minor differences. First, since digital filtering occurs after A-to-D conversion process, remove noise injected during conversion process. Analog filtering cannot this. other hand, analog filtering remove noise superimposed analog signal before reaches ADC. Digital filtering cannot this, noise peaks riding signals near full scale have potential saturate analog modulator digital filter, even though average value signal within limits. alleviate this problem, AD7712 overrange headroom built into sigma-delta modulator digital filter, which allows overrange excursions above analog input range. noise signals larger than this, consideration should given analog input filtering, reducing input channel voltage that full scale half that analog input channel full scale. This will provide overrange capability greater than 100% expense reducing dynamic range (50%).
Filter Characteristics
Since AD7712 contains this on-chip, low-pass filtering, there settling time associated with step function inputs, data output will invalid after step change until settling time elapsed. settling time depends upon notch frequency chosen filter. output data rate equates this filter notch frequency, settling time filter full-scale step input four times output data period. applications using both input channels, settling time filter must allowed elapse before data from second channel accessed.
Post Filtering
on-chip modulator provides samples 19.5 output rate. on-chip digital filter decimates these samples provide data output rate that corresponds programmed first notch frequency filter. Since output data rate exceeds Nyquist criterion, output rate given bandwidth will satisfy most application requirements. However, there some applications that require higher data rate given bandwidth noise performance. Applications that need this higher data rate will require some post filtering following digital filter AD7712. example, required bandwidth 7.86 required update rate data taken from AD7712 rate giving bandwidth 26.2 Post filtering applied this reduce bandwidth output noise, 7.86 bandwidth level, while maintaining output rate Post filtering also used reduce output noise from device bandwidths below 2.62 gain 128, output noise This essentially device noise white noise, since input chopped, noise flat frequency response. reducing bandwidth below 2.62 noise resultant passband reduced. reduction bandwidth factor results reduction output noise. This additional filtering will result longer settling time.
cutoff frequency digital filter determined value loaded bits FS11 control register. maximum clock frequency MHz, minimum cutoff frequency filter 2.58 while maximum programmable cutoff frequency Figure shows filter frequency response cutoff frequency 2.62 which corresponds first filter notch frequency This (sinx/x)3 response (also called sinc3), that provides >100 rejection. Programming different cutoff frequency FS0-FS11 does alter profile filter response; changes frequency notches outlined Control Register section.
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AD7712
Antialias Considerations
digital filter does provide rejection integer multiples modulator sample frequency 19.5 kHz, where This means that there frequency bands, wide cutoff frequency selected FS11), where noise passes unattenuated output. However, AD7712's high oversampling ratio, these bands occupy only small fraction spectrum, most broadband noise filtered. case, because high oversampling ratio, simple, single-pole filter generally sufficient attenuate signals these bands analog input thus provide adequate antialiasing filtering. passive components placed front AIN1 input AD7712, care must taken ensure that source impedance enough introduce gain errors system. input impedance AIN1 input over input appears dynamic load that varies with clock frequency with selected gain (see Figure input sample rate, shown Table III, determines time allowed analog input capacitor, CIN, charged. External impedances result longer charge time this capacitor, which result gain errors being introduced analog inputs. Table shows allowable external resistance/capacitance values such that gain error 16-bit level introduced, while Table shows allowable external resistance/capacitance values such that gain error 20-bit level introduced. Both inputs differential input channels (AIN1) look into similar input circuitry.
Table Typical External Series Resistance That Will Introduce 16-Bit Gain Error
Gain 8-128
88.6 41.4 17.6
External Capacitance (pF) 1000 45.3 22.1 10.6 27.1 13.2
5000
Table Typical External Series Resistance That Will Introduce 20-Bit Gain Error
Gain 8-128
70.5 31.8 13.4
External Capacitance (pF) 1000 34.5 16.9 20.4
5000
numbers Tables assume full-scale change analog input. case, error introduced longer charging times gain error that removed using system calibration capabilities AD7712 provided that resultant span within span limits system calibration techniques AD7712. AIN2 input contains resistive attenuation network outlined Figure typical input impedance this input result, AIN2 input should driven from impedance source.
RINT CINT (11.5pF TYP) VBIAS SWITCHING FREQUENCY DEPENDS fCLKIN SELECTED GAIN TYP) HIGH IMPEDANCE
AIN2
MODULATOR CIRCUIT
Figure AIN1 Input Impedance
VBIAS
Figure AIN2 Input Impedance
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AD7712
ANALOG INPUT FUNCTIONS Analog Input Ranges
analog inputs AD7712 provide user with considerable flexibility terms analog input voltage ranges. inputs differential, programmable gain, input channel that handle either unipolar bipolar input signals. common-mode range this input from AVDD provided that absolute value analog input voltage lies between AVDD second analog input single-ended, programmable gain, high level input that accepts analog input ranges VREF/GAIN VREF/GAIN. input leakage current AIN1 input maximum 25°C over temperature). This results offset voltage developed across source impedance. However, this offset effect compensated combination differential input capability part system calibration mode. input current AIN2 input depends input voltage. nominal input voltage range input current typ.
Burnout Current
external load. applications where connected directly IN(+), IN(-) should tied AGND provide nominal reference AD7712. reference inputs AD7712, IN(+) IN(-), provide differential reference input capability. common-mode range these differential inputs from AVDD. nominal differential voltage, VREF (REF IN(+) IN(-)), specified operation, reference voltage with degradation performance provided that absolute value IN(+) IN(-) does exceed AVDD limits VBIAS input voltage range limits obeyed. part also functional with VREF voltages down with degraded performance output noise will, terms size, larger. IN(+) must always greater than IN(-) correct operation AD7712. Both reference inputs provide high impedance, dynamic load similar AIN1 analog inputs. maximum input leakage current over temperature), source resistance result gain errors part. reference inputs look like AIN1 analog input (see Figure this case, RINT CINT varies with gain. input sample rate fCLK IN/256 does vary with gain. gains CINT gain gain gain gain 128, 1.25 digital filter AD7712 removes noise from reference input just does with analog input, same limitations apply regarding lack noise rejection integer multiples sampling frequency. output noise performance outlined Tables assumes clean reference. reference noise bandwidth interest excessive, degrade performance AD7712. Using on-chip reference reference source part (i.e., connecting results somewhat degraded output noise performance from AD7712 portions noise table that dominated device noise. on-chip reference noise effect eliminated ratiometric applications where reference used provide excitation voltage analog front end. connection scheme shown Figure between pins AD7712 recommended when using on-chip reference. Recommended reference voltage sources AD7712 include AD780 AD680 references.
AIN1(+) input AD7712 contains current source that turned on/off control register. This current source used checking that transducer burned gone open circuit before attempting take measurements that channel. current turned allowed flow into transducer measurement input voltage AIN1 input taken, indicate that transducer functioning correctly. normal operation, this burnout current turned writing control register.
Bipolar/Unipolar Inputs
analog inputs AD7712 accept either unipolar bipolar input voltage ranges. Bipolar unipolar options chosen programming control register. This programs both channels either unipolar bipolar operation. Programming part either unipolar bipolar operation does change input signal conditioning; simply changes data output coding. data coding binary unipolar inputs offset binary bipolar inputs. AIN1 input channel differential and, result, voltage which unipolar bipolar signals referenced voltage AIN1(-) input. example, AIN1(-) 1.25 AD7712 configured unipolar operation with gain VREF input voltage range AIN1(+) input 1.25 3.75 AIN1(-) 1.25 AD7712 configured bipolar mode with gain VREF analog input range AIN1(+) input -1.25 +3.75 AIN2 input, input signals referenced AGND.
REFERENCE INPUT/OUTPUT
IN(+) IN(-)
AD7712 contains temperature compensated reference, which initial tolerance This reference voltage provided OUT, used reference voltage part connecting IN(+) pin. This single-ended output, referenced AGND, which capable providing
AD7712
Figure OUT/REF Connection
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AD7712
VBIAS Input
VBIAS input determines what voltage internal analog circuitry biased. essentially provides return path analog currents flowing modulator, such should driven from impedance point minimize errors. maximum internal headroom, VBIAS voltage should halfway between AVDD VSS. difference between AVDD (VBIAS 0.85 VREF) determines amount headroom circuit upper end, while difference between (VBIAS 0.85 VREF) determines amount headroom circuit lower end. Care should taken choosing VBIAS voltage ensure that stays within prescribed limits. single operation, selected VBIAS voltage must ensure that VBIAS 0.85 VREF does exceed AVDD that VBIAS voltage itself greater than less than AVDD single operation dual operation, selected VBIAS voltage must ensure that VBIAS 0.85 VREF does exceed AVDD that VBIAS voltage itself greater than less than AVDD example, with AVDD +4.75 VREF +2.5 allowable range VBIAS voltage +2.125 +2.625 With AVDD +9.5 VREF range VBIAS +4.25 +5.25 With AVDD +4.75 -4.75 VREF +2.5 VBIAS range -2.625 +2.625 VBIAS voltage does have effect AVDD power supply rejection performance AD7712. VBIAS voltage tracks AVDD supply, improves power supply rejection from AVDD supply line from Using external Zener diode connected between AVDD line VBIAS source VBIAS voltage gives improvement AVDD power supply rejection performance.
USING AD7712 SYSTEM DESIGN CONSIDERATIONS
current drawn from DVDD power supply also directly related fCLK Reducing fCLK factor will halve DVDD current will affect current drawn from AVDD power supply.
System Synchronization
multiple AD7712s operated from common master clock, they synchronized update their output registers simultaneously. falling edge SYNC input resets filter places AD7712 into consistent, known state. common signal AD7712's SYNC inputs will synchronize their operation. This would normally done after each AD7712 performed calibration calibration coefficients loaded SYNC input also used reset digital filter systems where turn-on time digital power supply (DVDD) very long. such cases, AD7712 will start operating internally before DVDD line reached minimum operating level, 4.75 With DVDD voltage, AD7712's internal digital filter logic does operate correctly. Thus, AD7712 have clocked itself into incorrect operating condition time that DVDD reached correct level. digital filter will reset upon issue calibration command (whether self-calibration, system calibration, background calibration) AD7712. This ensures correct operation AD7712. systems where power-on default conditions AD7712 acceptable, calibration performed after power-on, issuing SYNC pulse AD7712 will reset AD7712's digital filter logic. SYNC line, with time constant longer than DVDD power-on time, will perform SYNC function.
Accuracy
AD7712 operates differently from successive approximation ADCs integrating ADCs. Since samples signal continuously, like tracking ADC, there need start convert command. output register updated rate determined first notch filter, output read time, either synchronously asynchronously.
Clocking
Sigma-delta ADCs, like VFCs other integrating ADCs, contain source nonmonotonicity inherently offer missing codes performance. AD7712 achieves excellent linearity high quality, on-chip silicon dioxide capacitors, which have very capacitance/voltage coefficient. device also achieves input drift through chopper stabilized techniques input stage. ensure excellent performance over time temperature, AD7712 uses digital calibration techniques that minimize offset gain error.
Autocalibration
AD7712 requires master clock input, which external TTL/CMOS compatible clock signal applied MCLK with MCLK left unconnected. Alternatively, crystal correct frequency connected between MCLK MCLK OUT, which case clock circuit will function crystal controlled oscillator. lower clock frequencies, ceramic resonator used instead crystal. these lower frequency oscillators, external capacitors required either ceramic resonator crystal. input sampling frequency, modulator sampling frequency, frequency, output update rate, calibration time directly related master clock frequency, fCLK Reducing master clock frequency factor will halve above frequencies update rate will double calibration time.
Autocalibration AD7712 removes offset gain errors from device. calibration routine should initiated device whenever there change ambient operating temperature supply voltage. should also initiated there change selected gain, filter notch, bipolar/unipolar input range. However, AD7712 background calibration mode, above changes automatically taken care (after settling time filter been allowed for). AD7712 offers self-calibration, system calibration, background calibration facilities. calibration occur selected channel, on-chip microcontroller must record modulator output different input conditions. These zero-scale full-scale points. With these readings, microcontroller calculate gain slope input output transfer function converter. Internally, part works with resolution bits determine conversion result either bits bits.
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AD7712
AD7712 also provides facility write on-chip calibration registers, and, this manner, span offset part adjusted user. offset calibration register contains value that subtracted from conversion results, while full-scale calibration register contains value that multiplied conversion results. offset calibration coefficient subtracted from result prior multiplication full-scale coefficient. first three modes outlined here, DRDY line indicates that calibration complete going low. DRDY before goes during) calibration command, take modulator cycle before DRDY goes high indicate that calibration progress. Therefore, DRDY line should ignored modulator cycle after last calibration command written control register.
Self-Calibration
unipolar mode, system calibration performed between endpoints transfer function; bipolar mode, performed between midscale positive full scale. This two-step system calibration mode offers another feature. After sequence been completed, additional offset gain calibrations performed themselves adjust zero reference point system gain. This achieved performing first step system calibration sequence writing MD2, MD1, MD0). This will adjust zero-scale offset point will change slope factor from what during full system calibration sequence. System calibration also used remove errors from antialiasing filter analog input. simple antialiasing filter front introduce gain error analog input voltage system calibration used remove this error.
System Offset Calibration
self-calibration mode with unipolar input range, zero-scale point used determining calibration coefficients with both inputs shorted (i.e., AIN1(+) AIN1(-) VBIAS AIN1 AIN2 VBIAS AIN2 full-scale point VREF. zero-scale coefficient determined converting internal shorted inputs node. full-scale coefficient determined from span between this shorted inputs conversion conversion internal VREF node. self-calibration mode invoked writing appropriate values MD2, MD1, bits control register. this calibration mode, shorted inputs node switched modulator first conversion performed; VREF node then switched another conversion performed. When calibration sequence complete, calibration coefficients updated filter resettled analog input voltage, DRDY output goes low. self-calibration procedure takes into account selected gain PGA. bipolar input ranges self-calibrating mode, sequence very similar that just outlined. this case, points that AD7712 calibrates midscale (bipolar zero) positive full scale.
System Calibration
System offset calibration variation both system calibration self-calibration. this case, zero-scale point system presented input converter. System offset calibration initiated writing MD2, MD1, MD0. system zero-scale coefficient determined converting voltage applied input, while fullscale coefficient determined from span between this conversion conversion VREF. zero-scale point should applied input duration calibration sequence. This one-step calibration sequence with DRDY going when sequence completed. unipolar mode, system offset calibration performed between endpoints transfer function; bipolar mode, performed between midscale positive full scale.
Background Calibration
System calibration allows AD7712 compensate system gain offset errors well internal errors. System calibration performs same slope factor calculations selfcalibration uses voltage values presented system inputs zero-scale full-scale points. System calibration two-step process. zero-scale point must presented converter first. must applied converter before calibration step initiated remain stable until step complete. System calibration initiated writing appropriate values MD2, MD1, bits control register. DRDY output from device will signal when step complete going low. After zero-scale point calibrated, full-scale point applied second step calibration process initiated again writing appropriate values MD2, MD1, MD0. Again full-scale voltage must before calibration initiated, must remain stable throughout calibration step. DRDY goes this second step indicate that system calibration complete.
AD7712 also offers background calibration mode where part interleaves calibration procedure with normal conversion sequence. background calibration mode, same voltages used calibration points self-calibration mode used, i.e., shorted inputs VREF. background calibration mode invoked writing MD2, MD1, control register. When invoked, background calibration mode reduces output data rate AD7712 factor while bandwidth remains unchanged. advantage that part continually performing calibration automatically updating calibration coefficients. result, effects temperature drift, supply sensitivity, time drift zero-scale full-scale errors automatically removed. When background calibration mode turned part will remain this mode until bits MD2, MD1, control register changed. With background calibration mode first result from AD7712 will incorrect full-scale calibration will have been performed. step change input, second output update will have settled 100% final value. Table summarizes calibration modes calibration points associated with them. also gives duration from when calibration invoked when valid data available user.
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AD7712
Table Calibration Truth Table
Type Self-Cal System System System Offset Background
MD2, MD1,
Zero-Scale Shorted Inputs Shorted Inputs
Full-Scale VREF VREF VREF
Sequence One-Step Two-Step Two-Step One-Step One-Step
Duration 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate
Span Offset Limits
Whenever system calibration mode used, there limits amount offset span that accommodated. range input span both unipolar bipolar modes AIN1 minimum value VREF/GAIN maximum value VREF/GAIN. AIN2, both numbers factor higher. amount offset that accommodated depends whether unipolar bipolar mode being used. This offset range limited requirement that positive full-scale calibration limit 1.05 VREF/GAIN AIN1. Therefore, offset range plus span range cannot exceed 1.05 VREF/ GAIN AIN1. span minimum (0.8 VREF/ GAIN), maximum offset (0.25 VREF/GAIN) AIN1. AIN2, both ranges multiplied factor bipolar mode, system offset calibration range again restricted span range. span range converter bipolar mode equidistant around voltage used zero-scale point, thus offset range plus half span range cannot exceed (1.05 VREF/GAIN) AIN1. span VREF/GAIN, offset span cannot move more than (0.05 VREF/GAIN) before endpoints transfer function exceed input overrange limits (1.05 VREF/GAIN) AIN1. span range minimum (0.4 VREF/ GAIN), maximum allowable offset range (0.65 VREF/
Measurement errors offset drift gain drift eliminated time recalibrating converter operating part background calibration mode. Using system calibration mode also minimize offset gain errors signal conditioning circuitry. Integral differential linearity errors significantly affected temperature changes.
POWER SUPPLIES GROUNDING
Since analog inputs reference input differential, most voltages analog modulator common-mode voltages. VBIAS provides return path most analog currents flowing analog modulator. result, VBIAS input should driven from impedance minimize errors charging/discharging impedances this line. When internal reference used reference source part, AGND ground return this reference voltage. analog digital supplies AD7712 independent separately pinned minimize coupling between analog digital sections device. digital filter will provide rejection broadband noise power supplies, except integer multiples modulator sampling frequency. digital supply (DVDD) must exceed analog positive supply (AVDD) more than normal operation. separate analog digital supplies used, decoupling scheme shown Figure recommended. systems where AVDD DVDD recommended that AVDD DVDD driven from same supply, although each supply should decoupled separately shown Figure preferable that common supply system's analog supply. also important that power applied AD7712 before signals AIN, logic input pins order avoid excessive current. separate supplies used AD7712 system digital circuitry, then AD7712 should powered first. possible guarantee this, then current limiting resistors should placed series with logic inputs.
ANALOG SUPPLY DIGITAL SUPPLY
GAIN) AIN1. Once again, AIN2, both ranges multiplied factor
POWER-UP CALIBRATION
power-up, AD7712 performs internal reset, which sets contents control register known state. However, ensure correct calibration device, calibration routine should performed after power-up. power dissipation temperature drift AD7712 warm-up time required before initial calibration performed. However, external reference being used, this reference must have stabilized before calibration initiated.
Drift Considerations
AD7712 uses chopper stabilization techniques minimize input offset drift. Charge injection analog switches leakage currents sampling node primary sources offset voltage drift converter. input leakage current essentially independent selected gain. Gain drift within converter depends primarily upon temperature tracking internal capacitors. affected leakage currents.
AVDD
DVDD
AD7712
Figure Recommended Decoupling Scheme
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AD7712
DIGITAL INTERFACE
AD7712's serial communications port provides flexible arrangement allow easy interfacing industry-standard microprocessors, microcontrollers, digital signal processors. serial read AD7712 access data from output register, control register, calibration registers. serial write AD7712 write data control register calibration registers. different modes operation available, optimized different types interfaces where AD7712 either master system provides serial clock) slave external serial clock provided AD7712). These modes, labeled self-clocking mode external clocking mode, discussed detail following sections.
Self-Clocking Mode
output data register. reset high when last data (either 16th 24th bit) read from output register. data read from output register, DRDY line will remain low. output register will continue updated output update rate, DRDY will indicate this. read from device this circumstance will access most recent word output register. data-word becomes available output register while data being read from output register, DRDY will indicate this dataword will lost user. DRDY affected reading from control register calibration registers. Data accessed from output data register only when DRDY low. goes with DRDY high, data transfer will take place. DRDY does have effect reading data from control register from calibration registers. Figure shows timing diagram reading from AD7712 self-clocking mode. This read operation shows read from AD7712's output data register. read from control register calibration registers similar, but, these cases, DRDY line related read function. Depending output update rate, stage control/calibration register read cycle without affecting read status should ignored. read operation from either control calibration registers must always read bits data from respective register. Figure shows read operation from AD7712. timing diagram shown, assumed that there pull-up resistor SCLK output. With DRDY low, input brought low. going enables serial clock AD7712 also places word serial data line. subsequent data bits clocked high transition serial clock valid prior following rising edge this clock. final active falling edge SCLK clocks LSB, this valid prior final active rising edge SCLK. Coincident with next falling edge SCLK, DRDY reset high. DRDY going high turns SCLK SDATA outputs, which means that data hold time slightly shorter than other bits.
AD7712 configured self-clocking mode tying MODE high. this mode, AD7712 provides serial clock signal used transfer data from AD7712. This self-clocking mode used with processors that allow external device clock their serial port, including most digital signal processors microcontrollers such 68HC11 68HC05. also allows easy interfacing serial parallel conversion circuits systems with parallel data communication, allowing interfacing 74XX299 universal shift registers without additional decoding. case shift registers, serial clock line should have pull-down resistor instead pull-up resistor shown Figures
Read Operation
Data read from output register, control register, calibration registers. determines whether data read accesses data from control register from output/calibration registers. This signal must remain valid duration serial read operation. With high, data accessed from either output register from calibration registers. With low, data accessed from control register. function DRDY line dependent only output update rate device reading output data register. DRDY goes when data-word available
DRDY
SCLK
SDATA
THREE-STATE
Figure Self-Clocking Mode, Output Data Read Operation
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AD7712
Write Operation
Data written either control register calibration registers. either case, write operation affected DRDY line, write operation does have effect status DRDY. write operation control register calibration register must always write bits respective register. Figure shows write operation AD7712. determines whether write operation transfers data control register calibration registers. This signal must remain valid duration serial write operation. falling edge enables internally generated SCLK output. serial data loaded AD7712 must valid rising edge this SCLK signal. Data clocked into AD7712 rising edge SCLK signal, with transferred first. last active high time SCLK, loaded AD7712. Subsequent next falling edge SCLK, SCLK output turned off. (The timing diagram Figure assumes pull-up resistor SCLK line.)
External Clocking Mode
register from calibration registers. With low, data accessed from control register. function DRDY line dependent only output update rate device reading output data register. DRDY goes when data-word available output data register. reset high when last data (either 16th 24th bit) read from output register. data read from output register, DRDY line will remain low. output register will continue updated output update rate, DRDY will indicate this. read from device this circumstance will access most recent word output register. data-word becomes available output register while data being read from output register, DRDY will indicate this, dataword will lost user. DRDY affected reading from control register calibration register. Data accessed from output data register only when DRDY low. goes while DRDY high, data transfer will take place. DRDY does have effect reading data from control register from calibration registers. Figures show timing diagrams reading from AD7712 external clocking mode. Figure shows situation where data read from AD7712 read operation. Figure shows situation where data read from AD7712 over number read operations. Both read operations show read from AD7712's output data register. Reads from control register calibration registers similar, but, these cases, DRDY line related read function. Depending output update rate, stage control/calibration register read cycle without affecting read, status should ignored. read operation from either control calibration registers must always read bits data from respective register.
AD7712 configured external clocking mode tying MODE low. this mode, SCLK AD7712 configured input, external serial clock must provided this SCLK pin. This external clocking mode designed direct interface systems that provide serial clock output that synchronized serial data output, including microcontrollers such 80C51, 87C51, 68HC11, 68HC05 most digital signal processors.
Read Operation
with self-clocking mode, data read from either output register, control register, calibration registers. determines whether data read accesses data from control register from output/calibration registers. This signal must remain valid duration serial read operation. With high, data accessed from either output
SCLK
SDATA
Figure Self-Clocking Mode, Control/Calibration Register Write Operation
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AD7712
Figure shows read operation from AD7712 where remains duration data word transmission. With DRDY low, input brought low. input SCLK signal should between read write operations. going places word read serial data line. subsequent data bits clocked high transition serial clock valid prior following rising edge this clock. penultimate falling edge SCLK clocks final falling edge resets DRDY line high. This rising edge DRDY turns serial data output. Figure shows timing diagram read operation where returns high during transmission word returns again access rest data-word. Timing parameters functions very similar that outlined Figure 13a, Figure number additional times show timing relationships when returns high middle transferring word. should return high during time SCLK. rising edge RFS, SDATA output turned off. DRDY remains will remain until bits data-word read from AD7712, regardless number times changes state during read operation. Depending time between falling edge SCLK rising edge RFS, next (BIT appear data before goes high. When returns again, activates SDATA output. When entire word transmitted, DRDY line will high, turning SDATA output Figure 13a.
DRDY
SCLK
SDATA
THREE-STATE
Figure 13a. External Clocking Mode, Output Data Read Operation
DRDY
SCLK
SDATA
THREE-STATE
Figure 13b. External Clocking Mode, Output Data Read Operation (RFS Returns High during Read Operation)
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AD7712
Write Operation
Data written either control register calibration registers. either case, write operation affected DRDY line, write operation does have effect status DRDY. write operation control register calibration register must always write bits respective register. Figure shows write operation AD7712 with remaining duration write operation. determines whether write operation transfers data control register calibration registers. This signal must remain valid duration serial write operation. before, serial clock line should between read write operations. serial data loaded AD7712 must valid high level externally applied SCLK signal. Data clocked into AD7712 high level this
SCLK signal with transferred first. last active high time SCLK, loaded AD7712. Figure shows timing diagram write operation AD7712 with returning high during write operation returning again write rest data word. Timing parameters functions very similar that outlined Figure 14a, Figure number additional times show timing relationships when returns high middle transferring word. Data loaded AD7712 must valid prior rising edge SCLK signal. should return high during time SCLK. After returns again, next data-word loaded AD7712 clocked next high level SCLK input. last active high time SCLK input, loaded AD7712.
SCLK
SDATA
Figure 14a. External Clocking Mode, Control/Calibration Register Write Operation
SCLK
SDATA
Figure 14b. External Clocking Mode, Control/Calibration Register Write Operation (TFS Returns High During Write Operation)
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AD7712
SIMPLIFYING EXTERNAL CLOCKING MODE INTERFACE
START
many applications, user require facility writing on-chip calibration registers. this case, serial interface AD7712 external clocking mode simplified connecting line input AD7712 (see Figure 15). This means that write device will load data control register (since while low), read device will access data from output data register from calibration registers (since high while low). should noted that this arrangement user does have capability reading from control register.
CONFIGURE INITIALIZE SERIAL PORT
BRING RFS, HIGH
POLL DRDY
FOUR INTERFACE LINES SDATA SCLK
BRING DRDY
AD7712
LOW?
Figure Simplified Interface with Connected
Another method simplifying interface generate signal from inverted signal. However, generating signals opposite around (RFS from inverted TFS) will cause writing errors.
MICROCOMPUTER/MICROPROCESSOR INTERFACING
READ SERIAL BUFFER
BRING HIGH
AD7712's flexible serial interface allows easy interface most microcomputers microprocessors. Figure shows flowchart diagram typical programming sequence reading data from AD7712 microcomputer while Figure shows flowchart diagram writing data AD7712. Figures show some typical interface circuits. flowchart Figure continuous read operations from AD7712 output register. example shown, DRDY line continuously polled. Depending microprocessor configuration, DRDY line come interrupt input, which case DRDY will automatically generate interrupt without being polled. Reading serial buffer could anything from read operation three read operations (where bits data read into 8-bit serial register). read operation control/calibration registers similar, but, this case, status DRDY ignored. line brought when line brought when reading from control register. flowchart also shows bits being reversed after they have been read from serial port. This depends whether microprocessor expects word first word first. AD7712 outputs first.
REVERSE ORDER BITS
Figure Flowchart Continuous Read Operations AD7712
flowchart Figure single 24-bit write operation AD7712 control calibration registers. This shows data being transferred from data memory accumulator before being written serial buffer. Some microprocessor systems will allow data written directly serial buffer from data memory. Writing data serial buffer from accumulator will generally consist either three write operations, depending size serial buffer. flowchart also shows option bits being reversed before being written serial buffer. This depends whether first transmitted microprocessor LSB. AD7712 expects first data stream. cases where data being read being written bytes data reversed, bits will have reversed every byte.
-24-
REV.
AD7712
START
CONFIGURE INITIALIZE SERIAL PORT
BRING RFS, HIGH
Table shows some typical 8XC51 code used single 24-bit read from output register AD7712. Table VIII shows some typical code single write operation control register AD7712. 8XC51 outputs first write operation while AD7712 expects first, data transmitted rearranged before being written output serial register. Similarly, AD7712 outputs first during read operation while 8XC51 expects first. Therefore, data that read into serial buffer needs rearranged before correct data-word from AD7712 available accumulator.
Table VII. 8XC51 Code Reading from AD7712
LOAD DATA FROM ADDRESS ACCUMULATOR
REVERSE ORDER BITS
BRING
WRITE DATA FROM ACCUMULATOR SERIAL BUFFER
BRING HIGH
Figure Flowchart Single Write Operation AD7712
AD7712 8051 Interface
Figure shows interface between AD7712 8XC51 microcontroller. AD7712 configured external clocking mode, while 8XC51 configured Mode serial interface mode. DRDY line from AD7712 connected Port P1.2 input 8XC51, DRDY line polled 8XC51. DRDY line connected INT1 input 8XC51 interrupt driven system preferred.
DVDD SYNC P1.0 P1.1 P1.2 P1.3 P3.0 P3.1 DRDY SDATA SCLK MODE
8XC51
AD7712
SCON,#00010001B; Configure 8051 MODE Operation IE,#00010000B; Disable Interrupts SETB 90H; P1.0, Used SETB 91H; P1.1, Used SETB 93H; P1.3, Used R1,#003H; Sets Number Bytes Read Read Operation R0,#030H; Start Address Where Bytes Will Loaded R6,#004H; P1.2 DRDY WAIT: NOP; A,P1; Read Port A,R6; Mask Bits Except DRDY READ; Zero Read SJMP WAIT; Otherwise Keep Polling READ: 90H; Bring 98H; Clear Receive Flag POLL: 98H, READ1 Tests Receive Interrupt Flag SJMP POLL READ A,SBUF; Read Buffer Rearrange Data B.0,C; Reverse Order Bits B.1,C; B.2,C; B.3,C; B.4,C; B.5,C; B.6,C; B.7,C; A,B; @R0,A; Write Data Memory Increment Memory Location Decrement Byte Counter A,R1 Jump Zero WAIT Fetch Next Byte END: SETB Bring High FIN: SJMP
Figure AD7712 8XC51 Interface
REV.
-25-
AD7712
Table VIII. 8XC51 Code Writing AD7712 SCON,#00000000B; IE,#10010000B; IP,#00010000B; SETB 91H; SETB 90H; R1,#003H; R0,#030H; A,#00H; SBUF,A; WAIT: WAIT; ROUTINE: NOP; A,R1; FIN; A,@R; Configure 8051 MODE Operation Enable Serial Reception Enable Transmit Interrupt Prioritize Transmit Interrupt Bring High Bring High Sets Number Bytes Written Write Operation Start Address Bytes Clear Accumulator Initialize Serial Port Wait Interrupt AD7712 68HC11 Interface
Figure shows interface between AD7712 68HC11 microcontroller. AD7712 configured external clocking mode, while port used 68HC11, which single-chip mode. DRDY line from AD7712 connected Port input 68HC11 DRDY line polled 68HC11. DRDY line connected input 68HC11, interrupt driven system preferred. 68HC11 MOSI MISO lines should configured wired-OR operation. Depending interface configuration, necessary provide bidirectional buffers between 68HC11 MOSI MISO lines. 68HC11 configured master mode with CPOL Logic CPHA Logic With master clock AD7712, interface will operate with four serial clock rates 68HC11.
DVDD DVDD SYNC DRDY
Interrupt Subroutine Load Accumulator Zero Jump Decrement Byte Counter Move Byte into Accumulator Increment Address Rearrange Data-From First First B.0,C; B.1,C; B.2,C; B.3,C; B.4,C; B.5,C; B.6,C; B.7,C; A,B; 93H; Bring 91H; Bring SBUF,A; Write Serial Port RETI; Return from Subroutine FIN: SETB 91H; High SETB 93H; High RETI; Return from Interrupt Subroutine
68HC11
MISO MOSI
AD7712
SCLK SDATA MODE
Figure AD7712 68HC11 Interface
-26-
REV.
AD7712
APPLICATIONS 4-20 LOOP
AD7712's high level input used measure current 4-20 loop applications shown Figure this case, system calibration capabilities AD7712 used remove offset caused flowing
ANALOG SUPPLY AVDD DVDD AVDD
through resistor. AD7712 handle input span VREF with VREF even though nominal input voltage range input Therefore, full span converter used measuring current between
VBIAS
2.5V REFERENCE CHARGE-BALANCING CONVERTER AIN1(+) AIN1(-) AIN2 VOLTAGE ATTENUATION CLOCK GENERATION SERIAL INTERFACE AUTO-ZEROED MODULATOR DIGITAL FILTER SYNC STANDBY
MCLK MCLK
4-20mA LOOP
CONTROL REGISTER OUTPUT REGISTER
AD7712
AGND DGND
MODE SDATA SCLK DRDY
Figure 4-20 Loop Measurement Using AD7712
OUTLINE DIMENSIONS 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24)
Dimensions shown millimeters (inches)
15.60 (0.6142) 15.20 (0.5984)
7.60 (0.2992) 7.40 (0.2913)
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) 0.51 (0.0201) 0.31 (0.0122) SEATING 0.33 (0.0130) PLANE 0.20 (0.0079)
0.75 (0.0295) 0.25 (0.0098)
COPLANARITY 0.10
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
REV.
-27-
AD7712
OUTLINE DIMENSIONS
24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24)
Dimensions shown inches (millimeters)
0.005 (0.13)
0.098 (2.49)
0.310 (7.87) 0.220 (5.59)
0.200 (5.08)
1.280 (32.51)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81)
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.100 (2.54)
0.070 (1.78) SEATING PLANE 0.030 (0.76)
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
24-Lead Plastic Dual In-Line Package [PDIP] (N-24)
Dimensions shown inches (millimeters)
1.185 (30.01) 1.165 (29.59) 1.145 (29.08)
0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
0.180 (4.57) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79)
0.015 (0.38)
0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.100 (2.54)
0.060 (1.52) SEATING 0.050 (1.27) PLANE 0.045 (1.14)
COMPLIANT JEDEC STANDARDS MO-095AG CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Revision History
Location 3/04-Data Sheet changed from REV. REV. Page
Changes SPECIFICATIONS Updated ORDERING GUIDE Deleted AD7712 ADSP-2105 Interface section Changes AD7712 68HC11 Interface section Updated OUTLINE DIMENSIONS -28- REV.
C01177-0-3/04(F)
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