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CMOS Cost 10-Bit Multiplying AD7533
cost 10-bit cost AD7520 replacement Linearity: LSB, LSB, power dissipation Full four-quadrant multiplying CMOS/TTL direct interface Latch free (protection Schottky required) Endpoint linearity
AD7533 cost, 10-bit, four-quadrant multiplying manufactured using advanced thin-film-onmonolithic-CMOS wafer fabrication process. function equivalent AD7520 industry standard, AD7533 recommended lower cost alternative AD7520 sockets 10-bit designs. AD7533 application flexibility demonstrated ability interface CMOS, operate power, provide proper binary scaling reference inputs either positive negative polarity.
APPLICATIONS
Digitally controlled attenuators Programmable gain amplifiers Function generation Linear automatic gain control
FUNCTIONAL BLOCK DIAGRAM
VREF IOUT2 IOUT1
01134-001
(MSB)
(LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
AD7533 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Revision History Specifications. Absolute Maximum Ratings. Caution. Terminology Configurations Function Descriptions Circuit Description.7 General Circuit Information.7 Equivalent Circuit Analysis Operation.8 Unipolar Binary Code Bipolar (Offset Binary) Code.8 Applications.9 Outline Dimensions Ordering Guide
REVISION HISTORY
1/06-Rev. Rev. Updated Format.Universal Changes Absolute Maximum Ratings Added Configurations Function Descriptions Section. Updated Outline Dimensions Changes Ordering Guide 3/04-Rev. Rev. Changes Specifications.2 Changes Absolute Maximum Ratings.3 Changes Ordering Guide Updated Outline Dimensions.7
Rev. Page
AD7533 SPECIFICATIONS
VOUT1 VOUT2 VREF unless otherwise noted. Table
Parameter STATIC ACCURACY Resolution Relative Accuracy1 AD7533JN, AD7533KN, AD7533LN, Gain Error2, Supply Rejection4 Gain/VDD Output Leakage Current IOUT1 IOUT2 DYNAMIC ACCURACY Output Current Settling Time Feedthrough Error Propagation Delay Glitch Impulse REFERENCE INPUT Input Resistance (Pin ANALOG OUTPUTS Output Capacitance CIOUT1 CIOUT2 CIOUT1 CIOUT2 DIGITAL INPUTS Input High Voltage (VINH) Input Voltage (VINL) Input Leakage Current (IIN) Input Capacitance (CIN) POWER REQUIREMENTS Ranges5 +25°C Bits ±0.2% ±0.1% ±0.05% 0.001%/% max4 ±0.05% max5 nV-s min, Operating Range Bits ±0.2% ±0.1% ±0.05% 0.001%/% ±200 ±200 ±0.1% max5 nV-s min, max6 Test Conditions
Digital input VINH Digital inputs VINH, Digital inputs VINL, VREF Digital inputs VINH, VREF 0.05% FSR; RLOAD digital inputs VINH VINL VINL VINH Digital inputs VINL, VREF sine wave
nominal
max5 max5 max5 max5 max5
max5 max5 max5 max5 max5
Digital inputs VINH
Digital inputs VINL
Rated accuracy Functionality with degraded performance Digital inputs VINL VINH Digital inputs over
full-scale range. Full Scale (FS) VREF. gain change from +25°C TMIN TMAX ±0.1% FSR. parameter, sample tested ensure specification compliance. Guaranteed, tested. Absolute temperature coefficient approximately -300 ppm/°C.
Rev. Page
AD7533 ABSOLUTE MAXIMUM RATINGS
unless otherwise noted. Table
Parameter VREF Digital Input Voltage Range IOUT1, IOUT2 Power Dissipation (Any Package) +75°C Derates above +75°C Operating Temperature Range Plastic (JN, Versions) Hermetic (AQ, Versions) Hermetic (SQ, Versions) Storage Temperature Range Lead Temperature (Soldering, sec) Rating -0.3 -0.3 -0.3 mW/°C -40°C +85°C -40°C +85°C -55°C +125°C -65°C +150°C 300°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD7533 TERMINOLOGY
Relative Accuracy Relative accuracy endpoint nonlinearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting ideal zero full scale expressed full-scale range (sub) multiples LSB. Resolution Value LSB. example, unipolar converter with bits resolution (2-n) (VREF). bipolar converter bits resolution [2-(n-1)] (VREF]. Resolution implies linearity. Settling Time Time required output function settle within given digital input stimulus, that full scale. Gain Error Gain error measure output error between ideal actual device output. measured with after offset error been adjusted expressed LSBs. Gain error adjustable zero with external potentiometer. Feedthrough Error Error caused capacitive coupling from VREF output with switches off. Output Capacitance Capacity from IOUT1 IOUT2 terminals ground. Output Leakage Current Current that appears IOUT1 terminal with digital inputs IOUT2 terminal when inputs high.
Rev. Page
AD7533 CONFIGURATIONS FUNCTION DESCRIPTIONS
IOUT2 IOUT1
IOUT2 (MSB)
AD7533
VREF
(MSB)
01134-002
VIEW (LSB) (Not Scale)
IOUT1
VREF
(LSB)
AD7533
VIEW (Not Scale)
Figure 16-Lead PDIP Configuration
01134-005
IOUT1 IOUT2 (MSB)
VREF
Figure 20-Terminal Configuration
IOUT2
VIEW (LSB) (Not Scale)
IOUT1
AD7533
CONNECT
01134-003
(MSB)
INDENTFIER
VREF
(LSB)
Figure 16-Lead SOIC Configuration
VIEW (Not scale)
AD7533
IOUT2 (MSB)
VREF
AD7533
CONNECT
VIEW (LSB) (Not Scale)
Figure 6.20-Lead PLCC Configuration
01134-004
Figure 16-Lead CERDIP Configuration
Table Function Descriptions
Number PDIP, SOIC, CERDIP LCC, PLCC Mnemonic IOUT1 IOUT2 VREF Description Current Output. Analog Ground. This should normally tied analog ground system. Ground. LSB. Positive Power Supply Input. These parts operated from supply Reference Voltage Input Terminal. Feedback Resistor Pin. Establish voltage output connecting external amplifier output. Connect.
Rev. Page
01134-006
IOUT1
AD7533 CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
AD7533, 10-bit multiplying converter, consists highly stable thin-film R-2R ladder CMOS current switches monolithic chip. Most applications require addition only output operational amplifier voltage current reference. simplified circuit shown Figure inverted ladder structure used, that binarily weighted currents switched between IOUT1 IOUT2 lines, thus maintaining constant current each ladder independent switch state.
VREF IOUT2 IOUT1
01134-001
EQUIVALENT CIRCUIT ANALYSIS
equivalent circuits digital inputs high digital inputs shown Figure Figure Figure with digital inputs low, reference current switched IOUT2. current source ILEAKAGE composed surface junction leakages substrate while current source 1024 represents constant 1-bit current drain through termination resistor R-2R ladder. capacitance output channel switch shown IOUT2 terminal. switch capacitance shown IOUT1 terminal. Analysis circuit digital inputs high, shown Figure similar Figure however, switches Terminal IOUT1. Therefore, there that terminal.
IOUT1 IREF VREF IOUT2
01134-008
(MSB)
(LSB)
ILEAKAGE
35pF
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Figure Functional Diagram
I/1024
ILEAKAGE
100pF
CMOS current switches shown Figure geometries Devices optimized make digital control inputs DTL/TTL/CMOS compatible over full military temperature range. input stage drives inverters (Devices which turn drive output channels. resistances switches binarily sealed that voltage drop across each switch same. example, Switch Figure designed resistance Switch reference input, current through switch current through Switch 0.25 thus maintaining constant drop across each switch. essential that each switch voltage drop equal binarily weighted current division property ladder maintained.
DTL/TTL/ CMOS INPUT IOUT2 IOUT1
01134-007
Figure AD7533 Equivalent Circuit-All Digital Inputs
IREF VREF IOUT1 I/1024 ILEAKAGE 100pF
IOUT2
01134-009
ILEAKAGE
35pF
Figure AD7533 Equivalent Circuit-All Digital Inputs High
LADDER
Figure CMOS Switch
Rev. Page
AD7533 OPERATION
UNIPOLAR BINARY CODE
Table Unipolar Binary Operation (2-Quadrant Multiplication)
Digital Input 1111111111 1000000001 1000000000 0111111111 0000000001 0000000000 Analog Output (VOUT shown Figure
BIPOLAR (OFFSET BINARY) CODE
Table Unipolar Binary Operation (4-Quadrant Multiplication)
Digital Input 1111111111 1000000001 1000000000 0111111111 0000000001 0000000000 Analog Output (VOUT shown Figure
1023 VREF 1024 VREF 1024 VREF VREF 1024 VREF 1024 VREF 1024 VREF 1024
VREF VREF VREF VREF VREF
Nominal magnitude circuit Figure given Nominal magnitude circuit Figure given
1024
BIPOLAR ANALOG INPUT ±10V
BIPOLAR DIGITAL INPUT
VREF
BIPOLAR ANALOG INPUT ±10V
VREF
IOUT1 IOUT2
VREF
UNIPOLAR DIGITAL INPUT
IOUT1 VOUT IOUT2
AD7533
VOUT
AD7533
NOTES SELECTED MATCHING TRACKING. USED ONLY GAIN ADJUSTMENT REQUIRED. PHASE COMPENSATION (5pF 15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIERS.
01134-010
NOTES USED ONLY GAIN ADJUSTMENT REQUIRED. PHASE COMPENSATION (5pF 15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
Figure Bipolar Operation (4-Quadrant Multiplication)
Figure Unipolar Binary Operation (2-Quadrant Multiplication)
Rev. Page
01134-011
AD7533 APPLICATIONS
BIPOLAR ANALOG INPUT ±10V
VREF
MAGNITUDE BITS DIGITAL INPUT SIGN
IOUT1 AD7512DIJN IOUT2
AD7533
VOUT
AD542
AD542
01134-012
Figure 10-Bit Sign Multiplying
CALIBRATE +15V
4.7k 6.8V SQUARE WAVE
AD542
VREF
DIGITAL FREQUENCY CONTROL WORD
IOUT1 IOUT2
AD7533
AD542
f=N( 8RtCt
TRIANGULAR WAVE
01134-013
210)
Figure Programmable Function Generator
+15V
VREF +15V
IOUT2
AD7533
IOUT1
DIGITAL INPUT VOUT -VIN
VOUT
VREF
DIGITAL INPUT
IOUT1
AD7533
IOUT2
-VREFD
VOUT
Figure Divider (Digitally Controlled Gain)
Figure Modified Scale Factor Offset
VREF
+15V
TEST INPUT VREF
DIGITAL INPUT (TEST LIMIT)
IOUT1
AD311 COMPARATOR
FAIL/PASS TEST
AD7533
IOUT2
01134-016
Figure Digitally Programmable Limit Detector
Rev. Page
01134-015
where: 1023 1024
VOUT VREF
01134-014
where: 1023 1024
AD7533 OUTLINE DIMENSIONS
0.800 (20.32) 0.790 (20.07) 0.780 (19.81)
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) 0.210 (5.33) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.005 (0.13) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN. CORNER LEADS CONFIGURED WHOLE HALF LEADS.
Figure 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown inches (millimeters)
10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10
1.75 (0.0689) 1.35 (0.0531)
0.50 (0.0197) 0.25 (0.0098)
0.51 (0.0201) SEATING 0.25 (0.0098) 1.27 (0.0500) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 16-Lead Standard Small Outline Package [SOIC] Narrow Body (R-16) Dimensions shown millimeters (inches)
Rev. Page
AD7533
0.005 (0.13)
0.098 (2.49)
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38)
0.840 (21.34) 0.200 (5.08) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.150 (3.81) SEATING 0.070 (1.78) PLANE 0.030 (0.76)
0.015 (0.38) 0.008 (0.20)
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 16-Lead Ceramic Dual In-Line Package [CERDIP] (Q-16) Dimensions shown inches (millimeters)
0.100 (2.54) 0.064 (1.63)
0.075 (1.91) 0.095 (2.41) 0.075 (1.90)
0.200 (5.08) 0.100 (2.54) 0.015 (0.38) 0.028 (0.71) 0.022 (0.56) 0.050 (1.27)
0.358 (9.09) 0.342 (8.69)
0.358 (9.09)
0.011 (0.28) 0.007 (0.18) 0.075 (1.91) 0.055 (1.40) 0.045 (1.14)
BOTTOM VIEW
0.088 (2.24) 0.054 (1.37)
0.150 (3.81)
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20A) Dimensions shown inches (millimeters)
0.048 (1.22 0.042 (1.07)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) 0.021 (0.53) 0.013 (0.33) 0.020 (0.50)
0.048 (1.22) 0.042 (1.07)
IDENTIFIER
VIEW
(PINS DOWN)
0.050 (1.27)
0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.045 (1.14) 0.025 (0.64) 0.120 (3.04) 0.090 (2.29)
BOTTOM VIEW
(PINS
0.020 (0.51)
0.356 (9.04) 0.350 (8.89) 0.395 (10.03) 0.385 (9.78)
COMPLIANT JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A) Dimensions shown inches (millimeters)
Rev. Page
AD7533
ORDERING GUIDE
Model AD7533ACHIPS AD7533JN AD7533JNZ1 AD7533KN AD7533KNZ1 AD7533LN AD7533LNZ1 AD7533JP AD7533JP-REEL AD7533JPZ1 AD7533JPZ-REEL1 AD7533KP AD7533KP-REEL AD7533KPZ1 AD7533KPZ-REEL1 AD7533KR AD7533KR-REEL AD7533KRZ1 AD7533KRZ-REEL1 AD7533AQ AD7533BQ AD7533CQ AD7533SQ AD7533UQ AD7533UQ/883B AD7533TE/883B
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C
Package Description 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 16-Lead Standard Small Outline Package [SOIC] 16-Lead Standard Small Outline Package [SOIC] 16-Lead Standard Small Outline Package [SOIC] 16-Lead Standard Small Outline Package [SOIC] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 20-Terminal Ceramic Leadless Chip Carrier [LCC]
Package Option N-16 N-16 N-16 N-16 N-16 N-16 P-20A P-20A P-20A P-20A P-20A P-20A P-20A P-20A R-16 R-16 R-16 R-16 Q-16 Q-16 Q-16 Q-16 Q-16 Q-16 E-20A
Nonlinearity max) ±0.2 ±0.2 ±0.1 ±0.1 ±0.05 ±0.05 ±0.2 ±0.2 ±0.2 ±0.2 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.2 ±0.1 ±0.05 ±0.2 ±0.05 ±0.05 ±0.1
Pb-free part.
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. C01134-0-1/06(B)
Rev. Page

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