Four 14-bit DACs package AD7834-serial loading AD7835-parallel 8-bit/1

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Four 14-bit DACs package AD7834-serial loading AD7835-parallel 8-bit/1

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LC2MOS Quad 14-Bit DACs AD7834/AD7835
Four 14-bit DACs package AD7834-serial loading AD7835-parallel 8-bit/14-bit loading Voltage outputs Power-on reset function Max/Min output voltage range ±8.192 Maximum output voltage span Common voltage reference inputs User-assigned device addressing Clear function user-defined voltage Surface-mount packages AD7834-28-lead SOIC PDIP AD7835-44-lead MQFP PLCC
AD7834 serial input device. Data loaded 16-bit format from external serial bus, first after leading into DIN, SCLK, FSYNC. AD7834 five dedicated package address pins, PA4, that wired AGND permit AD7834s individually addressed multipackage application. AD7835 accept either 14-bit parallel loading doublebyte loading, where right-justified data loaded 8-bit byte 6-bit byte. Data loaded from external into input latches under control BYSHF, channel address pins, With each device, LDAC signal used update four outputs simultaneously, individually, reception data. addition, each device, asynchronous input used signal outputs, VOUT1 VOUT4, user-defined voltage level Device Sense Ground pin, DSG. power-on, before power supplies have stabilized, internal circuitry holds output voltage levels within potential. supplies stabilize, output levels move exact potential (assuming exercised). AD7834 available 28-lead 0.3" SOIC package 28-lead 0.6" PDIP package, AD7835 available 44-lead MQFP package 44-lead PLCC package.
APPLICATIONS
Process control Automatic test equipment General purpose instrumentation
GENERAL DESCRIPTION
AD7834 AD7835 parts contain four 14-bit DACs monolithic chip. AD7834 AD7835 have output voltages range ±8.192 with maximum span
AD7834 FUNCTIONAL BLOCK DIAGRAM
VREF(-) VREF(+)
AD7835 FUNCTIONAL BLOCK DIAGRAM
VREF(-)A VREF(+)A
AD7834
PAEN FSYNC SCLK
SERIAL-TOPARALLEL CONVERTER CONTROL LOGIC ADDRESS DECODE
INPUT REGISTER
LATCH
AD7835
VOUT
BYSHF DB13
INPUT BUFFER
INPUT REGISTER INPUT REGISTER
LATCH
VOUT1
INPUT REGISTER
LATCH
VOUT
LATCH
INPUT REGISTER INPUT REGISTER LATCH
VOUT2
INPUT REGISTER
LATCH
VOUT
VOUT3
INPUT REGISTER LATCH
VOUT
01006-001
ADDRESS DECODE
LATCH
VOUT4
01006-002
AGND DGND LDAC
AGND DGND LDAC VREF(-)B VREF(+)B
Figure Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Figure
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. rights reserved.
AD7834/AD7835 TABLE CONTENTS
Specifications. Performance Characteristics Timing Specifications. Absolute Maximum Ratings. Caution. Configurations Function Descriptions Terminology Typical Performance Characteristics Theory Operation Architecture-General. Data Loading-AD7834, Serial Input Device Data Loading-AD7835, Parallel Loading Device Unipolar Configuration. Bipolar Configuration. Controlled Power-On Output Stage. Power-On with Low, LDAC High Power-On with LDAC Low, High Loading Using Input Voltage Range Power-On AD7834/AD7835. Microprocessor Interfacing. AD7834 80C51 Interface AD7834 68HC11 Interface AD7834 ADSP-2101 Interface AD7834 DSP56000/DSP56001 Interface. AD7834 TMS32020/TMS320C25 Interface. Interfacing AD7835-16-Bit Interface. 8-Bit Interface Applications. Serial Interface Multiple AD7834s Opto-Isolated Interface Automated Test Equipment Power Supply Bypassing Grounding. Outline Dimensions Ordering Guide
REVISION HISTORY
7/05-Rev. Rev. Updated Format.Universal Changes Figure Changes Ordering Guide 7/03-Rev. Rev. Revision Initial Version
Rev. Page
AD7834/AD7835 SPECIFICATIONS
AGND DGND TMIN TMAX, unless otherwise noted. Table
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error TMIN TMAX Zero-Scale Error Gain Error Gain Temperature Coefficient ±0.9 ±0.5 Crosstalk2 REFERENCE INPUTS Input Resistance Input Current VREF Range VREF Range [VREF VREF (-)] DEVICE SENSE GROUND INPUTS Input Current DIGITAL INPUTS VINH, Input High Voltage VINL, Input Voltage IINH, Input Current CIN, Input Capacitance POWER REQUIREMENTS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS 0/8.192 -8.192/0 5/14 ±0.9 ±0.5 0/8.192 -8.192/0 7/14 ±0.9 ±0.5 0/8.192 -8.192/0 5/14 Unit Bits FSR/°C FSR/°C min/max min/max min/max Test Conditions/Comments
Guaranteed Monotonic over Temperature. VREF(+) VREF VREF VREF VREF VREF
Terminology section.
Input.
specified performance. performance guaranteed.
15.0 -15.0
15.0 -15.0
15.0 -15.0
input. VDSG
specified performance. specified performance. specified performance.
VINH VCC, DGND. AD7834: min, VINL max. AD7835: min, max. AD7834: outputs unloaded. AD7835: outputs unloaded. Outputs unloaded.
Temperature range follows: version: -40°C +85°C; version: -40°C +85°C. version: -40°C +85°C Guaranteed design.
Rev. Page
AD7834/AD7835 PERFORMANCE CHARACTERISTICS
These characteristics included design guidance subject production testing. Table
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse Output Impedance Channel-to-Channel Isolation Crosstalk Digital Crosstalk Digital Feedthrough-AD7834 Digital Feedthrough-AD7835 Output Noise Spectral Density Unit (typ) nV-s nV-s nV-s nV-s nV-s nV/Hz Test Conditions/Comments Full-scale change ±1/2 LSB. latch contents alternately loaded with Measured with VREF(+) VREF(-) latch alternately loaded with Terminology section. Terminology section; applies AD7835 only. Terminology section. Feedthrough output under test change digital input code another converter. Effect input activity output under test. loaded DAC. VREF(+) VREF(-)
Rev. Page
AD7834/AD7835
AGND DGND TMIN TMAX, unless otherwise noted. Table
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error TMIN TMAX Zero-Scale Error Gain Error Gain Temperature Coefficient Crosstalk2 REFERENCE INPUTS Input Resistance Input Current VREF(+) Range VREF(-) Range [VREF(+) VREF(-)] DEVICE SENSE GROUND INPUTS Input Current DIGITAL INPUTS VINH, Input High Voltage VINL, Input Voltage IINH, Input Current CIN, Input Capacitance POWER REQUIREMENTS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS ±0.9 ±0.9 ±0.9 Unit Bits Test Conditions/Comments
Guaranteed monotonic over temperature. VREF VREF
±0.5 0/8.192 -5/0 5/13.192
±0.5 0/8.192 -5/0 7/13.192
±0.5 0/8.192 -5/0 5/13.192
FSR/°C FSR/°C min/max min/max min/max
VREF VREF VREF(+) VREF
Terminology section.
input.
specified performance. Performance Guaranteed.
input. VDSG
15.0 -15.0
15.0 -15.0
15.0 -15.0
specified performance. specified performance. specified performance.
VINH VCC, VINL DGND. AD7834: VINH min, VINL max. AD7835: VINH min, VINL max. AD7834: Outputs unloaded. AD7835: Outputs unloaded. Outputs unloaded.
Temperature range follows: version: -40°C +85°C; version: -40°C +85°C. version: -40°C +85°C. Guaranteed design.
Rev. Page
AD7834/AD7835 TIMING SPECIFICATIONS
+11.4 +15.75 -11.4 -15.75 AGND DGND Table
Parameter AD7834 SPECIFIC AD7835 SPECIFIC general
Limit TMIN, TMAX
Unit
Description SCLK cycle time SCLK SCLK high time FSYNC, PAEN setup time FSYNC, PAEN hold time Data setup time Data hold time LDAC FSYNC setup time LDAC toFSYNC hold time Delay between write operations BYSHF setup time BYSHF hold time setup time hold time pulsewidth Data setup time Data hold time LDAC setup time LDAC setup time LDAC hold time LDAC, pulsewidth
input signals specified with (10% timed from voltage level Rise fall times should longer than
BYSHF
SCLK
24TH
DATA
FSYNC
LDAC (SIMULTANEOUS UPDATE) LDAC (PER-CHANNEL UPDATE)
LDAC (SIMULTANEOUS UPDATE)
LDAC (PER-CHANNEL UPDATE)
Figure AD7834 Timing Diagram
Figure AD7835 Timing Diagram
Rev. Page
AD7834/AD7835 ABSOLUTE MAXIMUM RATINGS
25°C unless otherwise noted. Table
Parameters DGND3 AGND AGND AGND DGND Digital Inputs DGND VREF(+) VREF(-) VREF(+) AGND VREF(-) AGND AGND VOUT (1-4) AGND Operating Temperature Range Industrial Version) Storage Temperature Range Junction Temperature Plastic Package Thermal Impedance Lead Temperature, Soldering sec) SOIC Package Thermal Impedance Lead Temperature, Soldering Vapor Phase sec) Infrared sec) MQFP Package Thermal Impedance Lead Temperature, Soldering Vapor Phase sec) Infrared sec) PLCC Package Thermal Impedance Lead Temperature, Soldering Vapor Phase sec) Infrared sec) Power Dissipation (Any Package)
AD7834/ AD7835
Figure
-40°C +85°C -65°C +150°C 150°C 75°C/W 260°C
75°C/W 215°C 220°C 95°C/W 215°C 220°C 55°C/W 215°C 220°C
Transient currents will cause latch-up. must exceed more than possible this happen during power supply sequencing, diode protection scheme Figure will ensure protection.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
01006-005
Rating -0.3 (whichever lower) -0.3 +0.3 -0.3 +0.3 -0.3 -0.3
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
IN4148 SD103C
AD7834/AD7835 CONFIGURATIONS FUNCTION DESCRIPTIONS
VREF(-) VREF(+) VOUT2
AGND
AD7834
VIEW VOUT4 (Not Scale) VOUT1 DGND SCLK
VOUT3 LDAC FSYNC PAEN
01006-006
CONNECT
Figure AD7834 PDIP SOIC
Table AD7834 Function Descriptions
12,13,14,15,16 Mnemonic VREF(-) VREF(+) VOUT1 VOUT4 DGND SCLK PAEN Description Negative Analog Power Supply; Device Sense Ground Input. Used conjunction with input power-on protection DACs. When low, outputs forced potential pin. Negative Reference Input. negative reference voltage referred AGND. Positive Reference Input. positive reference voltage referred AGND. Connect. Outputs. Digital Ground. Logic Power Supply; Clock Input writing data device. Data clocked into input register falling edge SCLK. Serial Data Input. Package Address Inputs. These inputs hardwired high (VCC) (DGND) assign dedicated package addresses multipackage environment. Package Address Enable Input. When low, this input allows normal operation device. When high, device ignores package address, channel address, serial data stream loads serial data into input registers. This feature useful multipackage application where used load same data into same channel each package. Frame Sync Input. Active logic input used, conjunction with SCLK, write data device with serial data expected after falling edge this signal. contents 24-bit serial-toparallel input register transferred rising edge this signal. Load Input (Level Sensitive). This input signal, conjunction with FSYNC input signal, determines analog outputs updated. LDAC maintained high while data being loaded into device's input registers, change occurs analog outputs. Subsequently, when LDAC brought low, contents four input registers transferred into their respective latches, updating analog outputs. Asynchronous Clear Input (Level Sensitive, Active Low). When this input brought low, analog outputs switched externally potential pin. When brought high, signal outputs remain potential until LDAC brought low. When LDAC brought low, analog outputs switched back reflect their individual output levels. long remains low, LDAC signals ignored, signal outputs remain switched potential pin. Positive Analog Power Supply; Analog Ground.
FSYNC
LDAC
AGND
Rev. Page
AD7834/AD7835
VREF(-)A VREF(+)B
VREF(+)B
VREF(-)A
VREF(+)A
VREF(-)B
VREF(+)A
AGND
VREF(-)B
AGND
DSGA VOUT1 VOUT2 LDAC BYSHF DGND CONNECT
IDENTIFIER
DSGB VOUT3 VOUT4 DSGA VOUT1 VOUT2 LDAC BYSHF
IDENTIFIER
DSGB VOUT3 VOUT4
AD7835
VIEW (Not Scale)
DB13 DB12 DB11 DB10
01006-007
AD7835
VIEW (Not Scale)
DB13 DB12 DB11 DB10
CONNECT
DGND
01006-008
Figure AD7835 MQFP
Figure AD7835 PLCC
Table AD7835 Function Descriptions
MQFP PLCC Mnemonic Description Connect.
DSGA VOUT1 VOUT4
Device Sense Ground Input. Used conjunction with input power-on protection DACs. When low, outputs VOUT1 VOUT2 forced potential DSGA pin. Outputs Address Inputs. decoded select four input latches data transfer. used select four DACs simultaneously. Asynchronous Clear Input (level sensitive, active low). When this input brought low, analog outputs switched externally potentials pins (VOUT1 VOUT2 follow DSGA while VOUT3 VOUT4 follow DSGB). When brought high, signal outputs remain potentials until LDAC brought low. When LDAC brought low, analog outputs switched back reflect their individual output levels. long remains low, LDAC signals ignored signal outputs remain switched potential pins. Load Input (level sensitive). This input signal, conjunction with input signals, determines analog outputs updated. LDAC maintained high while data being loaded into device's input registers, change occurs analog outputs. Subsequently, when LDAC brought low, contents four input registers transferred into their respective latches, updating analog outputs simultaneously. Alternatively, LDAC brought while data being entered, addressed latch corresponding analog output updated immediately rising edge Byte Shift Input. When low, shifts data into DB13 half input register. Level-Triggered Chip Select Input (Active Low). device selected when this input low. Level-Triggered Write Input (Active Low). When active, used conjunction with write data over input databus. Logic Power Supply; Digital Ground.
LDAC
BYSHF DGND
Rev. Page
AD7834/AD7835
MQFP PLCC Mnemonic DB13 Description Parallel Data Inputs. AD7835 accept straight 14-bit parallel word DB13, where DB13 BYSHF input hardwired logic high. Alternatively byte loading, bottom eight data inputs, DB7, used data loading, while data inputs, DB13, should hardwired logic low. BYSHF control input selects whether LSBs MSBs data being loaded into device. Device Sense Ground Input. Used conjunction with input power-on protection DACs. When low, outputs VOUT3 VOUT4 forced potential DSGB pin. Reference Inputs DACs These reference voltages referred AGND. Analog Ground Positive Analog Power Supply; Negative Analog Power Supply; Reference Inputs DACs These reference voltages referred AGND.
DSGB VREF(+)B, VREF(-)B AGND VREF(+)A, VREF(-)A
Rev. Page
AD7834/AD7835 TERMINOLOGY
Relative Accuracy Relative accuracy endpoint linearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error. normally expressed inLSBs percentage full-scale reading. Differential Nonlinearity Differential nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity maximum ensures monotonicity. Crosstalk Although common input reference voltage signals internally buffered, small drops individual reference inputs across means update channel produces output change other channel outputs. four outputs buffered amps sharing common power supplies. load current changes channel update, this results further change more channel outputs. This effect most obvious high load currents reduces load currents reduced. With high impedance loads, effect virtually unmeasurable. Output Voltage Settling Time This amount time takes output settle specified level full-scale input change. Digital-to-Analog Glitch Impulse This amount charge injected into analog output when inputs change state. specified area glitch nV-secs. measured with reference inputs connected digital inputs toggled between Channel-to-Channel Isolation Channel-to-channel isolation refers proportion input signal from reference input which appears output other DAC. expressed dBs. AD7834 specification channel-to-channel isolation because reference DACs. Channel-to-channel isolation specified AD7835. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk defined glitch impulse that appears output converter both digital change subsequent analog change another converter. specified nV-secs. Digital Crosstalk glitch impulse transferred output converter change digital input code other converter defined digital crosstalk specified nV-secs. Digital Feedthrough When device selected, high frequency logic activity digital inputs capacitively coupled both across through device show noise VOUT pins. This noise digital feedthrough. Output Impedance This effective output source resistance. dominated package lead resistance. Full-Scale Error This error output voltage when loaded into latch. Ideally, output voltage, with loaded into latch, should VREF(+) LSB. Full-scale error does include zero-scale error. Zero-Scale Error Zero-scale error error output voltage when loaded into latch. Ideally, output voltage, with latch, equal VREF(-). Zero-scale error mainly offsets output amplifier. Gain Error Gain error defined (full-scale error) (zero-scale error).
Rev. Page
AD7834/AD7835 TYPICAL PERFORMANCE CHARACTERISTICS
(LSB)
0.50 0.45 0.40 0.35
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 CODE/1000
01006-009
0.30 0.25 0.20 0.15 0.10 0.05 TEMP 25°C DACs FROM DEVICE
VREF(+)
Figure Typical Plot
Figure Typical VREF(+), [VREF(+) VREF(-)
DACs FROM DEVICE
(LSB)
-0.1 -0.2 -0.3
01006-010
(LSB)
01006-013
-0.4 -0.5 CODE/1000
TEMPERATURE (°C)
Figure Typical Plot
Figure Typical Temperature
(LSB)
-0.2 -0.4
(LSB)
VREF(+)
01006-011
-0.6 -0.8 -1.0 CODE/1000
01006-014
Figure Typical VREF(+), [VREF(-)
Figure Typical DAC-to-DAC Matching
Rev. Page
01006-012
AD7834/AD7835
VOLTS
VOLTS
VREF(+) VREF(-) -3.025
VERT 100mV/DIV HORIZ 1s/DIV
VERT 10mV/DIV HORIZ 1s/DIV
-2.985
-3.005
-3.045
-3.065
01006-015
-3.085 VERT 2V/DIV HORIZ 1s/DIV
01006-017
-0.1 -0.2
-3.105
Figure Typical Digital/Analog Glitch Impulse
Figure Settling Time
7.250 VERT 2V/DIV HORIZ 1.2s/DIV 7.225
7.200 VREF(+) VREF(-)
VOLTS
7.175
7.150
VERT 25mV/DIV HORIZ 2.5s/DIV
7.125
01006-016
7.100
Figure Settling Time
VOLTS
Rev. Page
VOLTS
AD7834/AD7835 THEORY OPERATION
ARCHITECTURE-GENERAL
Each channel consists segmented 14-bit R-2R voltage-mode DAC. full-scale output voltage range equal entire reference span VREF(+) VREF(-). coding straight binary; produce output VREF(-); produce output VREF(+) LSB. analog output voltage each channel reflects contents latch. Data transferred from external input register each latch channel basis. AD7835 feature whereby using data transferred from input databus four input registers simultaneously. Bringing line switches signal outputs, VOUT1 VOUT4, voltage level pin. signal outputs held this level after removal signal will switch back outputs until LDAC signal exercised. Table Control
Control Function Ignore following bits information. following bits address data normal.
D21: Decoded select four channels within device. Table truth table. Table D22, Control
Control Function Select Channel Select Channel Select Channel Select Channel
D16: Determines package address. five address bits allow separate packages individually decoded. Successful decoding accomplished when these five bits match with five hardwired pins physical package. data loaded into identified input register. This data must have leading followed bits data, first. location 24-bit data stream.
DATA LOADING-AD7834, SERIAL INPUT DEVICE
write operation transfers bits data AD7834. first bits control data remaining bits data (see Figure 18). control data identifies channel updated with data which possible packages resides communication with device, first bits must always control data. output voltages, VOUT1 VOUT4, updated reflect data input registers ways. first method normally keeps LDAC high only pulses LDAC momentarily update latches simultaneously with contents their respective input registers. second method ties LDAC channel updating occurs channel basis after data been clocked into AD7834. With LDAC low, rising edge FSYNC transfers data directly into latch, updating analog output voltage. Data being shifted into AD7834 enters 24-bit long shift register. more than bits clocked before FSYNC goes high, last bits transmitted used control data data. Individual functions discussed Figure D23: Determines whether following bits address data should used ignored. This effectively software chip select bit. first transmitted 24-bit long word.
DATA LOADING-AD7835, PARALLEL LOADING DEVICE
Data loaded into AD7835 either straight 14-bit wide words 8-bit bytes. systems that transfer 14-bit wide data, BYSHF input should hardwired VCC. This sets AD7835 straight 14-bit parallel-loading DAC. 8-bit systems where required transfer data bytes, necessary have BYSHF input under logic control. such system, pins device databus, DB13, must hardwired DGND. byte data loaded into lower eight places selected input register carrying write operation while holding BYSHF high. second write operation subsequently executed with BYSHF MSBs inputs (DB5 MSB).
Rev. Page
AD7834/AD7835
NOTE: FIRST TRANSMITTED SERIAL WORD.
CONTROL USE/IGNORE FOLLOWING BITS INFORMATION CHANNEL ADDRESS MSB, CHANNEL ADDRESS LSB, PACKAGE ADDRESS MSB, PACKAGE ADDRESS, PACKAGE ADDRESS, PACKAGE ADDRESS, PACKAGE ADDRESS LSB, DB10 THIRD MSB, DB11 SECOND MSB, DB12 MSB, DB13 SECOND LEADING ZERO FIRST LEADING ZERO
LSB, SECOND LSB, THIRD LSB,
Figure Assignments 24-Bit Data Stream AD7834
When 14-bit transfers being used, output voltages, VOUT1 VOUT4, updated reflect data input registers ways. first method normally keeps LDAC high only pulses LDAC momentarily update latches simultaneously with contents their respective input registers. second method ties LDAC low, channel updating occurs channel basis after data loaded input register. avoid output going intermediate value during 2-byte transfer, LDAC should tied permanently should held high until bytes written input register. When selected input register been loaded with bytes, LDAC should then pulsed update latch and, consequently, perform digital-to-analog conversion. many applications, acceptable allow output intermediate value during 2-byte transfer. such applications, LDAC tied low, thus using less control line. actual input register that being written determined logic levels present devices address lines, shown Table Table AD7835-Address Line Truth Table
Selected DACs Selected
UNIPOLAR CONFIGURATION
Figure shows AD7834/AD7835 unipolar binary circuit configuration. VREF(+) input driven AD586, reference. VREF(-) tied ground. Table gives code table unipolar operation AD7834/ AD7835.
+15V
VREF(+)
VOUT VOUT
AD586
AD7834/ AD78351
AGND VREF(-) DGND
-15V
1ADDITIONAL
PINS OMITTED CLARITY
Figure Unipolar Operation
Offset gain adjusted Figure follows: adjust offset, disconnect VREF(-) input from load with adjust VREF(-) voltage until VOUT gain adjustment, AD7834/AD7835 should loaded with adjusted until VOUT V(16383/16384) 4.999695. Many circuits require these offset gain adjustments. these circuits, omitted. AD586 left open circuit, (VREF(-)) AD7834/AD7835 tied Table Code Table Unipolar Operation
Binary Number Latch
1111 0000 1111 0000 0000
1111 0000 1111 0000 0000
1111 0000 1111 0001 0000
Analog Output (VOUT) VREF (16383/16384) VREF (8192/16384) VREF (8191/16384) VREF (1/16384)
VREF VREF (+); VREF unipolar operation. VREF V/214 V/16384
Rev. Page
01006-019
SIGNAL
SIGNAL
01006-018
AD7834/AD7835
BIPOLAR CONFIGURATION
+15V 100k VREF(+) VOUT VOUT (-5V +5V)
Figure full-scale bipolar zero adjustments provided varying gain balance AD588. varies gain AD588 while adjusts offset both outputs together with respect ground. bipolar-zero adjustment, loaded with 1000 0000 adjusted until VOUT Full scale adjusted loading with adjusting until VOUT 5(8191/8192) 4.99939 When bipolar zero full-scale adjustment needed, omitted. AD588 should connected should left floating.
AD588
100k
1ADDITIONAL
AD7834/ AD78351
VREF(-) AGND DGND
PINS OMITTED CLARITY
-15V
Figure Bipolar Operation
Figure shows AD7834/AD7835 setup operation. AD588 provides precision tracking outputs that VREF(+) VREF(-) inputs AD7834/AD7835. code table bipolar operation AD7834/AD7835 shown Table Table Code Table Bipolar Operation
Binary Number Latch 1111 1111 1111 0000 0000 0001 0000 0000 0000 1111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT) VREF(-) VREF (16383/16384) VREF VREF (8193/16384) VREF VREF (8192/16384) VREF VREF (8191/16384) VREF VREF (1/16384) VREF
VREF [VREF VREF (-)]. VREF VREF V/214 V/16384
Rev. Page
01006-020
SIGNAL
AD7834/AD7835 CONTROLLED POWER-ON OUTPUT STAGE
block diagram output stage AD7834/AD7835 shown Figure capable driving load parallel with transmission gates used control power-on voltage present VOUT. also used conjunction with input VOUT user defined voltage present pin.
01006-021
01006-023
VOUT
VOUT
Figure Output Stage with
VOUT been disconnected from opening will track voltage present unity gain buffer.
POWER-ON WITH LDAC LOW, HIGH
many applications AD7834/AD7835, LDAC kept continuously low, updating after each valid data transfer. LDAC when power applied, then closed open, connecting output input output amplifier. closed open, connecting amplifier unity gain buffer, before. VOUT connected thin-film resistance between VOUT) until reach approximately Then, internal power-on circuitry opens closes This situation shown Figure VOUT same voltage output.
01006-024
Figure Block Diagram AD7834/AD7835 Output Stage
POWER-ON WITH LOW, LDAC HIGH
output stage AD7834/AD7835 designed allow output stability during power-on. kept during power-on, power applied part, open while closed (see Figure 22).
01006-022
VOUT
VOUT
Figure Output Stage with
VOUT kept within hundred millivolts thin-film resistor between VOUT. output amplifier connected unity gain buffer voltage applied buffer input amplifier's output thus same voltage pin. output stage remains configured Figure until voltage reaches approximately now, output amplifier enough headroom handle signals input also time settle. internal power-on circuitry opens closes (see Figure 23). Now, output amplifier connected unity gain mode voltage still applied noninverting input This voltage appears VOUT.
Figure Output Stage with LDAC
LOADING USING INPUT
When LDAC goes low, closes opens Figure voltage VOUT follows voltage present output DAC. output stage remains connected this manner until signal applied. Then, situation reverts (see Figure 23). Once again, VOUT remains same voltage until LDAC goes low. This reconnects output unity gain buffer.
Rev. Page
AD7834/AD7835
VOLTAGE RANGE
During power-on, VOUT pins AD7834/AD7835 connected relevant pins thin-film resistor, potential must obey maximum ratings times. Thus, voltage must always within range However, keep voltages VOUT pins AD7834/AD7835 within relevant potential during power-on, voltage applied should also kept within range AGND AGND Once AD7834/AD7835 powered on-chip amplifiers have settled, situation shown Figure voltage applied buffered same amplifier that buffers output voltage normal operation. Thus, specified operations, maximum voltage applied increases maximum allowable VREF(+) voltage, minimum voltage applied minimum VREF(-) voltage. After AD7834/AD7835 fully powered outputs track voltage within this minimum/maximum range.
Rev. Page
AD7834/AD7835 POWER-ON AD7834/AD7835
Power normally applied AD7834/AD7835 following sequence: first VSS, then VCC, then VREF(+) VREF(-). VREF pins allowed float when power applied part. VREF(+) allowed below VREF(-) VREF(-) allowed below allowed below some systems, necessary introduce more Schottky diodes between pins prevent above situations arising power-on. These diodes shown Figure However most systems, with careful consideration given power supply sequencing, above rules adhered protection diodes necessary.
VREF(+)
AD78341
VREF(-)
SD103C 1N5711 1N5712
01006-025
1ADDITIONAL PINS OMITTED CLARITY
Figure Power-On Protection
Rev. Page
AD7834/AD7835 MICROPROCESSOR INTERFACING
AD7834 80C51 INTERFACE
serial interface between AD7834 80C51 microcontroller shown Figure 80C51 drives SCLK AD7834, while drives serial data line part. 80C51 provides SBUF register first serial data stream. AD7834 expects 24-bit write first. Therefore, user ensure data SBUF register arranged correctly data received first AD7834/AD7835. When data transmitted part, P3.3 taken low. Data valid falling edge TXD. 80C51 transmits data 8-bit bytes with only falling clock edges occurring transmit cycle. load data AD7834, P3.3 left after first bits transferred. second byte then transferred, with P3.3 still kept low. After third byte been transferred, P3.3 line taken high.
80C51
P3.5 P3.4 P3.3
load data AD7834, left after first bits transferred. second byte data then transmitted serially AD7834. Then, third byte transmitted, when this transfer complete, line taken high.
68HC11
MOSI
1ADDITIONAL PINS
AD78341
LDAC FSYNC SCLK OMITTED CLARITY
01006-027
Figure AD7834 68HC11 Interface
AD78341
LDAC FSYNC SCLK
01006-026
Figure LDAC controlled port outputs, respectively. with 80C51, each AD7834 updated after each byte transfer, else DACs simultaneously updated after bytes transferred.
AD7834 ADSP-2101 INTERFACE
interface between AD7834 ADSP-2101 shown Figure interface shown, SPORT0 used transfer data part. SPORT1 configured alternate functions. flag output SPORT0, connected LDAC used load latches. this way, data transferred from ADSP-2101 input registers DAC, latches updated simultaneously. application shown, AD7834 controlled circuitry that monitors power system.
POWER MONITOR
1ADDITIONAL PINS OMITTED CLARITY
Figure AD7834 80C51 Interface
LDAC AD7834 also controlled 80C51 port outputs. user bring LDAC after every bytes have been transmitted update DAC, which been programmed. Alternatively, possible wait until input registers have been loaded (12-byte transmits) then update outputs.
ADSP-21011
AD78341
AD7834 68HC11 INTERFACE
Figure shows serial interface between AD7834 68HC11 microcontroller. 68HC11 drives SCLK AD7834, while MOSI output drives serial data line, DIN, AD7834. FSYNC signal derived from port line PC7, shown Figure correct operation this interface, 68HC11 should configured CPOL CPHA When data transferred part, taken low. When 68HC11 configured like this, data MOSI valid falling edge SCK. 68HC11 transmits serial data 8-bit bytes, first. AD7834 also expects 24-bit write first. Eight falling clock edges occur transmit cycle.
1ADDITIONAL PINS
LDAC FSYNC SCLK OMITTED CLARITY
01006-028
Figure AD7834 ADSP-2101 Interface
AD7834 requires bits serial data framed single FSYNC pulse. necessary that this FSYNC pulse stays until data transferred. This provided ADSP-2101 ways. Both require setting serial word length SPORT bits, with following conditions: internal SCLK, alternate framing mode, active framing signal.
Rev. Page
AD7834/AD7835
First, data transferred using autobuffering feature ADSP-2101, sending 12-bit words directly after each other. This ensures continuous pulse. Second, first data word loaded serial port, subsequent generated interrupt trapped, then second data word sent immediately after first. Again, this produces continuous pulse that frames data bits.
CLOCK/ TIMER TMS32020/ TMS320C251 CLKX
AD78341
LDAC FSYNC SCLK
01006-030
AD7834 DSP56000/DSP56001 INTERFACE
Figure shows serial interface between AD7834 DSP56000/DSP56001. serial port configured word length bits, gated clock, with FSL0 FSL1 control bits each Normal mode synchronous operation selected which allows outputs controlling LDAC, respectively. framing signal inverted before being applied FSYNC. internally generated DSP56000/DSP56001 applied SCLK AD7834. Data from DSP56000/DSP56001 valid falling edge SCK.
DSP56000/ DSP560011
1ADDITIONAL
1ADDITIONAL
PINS OMITTED CLARITY
Figure AD7834 TMS32020/TMS320C25 Interface
INTERFACING AD7835-16-BIT INTERFACE
AD7835 interfaced variety microcontrollers processors, both 8-bit 16-bit. Figure shows AD7835 interfaced generic 16-bit microcontroller/DSP processor. BYSHF tied this interface. lower address lines from processor connected AD7835 shown. upper address lines decoded provide chip select signal AD7835. They also decoded, conjunction with lower address lines need provide LDAC signal. Alternatively, LDAC driven external timing circuit just tied low. data lines processor connected data lines AD7835. selection DACs provided Table
CONTROLLER/ PROCESSOR1 DATABUS UPPER BITS ADDRESS ADDRESS DECODE LDAC
01006-031
AD78341
LDAC FSYNC SCLK
01006-029
AD78351
BYSHF
PINS OMITTED CLARITY
Figure AD7834 DSP56000/DSP56001 Interface
AD7834 TMS32020/TMS320C25 INTERFACE
serial interface between AD7834 TMS32020/ TMS320C25 processor shown Figure CLKX signals TMS32020/TMS32025 generated using external clock/timer circuit. CLKX pins configured inputs. TMS32020/ TMS320C25 8-bit serial data length. Data then written AD7834 writing bytes serial port TMS32020/TMS320C25. configuration shown Figure input AD7834 controlled output TMS32020/TMS320C25. clock/timer circuit controls LDAC input AD7834. Alternatively, LDAC also tied ground allow automatic update latches after each transfer.
1ADDITIONAL PINS OMITTED CLARITY
Figure AD7835 16-Bit Interface
Rev. Page
AD7834/AD7835
8-BIT INTERFACE
Figure shows 8-bit interface between AD7835 generic 8-bit microcontroller/DSP processor. AD7835 tied DGND. processor connected AD7835. BYSHF driven line processor. This maps upper bits lower bits into adjacent bytes processor's address space. Table shows truth table addressing DACs AD7835. example, base address DACs processor address space decoded upper address bits location HC000, then first DAC's upper lower bits locations HC000 HC001, respectively.
CONTROLLER/ PROCESSOR1 DGND DATABUS UPPER BITS ADDRESS ADDRESS DECODE LDAC BYSHF
Table Selection, 8-Bit Interface
Processor Address Lines Selected Upper Bits DACs Lower Bits DACs Upper Bits, Lower Bits, Upper Bits, Lower Bits, Upper Bits, Lower Bits, Upper Bits, Lower 8-Bits,
AD78351
1ADDITIONAL PINS OMITTED CLARITY
Figure AD7835 8-Bit Interface
When writing DACs, lower eight bits must written first, followed upper bits. upper bits should output data lines Once again, upper address lines processor decoded provide signal. They also decoded conjunction with lines provide LDAC signal. Alternatively, LDAC driven external timing circuit acceptable allow output intermediate value between 8-bit writes, LDAC tied low.
Rev. Page
01006-032
AD7834/AD7835 APPLICATIONS
SERIAL INTERFACE MULTIPLE AD7834S
Figure shows package address pins AD7834 used address multiple AD7834s. This figure shows only devices, AD7834s each assigned unique address hardwiring each package address pins DGND. Normal operation device occurs when PAEN low. When serial data being written AD7834s, only device with same package address package address contained serial data accepts data into input registers. Conversely, PAEN high, package address ignored, data loaded into same channel each package. primary limitation with multiple packages output update rate. example, output update rate required, there load DACs. Assuming serial clock frequency MHz, takes load data DAC. Thus DACs packages updated this time. update rate requirement decreases, number possible packages increases.
CONTROLLER CONTROL CONTROL SYNC SERIAL CLOCK SERIAL DATA
Figure shows 5-channel isolated interface AD7834. Multiple devices connected outputs optocoupler controlled explained above. reduce number opto-isolators, PAEN line doesn't need controlled used. PAEN line controlled microcontroller, then should tied each device. simultaneous updating DACs required, then LDAC each part tied permanently further opto-isolator needed.
CONTROLLER
CONTROL CONTROL SYNC SERIAL CLOCK SERIAL DATA
PAENs LDACs FSYNCs SCLKs DINs
01006-034
AD78341
DEVICE PAEN LDAC FSYNC SCLK
OPTO-COUPLER
Figure Opto-Isolated Interface
AUTOMATED TEST EQUIPMENT
AD7834/AD7835 particularly suited automated test environment. Figure shows AD7835 providing necessary voltages driver window comparator typical electronics configuration. AD588s used provide reference voltages AD7835. configuration shown, AD588s configured, voltage greater than voltage voltage less than voltage AD588s used reference DACs These DACs used provide high levels driver. driver have associated offset. This nulled applying offset voltage AD588. First, code 1000 0000 loaded into latch, driver output output. VOFFSET voltage adjusted until appears between driver output GND. This causes both VREF(+)A VREF(-)A offset with respect AGND amount equal VOFFSET. However, output driver varies from with respect input code varies from 111. VOFFSET voltage also applied pin. When clear performed AD7835, output driver with respect GND.
AD78341
DEVICE PAEN LDAC FSYNC SCLK
AD78341
DEVICE PAEN LDAC FSYNC SCLK
1ADDITIONAL PINS OMITTED CLARITY
Figure Serial Interface Multiple AD7834s
OPTO-ISOLATED INTERFACE
many process control applications, necessary provide isolation barrier between controller unit being controlled. Opto-isolators provide voltage isolation excess serial loading structure AD7834 makes ideal opto-isolated interfaces number interface lines kept minimum.
Rev. Page
01006-033
AD7834/AD7835
+15V -15V +15V -15V +15V VREF(+)A VREF(-)A 0.1F VOUT2 -15V VOUT1 DRIVER VOFFSET
AD588
AD78351
VOUT3 VREF(+)B VREF(-)B AGND
AD7834/AD7835 only device requiring AGND DGND connection, then ground planes should connected AGND DGND pins AD7834/ AD7835. AD7834/AD7835 system where multiple devices require AGND DGND connection, connection still made point only, star ground point, which established close possible AD7834/AD7835.
VDUT
AD588
VOUT4
WINDOW COMPARATOR TESTER
01006-035
1ADDITIONAL PINS OMITTED CLARITY
Figure Application
other AD588 provides reference voltage DACs These provide reference voltages window comparator shown Figure this AD588 connected GND. This causes VREF(+)B VREF(-)B referenced GND. input codes vary from 111, VOUT3 VOUT4 vary from with respect GND. also connected When AD7835 cleared, VOUT3 VOUT4 cleared with respect GND. Care must taken ensure that maximum minimum voltage specifications AD7835 reference voltages followed shown Figure
Digital lines running under device must avoided these will couple noise onto die. analog ground plane under AD7834/AD7835 avoid noise coupling. power supply lines AD7834/AD7835 large trace possible provide impedance paths reduce effects glitches power supply line. Shield fast switching signals, such clocks, with digital ground avoid radiating noise other parts board. These signals should never near analog inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This reduces effects feedthrough through board. microstrip method best, always possible with double-sided board. With this method, component side board dedicated ground plane while signal traces placed solder side. AD7834/AD7835 must have ample supply bypassing located close possible package, ideally right against device. Figure shows recommended capacitor values parallel with each supplies. capacitors tantalum bead type. capacitor have Effective Series Resistance (ESR) Effective Series Inductance (ESI), such common ceramic types, which provide impedance path ground high frequencies handle transient currents internal logic switching.
DGND 0.1F 0.1F AGND
POWER SUPPLY BYPASSING GROUNDING
circuit where accuracy important, careful consideration power supply ground return layout helps ensure rated performance. printed circuit board which AD7834/AD7835 mounted should designed analog digital sections separated confined certain areas board. This facilitates ground planes that easily separated. minimum etch technique generally best ground planes since gives best shielding. Digital analog ground planes should joined only place.
AD7834/ AD78351
0.1F
1ADDITIONAL PINS OMITTED CLARITY
01006-036
Figure Power Supply Decoupling
Rev. Page
AD7834/AD7835 OUTLINE DIMENSIONS
18.10 (0.7126) 17.70 (0.6969)
7.60 (0.2992) 7.40 (0.2913)
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10
0.75 (0.0295) 0.25 (0.0098)
1.27 (0.0500) 0.51 (0.0201) SEATING 0.33 (0.0130) PLANE 0.31 (0.0122) 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Figure 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (R-28) Dimensions shown millimeters (inches)
1.565 (39.75) 1.380 (35.05)
0.580 (14.73) 0.485 (12.31)
0.100 (2.54) 0.250 (6.35) 0.200 (5.08) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.005 (0.13)
0.625 (15.88) 0.600 (15.24) 0.195 (4.95) 0.125 (3.17)
0.700 (17.78)
0.015 (0.38) 0.008 (0.20)
COMPLIANT JEDEC STANDARDS MS-011-AB CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN. CORNER LEADS CONFIGURED WHOLE HALF LEADS.
Figure 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown inches (millimeters)
Rev. Page
AD7834/AD7835
0.048 (1.22) 0.042 (1.07) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
0.020 (0.51) 0.021 (0.53) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) BOTTOM VIEW
(PINS
0.048 (1.22) 0.042 (1.07)
IDENTIFIER VIEW
(PINS DOWN)
0.050 (1.27)
0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64)
0.656 (16.66) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40)
0.120 (3.05) 0.090 (2.29)
COMPLIANT JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 44-Lead Plastic Leaded Chip Carrier [PLCC} (P-44A) Dimensions shown inches (millimeters)
1.03 0.88 0.73
2.45
13.90
SEATING PLANE
VIEW 2.10 2.00 1.95 0.25
(PINS DOWN)
10.00
0.23 0.11
VIEW
0.10 COPLANARITY
VIEW
ROTATED
0.80 LEAD PITCH COMPLIANT JEDEC STANDARDS MO-112-AA-1
0.45 0.30 LEAD WIDTH
Figure 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions show millimeters
Rev. Page
AD7834/AD7835
ORDERING GUIDE
Model AD7834AR AD7834AR-REEL AD7834ARZ AD7834ARZ-REEL1 AD7834BR AD7834BR-REEL AD7834BRZ1 AD7834BZR-REEL1 AD7834AN AD7834ANZ1 AD7834BN AD7834BNZ1 AD7835AP AD7835AP-REEL AD7835APZ1 AD7835APZ-REEL1 AD7835AS AD7835AS-REEL AD7835ASZ1 AD7835ASZ-REEL1
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Linearity Error (LSBs)
(LSBs) ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9 ±0.9
Package Description 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead SOIC 28-Lead PDIP 28-Lead PDIP 28-Lead PDIP 28-Lead PDIP 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead-MQFP 44-Lead-MQFP 44-Lead-MQFP 44-Lead-MQFP
Package Option R-28 R-28 R-28 R-28 R-28 R-28 R-28 R-28 N-28-2 N-28-2 N-28-2 N-28-2 P-44A P-44A P-44A P-44A S-44-2 S-44-2 S-44-2 S-44-2
Pb-free part.
Rev. Page
AD7834/AD7835 NOTES
2005 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. C01006-0-7/05(C)
Rev. Page

Four 14-bit DACs package AD7834-serial loading AD7835-parallel 8-bit/1

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