Power Programmable Waveform Generator AD9833 AD9833 power program

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Power Programmable Waveform Generator AD9833 AD9833 power program

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FEATURES Digitally Programmable Frequency Phase Power Consumption 12.5 Output Frequency Range 28-Bit Resolution (0.1 Clock) Sinusoidal/Triangular/Square Wave Outputs Power Supply External Components Required 3-Wire SPI® Interface Extended Temperature Range: +105 Power-Down Option 10-Lead MSOP Package
Power Programmable Waveform Generator AD9833
AD9833 power programmable waveform generator capable producing sine, triangular, square wave outputs. Waveform generation required various types sensing, actuation, time domain reflectometry applications. output frequency phase software programmable, allowing easy tuning. external components needed. frequency registers bits; with clock rate, resolution achieved. Similarly, with clock rate, AD9833 tuned 0.004 resolution. AD9833 written 3-wire serial interface. This serial interface operates clock rates compatible with microcontroller standards. device operates with power supply from AD9833 power-down function (SLEEP). This allows sections device that being used powered down, thus minimizing current consumption part, e.g., powered down when clock output being generated. AD9833 available 10-lead MSOP package.
APPLICATIONS Frequency Stimulus/Waveform Generation Liquid Flow Measurement Sensory Applications-Proximity, Motion, Defect Detection Line Loss/Attenuation Test Medical Equipment Sweep/Clock Generators
FUNCTIONAL BLOCK DIAGRAM
AGND DGND CAP/2.5V
MCLK AVDD/ DVDD
REGULATOR
ON-BOARD REFERENCE FULL-SCALE CONTROL COMP
2.5V
FREQ0
FREQ1
PHASE ACCUMULATOR (28-BIT)
10-BIT
PHASE0 PHASE1
DIVIDE VOUT
CONTROL REGISTER
SERIAL INTERFACE CONTROL LOGIC
AD9833
FSYNC
SCLK
SDATA
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD9833-SPECIFICATIONS*
Parameter SIGNAL SPECIFICATIONS Resolution Update Rate VOUT VOUT VOUT Accuracy Integral Nonlinearity Differential Nonlinearity SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wideband Nyquist) Narrow Band kHz) Clock Feedthrough Wake-Up Time LOGIC INPUTS VINH, Input High Voltage VINL, Input Voltage IINH/IINL, Input Current CIN, Input Capacitance POWER SUPPLIES Power Sleep Mode
(VDD AGND DGND TMIN TMAX, RSET VOUT, unless otherwise noted.)
0.65 Unit Bits MSPS ppm/C
Test Conditions/Comments
fMCLK MHz, fOUT fMCLK/4096 fMCLK MHz, fOUT fMCLK/4096 fMCLK MHz, fOUT fMCLK/50 fMCLK MHz, fOUT fMCLK/50
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
fMCLK MHz, fOUT fMCLK/4096 Code Dependent. Powered Down, MCLK Running
*Operating temperature range follows: Version: -40C +105C; typical specifications 25C. Specifications subject change without notice.
100nF 10nF CAP/2.5V COMP
REGULATOR
VOUT 10-BIT 20pF
AD9833
Figure Test Circuit Used Test Specifications
REV.
AD9833 TIMING CHARACTERISTICS* (VDD AGND DGND unless otherwise noted.)
Parameter Limit TMIN TMAX Unit Test Conditions/Comments MCLK Period MCLK High Duration MCLK Duration SCLK Period SCLK High Duration SCLK Duration FSYNC SCLK Falling Edge Setup Time FSYNC SCLK Hold Time Data Setup Time Data Hold Time SCLK High FSYNC Falling Edge Setup Time
*Guaranteed design, production tested. Specifications subject change without notice.
MCLK
Figure Master Clock
SCLK
FSYNC
SDATA
Figure Serial Timing
REV.
AD9833
ABSOLUTE MAXIMUM RATINGS*
25C, unless otherwise noted.)
AGND -0.3 DGND -0.3 AGND DGND -0.3 +0.3 CAP/2.5 2.75 Digital Voltage DGND -0.3 Analog Voltage AGND -0.3 Operating Temperature Range Industrial Version) -40C +105C Storage Temperature Range -65C +150C Maximum Junction Temperature 150C
MSOP Package Thermal Impedance 206C/W Thermal Impedance 44C/W Lead Temperature, Soldering sec) 300C Reflow, Peak Temperature 220C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD9833BRM AD9833BRM-REEL AD9833BRM-REEL7 EVAL-AD9833EB
Temperature Range -40C +105C -40C +105C -40C +105C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board
Package Option RM-10 RM-10 RM-10
Branding
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9833 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
REV.
AD9833
CONFIGURATION
COMP CAP/2.5V
VOUT
AD9833
AGND
FSYNC VIEW DGND (Not Scale) SCLK
MCLK
SDATA
FUNCTION DESCRIPTIONS
Number Power Supply
Mnemonic
Function Positive Power Supply Analog Digital Interface Sections. on-board regulator also supplied from VDD. have value from decoupling capacitor should connected between AGND. digital circuitry operates from power supply. This generated from using on-board regulator (when exceeds regulator requires decoupling capacitor typically which connected from CAP/2.5 DGND. equal less than CAP/2.5 should tied directly VDD. Digital Ground. Analog Ground. Bias Pin. This used decoupling bias voltage. Voltage Output. analog digital output from AD9833 available this pin. external load resistor required because device resistor board. Digital Clock Input. output frequencies expressed binary fraction frequency MCLK. output frequency accuracy phase noise determined this clock. Serial Data Input. 16-bit serial data-word applied this input. Serial Clock Input. Data clocked into AD9833 each falling SCLK edge. Active Control Input. This frame synchronization signal input data. When FSYNC taken low, internal logic informed that word being loaded into device.
CAP/2.5
Analog Signal Reference
DGND AGND COMP VOUT
Digital Interface Control
MCLK
SDATA SCLK FSYNC
REV.
AD9833-Typical Performance Characteristics
(mA)
AVDD
(mA)
SFDR (dBc)
SFDR MCLK/7 SFDR MCLK/50
100k
MCLK FREQUENCY (MHz)
MCLK (MHz)
fOUT (Hz)
Typical Current Consumption MCLK Frequency
Typical fOUT fMCLK
Narrow-Band SFDR MCLK Frequency
SFDR (dB)
fOUT MCLK/4096
SFDR (dBc)
SFDR MCLK/7
MCLK 18MHz MCLK 1MHz
(dB)
MCLK 10MHz
SFDR MCLK/50
MCLK 25MHz
12.5 MCLK FREQUENCY (MHz)
0.001
0.01
MCLK FREQUENCY (MHz)
fOUT/f MCLK
Wideband SFDR MCLK Frequency
Wideband SFDR fOUT/fMCLK Various MCLK Frequencies
MCLK Frequency
1000 WAKE-UP TIME TEMPERATURE
VREFOUT
1.250 UPPER RANGE
1.225
2.3V
1.200
5.5V
1.175 LOWER RANGE 1.150
1.125 1.100
TEMPERATURE
Wake-Up Time Temperature
VREFOUT Temperature
REV.
AD9833
-100
FREQUENCY (Hz)
100k
-100
FREQUENCY (Hz)
-100
FREQUENCY (Hz)
fMCLK MHz, fOUT kHz, Frequency Word 000FBA9
fMCLK MHz, fOUT 1.43 fMCLK/7, Frequency Word 2492492
fMCLK MHz, fOUT 3.33 fMCLK/3, Frequency Word 5555555
100k -100
-100
-100
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
12.5M
fMCLK MHz, fOUT kHz, Frequency Word 000FBA9
fMCLK MHz, fOUT kHz, Frequency Word 009D495
fMCLK MHz, fOUT kHz, Frequency Word 0624DD3
12.5M
-100
-100
FREQUENCY (Hz) 12.5M
-100
FREQUENCY (Hz)
FREQUENCY (Hz)
12.5M
fMCLK MHz, fOUT MHz, Frequency Word 189374D
fMCLK MHz, fOUT 3.857 fMCLK/7, Frequency Word 2492492
fMCLK MHz, fOUT 8.333 fMCLK/3, Frequency Word 5555555
REV.
AD9833
TERMINOLOGY Integral Nonlinearity THEORY OPERATION
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition (000 01), full scale, point above last code transition (111 11). error expressed LSBs.
Differential Nonlinearity
Sine waves typically thought terms their magnitude form a(t) sin( However, these nonlinear easy generate except through piecewise construction. other hand, angular information linear nature. That phase angle rotates through fixed angle each unit time. angular rate depends frequency signal traditional rate
MAGNITUDE
This difference between measured ideal change between adjacent codes DAC. specified differential nonlinearity maximum ensures monotonicity.
Output Compliance
output compliance refers maximum voltage that generated output meet specifications. When voltages greater than that specified output compliance generated, AD9833 meet specifications listed data sheet.
Spurious-Free Dynamic Range
PHASE
Along with frequency interest, harmonics fundamental frequency images these frequencies present output device. spurious-free dynamic range (SFDR) refers largest spur harmonic present band interest. wideband SFDR gives magnitude largest harmonic spur relative magnitude fundamental frequency Nyquist bandwidth. narrow-band SFDR gives attenuation largest spur harmonic bandwidth about fundamental frequency.
Total Harmonic Distortion
Figure Sine Wave
Knowing that phase sine wave linear given reference interval (clock period), phase rotation that period determined. DPhase Solving DPhase Solving substituting reference clock frequency reference period MCLK DPhase MCLK AD9833 builds output based this simple equation. simple chip implement this equation with three major subcircuits: numerically controlled oscillator phase modulator, ROM, digital-to-analog converter. Each these subcircuits discussed following section.
CIRCUIT DESCRIPTION
Total harmonic distortion (THD) ratio harmonics value fundamental. AD9833, defined
where amplitude fundamental amplitudes second through sixth harmonics.
Signal-to-Noise Ratio (SNR)
ratio value measured output signal other spectral components below Nyquist frequency. value expressed decibels.
Clock Feedthrough
There will feedthrough from MCLK input analog output. Clock feedthrough refers magnitude MCLK signal relative fundamental frequency AD9833's output spectrum.
AD9833 fully integrated direct digital synthesis (DDS) chip. chip requires reference clock, precision resistor, decoupling capacitors provide digitally created sine waves 12.5 MHz. addition generation this signal, chip fully capable broad range simple complex modulation schemes. These modulation schemes fully implemented digital domain, allowing accurate simple realization complex modulation algorithms using techniques. internal circuitry AD9833 consists following main sections: numerically controlled oscillator (NCO), frequency phase modulators, ROM, digital-to-analog converter, regulator.
REV.
AD9833
Numerically Controlled Oscillator Plus Phase Modulator Regulator
This consists frequency select registers, phase accumulator, phase offset registers, phase offset adder. main component 28-bit phase accumulator. Continuous time signals have phase range Outside this range numbers, sinusoid functions repeat themselves periodic manner. digital implementation different. accumulator simply scales range phase numbers into multibit digital word. phase accumulator AD9833 implemented with bits. Therefore, AD9833, 228. Likewise, Phase term scaled into this range numbers Phase With these substitutions, previous equation becomes
Phase MCLK
provides power supply required analog section digital section AD9833. This supply have value internal digital section AD9833 operated on-board regulator steps down voltage applied When applied voltage AD9833 equal less than CAP/2.5 pins should tied together, thus bypassing on-board regulator.
FUNCTIONAL DESCRIPTION Serial Interface
AD9833 standard 3-wire serial interface that compatible with SPI®, QSPITM, MICROWIRETM, interface standards. Data loaded into device 16-bit word under control serial clock input, SCLK. timing diagram this operation given Figure FSYNC input level triggered input that acts frame synchronization chip enable. Data transferred into device only when FSYNC low. start serial data transfer, FSYNC should taken low, observing minimum FSYNC SCLK falling edge setup time, After FSYNC goes low, serial data will shifted into device's input shift register falling edges SCLK clock pulses. FSYNC taken high after 16th falling edge SCLK, observing minimum SCLK falling edge FSYNC rising edge time, Alternatively, FSYNC kept multiple SCLK pulses then brought high data transfer. this way, continuous stream 16-bit words loaded while FSYNC held low, FSYNC only going high after 16th SCLK falling edge last word loaded. SCLK continuous, alternatively SCLK idle high between write operations must high when FSYNC goes (t11).
Powering AD9833
where Phase input phase accumulator selected either from FREQ0 register FREQ1 register, controlled FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding output discontinuity when switching between frequencies. Following NCO, phase offset added perform phase modulation using 12-bit phase registers. contents these phase registers added most significant bits NCO. AD9833 phase registers; their resolution /4096.
make output from useful, must converted from phase information into sinusoidal value. Since phase information maps directly into amplitude, uses digital phase information address look-up table converts phase information into amplitude. Although contains 28-bit phase accumulator, output truncated bits. Using full resolution phase accumulator impractical unnecessary, this would require look-up table entries. necessary only have sufficient phase resolution such that errors truncation smaller than resolution 10-bit DAC. This requires that have bits phase resolution more than 10-bit DAC. enabled using MODE (D1) control register. This explained further Table
Digital-to-Analog Converter
AD9833 includes high impedance current source 10-bit DAC. receives digital words from converts them into corresponding analog voltages. configured single-ended operation. external load resistor required since device resistor board. generates output voltage typically p-p.
flow chart Figure shows operating routine AD9833. When AD9833 powered part should reset. This will reset appropriate internal registers zero provide analog output midscale. avoid spurious outputs while AD9833 being initialized, RESET should until part ready begin generating output. RESET does reset phase, frequency, control registers. These registers will contain invalid data, therefore should known value user. RESET should then begin generating output. data will appear output eight MCLK cycles after RESET
Latency
Associated with each asynchronous write operation AD9833 latency. selected frequency/phase register loaded with word, there delay seven eight MCLK cycles before analog output will change. (There uncertainty MCLK cycle, depends position MCLK rising edge when data loaded into destination register.)
REV.
AD9833
Control Register
AD9833 contains 16-bit control register that sets AD9833 user wants operate control bits, except MODE, sampled internal negative edge MCLK. Table describes individual bits control register. different functions various output options from AD9833 described more detail section following Table
SLEEP12 SLEEP1
inform AD9833 that contents control register will altered, must shown below.
Table Control Register
CONTROL BITS
AD9833
(LOW POWER) 10-BIT
RESET
PHASE ACCUMULATOR (28-BIT)
MODE OPBITEN DIVIDE DIV2 OPBITEN
DIGITAL OUTPUT (ENABLE)
VOUT
DB15 DB14 DB13 DB12 DB11 DB10 FSELECT PSELECT RESET SLEEP1 SLEEP12 OPBITEN DIV2 MODE
Figure Function Control Bits
Table Description Bits Control Register Name Function
FSELECT PSELECT Reserved RESET SLEEP1
write operations required load complete word into either frequency registers. allows complete word loaded into frequency register consecutive writes. first write contains LSBs frequency word, next write will contain MSBs. first bits each 16-bit word define frequency register which word loaded should, therefore, same both consecutive writes. Refer Table appropriate addresses. write frequency register occurs after both words have been loaded, register never holds intermediate value. example complete 28-bit write shown Table When 28-bit frequency register operates 14-bit registers, containing MSBs other containing LSBs. This means that MSBs frequency word altered independent LSBs, vice versa. alter MSBs LSBs, single write made appropriate frequency address. control (HLB) informs AD9833 whether bits altered MSBs LSBs. This control allows user continuously load MSBs LSBs frequency register while ignoring remaining bits. This useful complete 28-bit resolution required. used conjunction with (B28). This control indicates whether bits being loaded being transferred MSBs LSBs addressed frequency register. (B28) must able change MSBs LSBs frequency word separately. When (B28) this control ignored. allows write MSBs addressed frequency register. allows write LSBs addressed frequency register. FSELECT defines whether FREQ0 register FREQ1 register used phase accumulator. PSELECT defines whether PHASE0 register PHASE1 register data added output phase accumulator. This should RESET resets internal registers which corresponds analog output midscale. RESET disables RESET. This function explained further Table When SLEEP1 internal MCLK clock disabled, output will remain present value longer accumulating. When SLEEP1 MCLK enabled. This function explained further Table
-10-
REV.
AD9833
Table Description Bits Control Register (continued) Name SLEEP12 Function SLEEP12 powers down on-chip DAC. This useful when AD9833 used output data. SLEEP12 implies that active. This function explained further Table function this bit, association with (MODE), control what output VOUT pin. This explained further Table When OPBITEN output longer available VOUT pin. Instead, MSB/2) data connected VOUT pin. This useful coarse clock source. DIV2 controls whether MSB/2 that output. When OPBITEN connected VOUT. MODE determines whether sinusoidal ramp output that available. This must DIV2 used association with (OPBITEN). This explained further Table When DIV2 data passed directly VOUT pin. When DIV2 MSB/2 data output VOUT pin. This must This used association with OPBITEN (D5). function this control what output VOUT when on-chip connected VOUT. This should control OPBITEN This explained further Table When MODE bypassed, resulting triangle output from DAC. When MODE used convert phase information into amplitude information, which results sinusoidal signal output. This must
OPBITEN
Reserved DIV2
Reserved MODE
Reserved
Frequency Phase Registers
analog output from AD9833 MCLK /228 FREQREG where FREQREG value loaded into selected frequency register. This signal will phase shifted 4096 PHASEREG where PHASEREG value contained selected phase register. Consideration must given relationship selected output frequency reference clock frequency avoid unwanted output anomalies. flow chart Figure shows routine writing frequency phase registers AD9833.
Writing Frequency Register
AD9833 contains frequency registers phase registers, which described Table III.
Table III. Frequency/Phase Registers
Register Size FREQ0
Description
Bits Frequency Register When FSELECT this register defines output frequency fraction MCLK frequency. Bits Frequency Register When FSELECT this register defines output frequency fraction MCLK frequency.
FREQ1
PHASE0 Bits Phase Offset Register When PSELECT contents this register added output phase accumulator. PHASE1 Bits Phase Offset Register When PSELECT contents this register added output phase accumulator.
When writing frequency register, Bits give address frequency register.
Table Frequency Register Bits
FREQ0 Bits FREQ1 Bits
REV.
-11-
AD9833
user wants change entire contents frequency register, consecutive writes same address must performed since frequency registers bits wide. first write will contain LSBs, while second write will contain MSBs. this mode operation, control (D13) should example 28-bit write shown Table
Table Writing 00FC00 FREQ0 RESET Function
RESET function resets appropriate internal registers provide analog output midscale. RESET does reset phase, frequency, control registers. When AD9833 powered part should reset. reset AD9833, RESET take part reset, signal will appear output eight MCLK cycles after RESET
Table Applying RESET
SDATA Input 0010 0000 0000 0000 0100 0000 0000 0000 0100 0000 0011 1111
Result Input Word Control Word Write (D15, 00), (D13) (D12) FREQ0 Write (D15, 01), LSBs 0000 FREQ0 Write (D15, 01), MSBs 003F RESET
SLEEP Function
Result Reset Applied Internal Registers Reset
some applications, user does need alter bits frequency register. With coarse tuning, only MSBs altered, while with fine tuning, only LSBs altered. setting control (D13) 28-bit frequency register operates two, 14-bit registers, containing MSBs other containing LSBs. This means that MSBs frequency word altered independent LSBs, vice versa. (D12) control register identifies which bits being altered. Examples this shown Tables VII.
Table Writing 3FFF LSBs FREQ1
Sections AD9833 that powered down minimize power consumption. This done using SLEEP function. parts chip that powered down internal clock DAC. bits required SLEEP function outlined Table
Table Applying SLEEP Function
SLEEP1 SLEEP12 Result Power-Down Powered Down Internal Clock Disabled Both Powered Down Internal Clock Disabled
SDATA Input 0000 0000 0000 0000
Result Input Word Control Word Write (D15, 00), (D13) (D12) i.e. LSBs FREQ1 Write (D15, 10), LSBs 3FFF
Powered Down
1011 1111 1111 1111
This useful when AD9833 used output data only. this case, required powered down reduce power consumption.
Internal Clock Disabled
Table VII. Writing 00FF MSBs FREQ0
SDATA Input
Result Input Word
0001 0000 0000 0000 Control Word Write (D15, 00), (D13) (D12) i.e., MSBs 0100 0000 1111 1111 FREQ0 Write (D15, 01), MSBs 00FF
Writing Phase Register
When internal clock AD9833 disabled, output will remain present value longer accumulating. frequency, phase, control words written part when SLEEP1 control active. synchronizing clock still active, which means that selected frequency phase registers also changed using control bits. Setting SLEEP1 enables MCLK. changes made registers while SLEEP1 active will seen output after certain latency.
VOUT
When writing phase register, Bits identifies which phase register being loaded.
Table VIII. Phase Register Bits
AD9833 offers variety outputs from chip, which available from VOUT pin. choice outputs data, sinusoidal output, triangle output. OPBITEN (D5) MODE (D1) bits control register used decide which output available from AD9833. This explained further below also Table
PHASE0 Bits PHASE1 Bits
data output from AD9833. setting OPBITEN (D5) control data available VOUT pin. This useful coarse clock source. This square wave also divided before being output. DIV2 (D3) control register controls frequency this output from VOUT pin.
-12-
REV.
AD9833
Sinusoidal Output
used convert phase information from frequency phase registers into amplitude information that results sinusoidal signal output. have sinusoidal output from VOUT pin, MODE (D1) OPBITEN (D5)
Triangle Output
AD9833 also suitable signal generator applications. Because data available VOUT pin, device used generate square wave. With current consumption, part suitable applications which used local oscillator.
GROUNDING LAYOUT
bypassed that truncated digital output from sent DAC. this case, output longer sinusoidal. will produce 10-bit linear triangular function. have triangle output from VOUT pin, MODE (D1) Note that SLEEP12 must (i.e., enabled) when using this pin.
Table Various Outputs from VOUT
OPBITEN
VOUT
MODE DIV2 VOUT Sinusoid Triangle Data MSB/2 Data Reserved
printed circuit board that houses AD9833 should designed that analog digital sections separated confined certain areas board. This facilitates ground planes that separated easily. minimum etch technique generally best ground planes since gives best shielding. Digital analog ground planes should joined place only. AD9833 only device requiring AGND DGND connection, then ground planes should connected AGND DGND pins AD9833. AD9833 system where multiple devices require AGND DGND connections, connection should made point only, star ground point that should established close possible AD9833. Avoid running digital lines under device these will couple noise onto die. analog ground plane should allowed under AD9833 avoid noise coupling. power supply lines AD9833 should large track possible provide impedance paths reduce effects glitches power supply line. Fast switching signals, such clocks, should shielded with digital ground avoid radiating noise other sections board. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough through board. microstrip technique best always possible with double-sided board. this technique, component side board dedicated ground planes, while signals placed other side. Good decoupling important. AD9833 should have supply bypassing ceramic capacitors parallel with tantalum capacitors. achieve best from decoupling capacitors, they should placed close possible device, ideally right against device. Proper operation comparator requires good layout strategy. strategy must minimize through proper layout parasitic capacitance between SIGN adding isolation using ground plane. example, 4-layer board, signal could connected layer SIGN connected bottom layer, that isolation provided power ground planes between.
VOUT
Figure Triangle Output
APPLICATIONS
Because various output options available from part, AD9833 configured suit wide variety applications. areas where AD9833 suitable modulation applications. part used perform simple modulation, such FSK. More complex modulation schemes, such GMSK QPSK, also implemented using AD9833. application, frequency registers AD9833 loaded with different values. frequency will represent space frequency, while other will represent mark frequency. Using FSELECT control register AD9833, user modulate carrier frequency between values. AD9833 phase registers; this enables part perform PSK. With phase shift keying, carrier frequency phase shifted, phase being altered amount that related stream being input modulator.
REV.
-13-
AD9833
DATA WRITE FIGURE
SELECT DATA SOURCES
WAIT MCLK CYCLES
INITIALIZATION FIGURE BELOW
OUTPUT VOUT VREF RLOAD/R (SIN(2 (FREQREG
fMCLK
/228 PHASEREG/212))))
CHANGE PHASE? CHANGE FSELECT? CHANGE FREQUENCY REGISTER? CONTROL REGISTER WRITE (SEE TABLE CHANGE OUTPUT DIGITAL SIGNAL? CHANGE FREQUENCY? CHANGE OUTPUT FROM RAMP?
CHANGE PSELECT? CHANGE PHASE REGISTER?
Figure Flow Chart AD9833 Initialization Operation
INITIALIZATION
APPLY RESET
(CONTROL REGISTER WRITE) RESET
WRITE FREQUENCY PHASE REGISTERS FREQ0 FOUT0 MCLK FREQ1 FOUT1 MCLK PHASE0 PHASE1 (PHASESHIFT 212) (SEE FIGURE
RESET SELECT FREQUENCY REGISTERS SELECT PHASE REGISTERS
(CONTROL REGISTER WRITE) RESET FSELECT SELECTED FREQUENCY REGISTER PSELECT SELECTED PHASE REGISTER
Figure Initialization
-14-
REV.
AD9833
DATA WRITE
WRITE FULL 28-BIT WORD FREQUENCY REGISTER? (CONTROL REGISTER WRITE) (D13)
WRITE MSBs LSBs FREQUENCY REGISTER?
WRITE PHASE REGISTER?
(CONTROL REGISTER WRITE) (D13) (D12) (16-BIT WRITE) D15, (CHOOSE PHASE REGISTER) PHASE DATA
WRITE CONSECUTIVE 16-BIT WORDS (SEE TABLE EXAMPLE)
WRITE 16-BIT WORD (SEE TABLES EXAMPLES)
WRITE ANOTHER FULL 28-BIT WORD FREQUENCY REGISTER?
WRITE 14MSBs LSBs FREQUENCY REGISTER?
WRITE ANOTHER PHASE REGISTER?
Figure Data Writes
INTERFACING MICROPROCESSORS
AD9833 standard serial interface that allows part interface directly with several microprocessors. device uses external serial clock write data/control information into device. serial clock have frequency maximum. serial clock continuous, idle high between write operations. When data/control information being written AD9833, FSYNC taken held while bits data being written into AD9833. FSYNC signal frames bits information being loaded into AD9833.
AD9833 ADSP-21xx Interface
ADSP-2101/ ADSP-2103*
AD9833*
SCLK
FSYNC SDATA SCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure ADSP-2101/ADSP-2103 AD9833 Interface
AD9833 68HC11/68L11 Interface
Figure shows serial interface between AD9833 ADSP-21xx. ADSP-21xx should operate SPORT transmit alternate framing mode (TFSW ADSP-21xx programmed through SPORT control register should configured follows: Internal clock operation (ISCLK Active framing (INVTFS 16-bit word length (SLEN Internal frame sync signal (ITFS Generate frame sync each write (TFSR Transmission initiated writing word register after SPORT been enabled. data clocked each rising edge serial clock clocked into AD9833 SCLK falling edge.
Figure shows serial interface between AD9833 68HC11/68L11 microcontroller. microcontroller configured master setting MSTR SPCR This provides serial clock while MOSI output drives serial data line SDATA. Since microcontroller does have dedicated frame sync pin, FSYNC signal derived from port line (PC7). setup conditions correct operation interface follows: idles high between write operations (CPOL Data valid falling edge (CPHA When data being transmitted AD9833, FSYNC line taken (PC7). Serial data from 68HC11/68L11 transmitted 8-bit bytes with only eight falling clock edges occurring transmit cycle. Data transmitted first. order load data into AD9833, held after first bits transferred, second serial write operation performed AD9833. Only after second bits have been transferred should FSYNC taken high again.
REV.
-15-
AD9833
68HC11/68L11*
AD9833*
DSP56002*
AD9833*
MOSI
FSYNC SDATA SCLK
FSYNC SDATA SCLK
*ADDITIONAL PINS OMITTED CLARITY
*ADDITIONAL PINS OMITTED CLARITY
Figure 68HC11/68L11 AD9833 Interface
AD9833 80C51/80L51 Interface
Figure DSP56002 AD9833 Interface
AD9833 EVALUATION BOARD
Figure shows serial interface between AD9833 80C51/80L51 microcontroller. microcontroller operated mode that 80C51/80L51 drives SCLK AD9833, while drives serial data line SDATA. FSYNC signal again derived from programmable port (P3.3 being used diagram). When data transmitted AD9833, P3.3 taken low. 80C51/80L51 transmits data 8-bit bytes, thus only eight falling SCLK edges occur each cycle. load remaining bits AD9833, P3.3 held after first bits have been transmitted, second write operation initiated transmit second byte data. P3.3 taken high following completion second write operation. SCLK should idle high between write operations. 80C51/80L51 outputs serial data format that first. AD9833 accepts first (the MSBs being control information, next bits being address, while LSBs contain data when writing destination register). Therefore, transmit routine 80C51/80L51 must take this into account rearrange bits that output first.
80C51/80L51*
AD9833 Evaluation Board allows designers evaluate high performance AD9833 modulator with minimum effort. prove that this device will meet user's waveform synthesis requirements, user requires only power supply, IBM® compatible spectrum analyzer along with evaluation board. evaluation includes populated, tested AD9833 printed circuit board. evaluation board interfaces parallel port compatible Software available with evaluation board that allows user easily program AD9833. schematic evaluation board shown Figure software will compatible that Microsoft Windows® Windows Windows Windows 2000 installed.
Using AD9833 Evaluation Board
AD9833*
AD9833 evaluation test system designed simplify evaluation AD9833. application note also available with evaluation board gives full information operating evaluation board.
Prototyping
P3.3
FSYNC SDATA SCLK
area available evaluation board user additional circuits evaluation test set. Users want build custom analog filters output buffers operational amplifiers used final application.
External Clock
*ADDITIONAL PINS OMITTED CLARITY
Figure 80C51/80L51 AD9833 Interface
AD9833 DSP56002 Interface
AD9833 operate with master clocks MHz. oscillator included evaluation board. However, this oscillator removed and, required, external CMOS clock connected part.
Power Supply
Figure shows interface between AD9833 DSP56002. DSP56002 configured normal mode asynchronous operation with gated internal clock (SYN SCKD frame sync generated internally (SC2 transfers bits wide (WL1 frame sync signal will frame bits (FSL frame sync signal available SC2, needs inverted before being applied AD9833. interface DSP56000/DSP56001 similar that DSP56002.
Power AD9833 evaluation board must provided externally through connections. power leads should twisted reduce ground loops.
-16-
REV.
AD9833
SCLK SDATA FSYNC DVDD SCLK SDATA FSYNC COMP 0.01 DVDD
DVDD SCLK SDATA FSYNC
MCLK DVDD DVDD
AD9833
MCLK VOUT VOUT
DGND
AGND
DGND
Figure Evaluation Board Layout
Integrated Circuits
Capacitors
AD9833BRU 74HCT244 XTAL Ceramic Capacitor 0805 Ceramic Capacitor Option Extra Decoupling Capacitor Ceramic Capacitor Tantalum Capacitor Resistor 2-Pin Header Subminiature Connector 36-Pin Edge Connector Mounting Terminal Block
C10,
Resistor
Links
LK1,
Sockets
MCLK VOUT
Connectors
REV.
-17-
AD9833
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP] (RM-10)
Dimensions shown millimeters
3.00
3.00
4.90
0.50 0.95 0.85 0.75 0.15 0.27 0.17 1.10 0.23 0.08 SEATING PLANE 0.80 0.40
COPLANARITY 0.10 COMPLIANT JEDEC STANDARDS MO-187BA
-18-
REV.
AD9833 Revision History
Location 6/03-Data Sheet changed from REV. REV. Page
Updated ORDERING GUIDE
REV.
-19-
-20-
C02704-0-6/03(A)

Power Programmable Waveform Generator AD9833 AD9833 power program

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